FlashFlex MCU SST89C58RC

Transcription

1 Introduction This document provides the instructions to help programming vendors qualify SST FlashFlex microcontrollers. Functional Blocks 051 CPU Core ALU, ACC, B-Register, Instruction Register, Program Counter, Oscillator Timing and Control Interrupt Control 9 Interrupts Watchdog Timer Flash Control Unit SuperFlash EEPROM Primary Partition 32 x8 Secondary Partition 2 x8 Security Lock RAM 1 x8 I/O Port 0 I/O Port 1 I/O Port I/O I/O I/O Timer 0 (16-bit) I/O Port 3 8 I/O Timer 1 (16-bit) BOR Timer 2 (16-bit) Enhanced SMBus 0 8-bit Enhanced UART Enhanced SMBus (02) B1.0 Figure 1: Functional Block Diagram 1

2 Flash Memory Programming The device internal flash memory can be programmed or erased using the External Host Programming mode. External Host Programming Mode External host programming mode allows the user to program the flash memory directly without using the CPU. External host mode is entered by forcing ALE from a logic high to a logic low while RST input is being held continuously high. The device will stay in External Host mode as long as RST = 1, EA# = 1, ALE = 0, P3.0 = 1, and P3.1 = 1. A Read-ID operation is necessary to arm the device in External Host mode, and no other commands can be enabled until a Read-ID is performed. In this mode, the internal flash memory partitions are accessed through the re-assigned I/O port pins by an external host, such as a MCU programmer, a PCB tester, or a PC-controlled development board. See Figure 2 for details. When using the Verify command, P3.6 acts as the output enable signal. See Table 1 for more information about the External Host Programming mode commands. Table 1: External Host Mode Commands 1,2 (1 of 2) P3.2 P3.4 Operation RST PSEN# PROG #/ALE EA# P3.5 P3.7 P2[7:0] P1[7:0] P0[7:0] P3.0 P3.1 P3.6 3 Read ID V IH V IH V IL V IH 00 AH AL DO Chip Erase V IH V IL V IH 01 XX XX XX Partition 0 Erase V IH V IL V IH 0D XX XX XX Sector Erase V IH V IL V IH 0B AH AL XX Byte Programming V IH V IL V IH 0E AH AL DI Byte Verify (Read) 5 V IH V IH V IL V IH 0C AH AL DO 1 0 RD_E N Secure-Page0 V IH V IL V IH XX XX Secure-Page1 V IH V IL V IH XX XX Secure-Page2 V IH V IL V IH XX XX Secure-Page3 V IH V IL V IH XX XX Secure-Page4 V IH V IL V IH XX XX Disable-Extern-IAP V IH V IL V IH 05 B0 XX XX Disable-Extern-Boot V IH V IL V IH 05 B1 XX XX Disable-Extern-MOVC V IH V IL V IH 05 B2 XX XX Disable-Extern-Host- V IH V IL V IH 05 B3 XX XX Cmd Enable-Clock-Double V IH V IL V IH 08 E0 XX XX Boot-From-User-Vector V IH V IL V IH 08 E1 XX XX Boot-From-Zero V IH V IL V IH 08 E2 XX XX Set-User-Boot-Vector V IH V IL V IH 09 F0 XX DO

3 Table 1: External Host Mode Commands 1,2 (Continued) (2 of 2) P3.2 P3.4 PROG P3.5 Operation RST PSEN# #/ALE EA# P3.7 P2[7:0] P1[7:0] P0[7:0] P3.0 P3.1 P3.6 3 Select Partition 0 V IH V IL V IH 05 D0 XX XX Select Partition 1 V IH V IL V IH 05 D1 XX XX T0-0.0 DS External Host programming mode is guaranteed at 25 C (room temperature) only 2. V IL = Input Low Voltage; V IH = Input High Voltage; X = Don t care; AL = Address low order byte; AH = Address high order byte; DI = Data Input; DO = Data Output. 3. P3.6=RD_EN for Byte Verify 4. Symbol signifies a negative pulse and the command is asserted during the low state of PROG#/ALE input. All other combinations of the above input pins are invalid and may result in unexpected behaviors. 5. For Byte-Verify, the P3.6 is used as a Read-Enable control signal. V SS V DD RST Flash Control Signals 1 0 Ready/Busy# Input / Output Enable Port 3 Port 0 Port Input/Output Data Bus Address Bus A 15 -A 8 Port Address Bus A 7 -A 0 EA# ALE/PROG# PSEN# 1337(02) F12.0 Figure 2: I/O Pin Assignments for External Host Mode Product Identification The Read-ID command accesses the signature bytes that identify the device and the manufacturer as SST. External programmers primarily use these signature bytes in the selection of programming algorithms. The Read-ID command is selected by the command code of 0H on P3[2], P3[4:5], and P3[7]. See Figure 3 for timing waveforms. Table 2: Product Identification Address Data Manufacturer s ID 30H BFH Device ID 31H F7H Device ID (Extended) 32h A0H T0-0.0 DS

4 Arming Command An arming command sequence must take place before any external host mode sequence command is recognized by the device. This prevents accidental triggering of external host mode commands due to noise or programmer error. The arming command is as follows: 1. RST, PSEN, EA, and ALE are held High. P3.1 and P3.6 are held LOW, and P3.0 is held High. 2. ALE goes Low and P3.3 (RD/BY#) is held to Low. This enters the device into external host mode, reconfigures the pins, and turns off the on-chip oscillator. 3. A Read-ID command is issued, and after 1 ms the external host mode commands can be issued. After the above sequence, all other external host mode commands are enabled. Before the Read-ID command is received, all other external host mode commands received are ignored. External Host Mode Commands The external host mode commands are: Read ID (detailed in Section, Product Identification ) Chip-Erase Partition0-Erase Sector-Erase Byte-Program Byte-Verify (Read) Secure-Page0 Secure-Page1 Secure-Page2 Secure-Page3 Secure-Page4 Disable-External-IAP Disable-External-Boot Disable-External-MOVC Disable-External-Host-Cmd Enable-Clock-Double Boot-From-User-Vector Boot-From-Zero Set-User-Boot-Vector Select Partition 0 Select Partition 1 See Table 1 for all signal logic assignments, Figure 2 for I/O pin assignments, and Table 5 for the timing parameters. The critical timing for all Erase and Program commands is generated by an on-chip flash memory controller. The high-to-low transition of the PSEN# signal initiates the Erase or Program commands, which are synchronized internally. The Read commands are asynchronous reads, independent of the PSEN# signal level. 4

5 The Chip-Erase, Partition0-Erase, and Sector-Erase commands are used for erasing all or part of the memory array. Erased data bytes in the memory array will be erased to FFH. Memory locations that are to be programmed must be in the erased state prior to programming. Chip-Erase ignores the Security setting status and will erase all settings on all pages and the different chip-level security restrictions, returning the device to its unlocked state. The Chip-Erase command will also erase the boot vector setting. Upon completion of Chip-Erase command, the chip will boot from the default settings See Table 3 for the default boot vector setting and Figure 4 for timing waveforms. Table 3: Default Boot Vector Setting Device Address 0F800H T0-0.0 DS25101 The Partition0-Erase command erases all bytes in Partition0. See Figure 3-3 for timing waveforms. The Sector-Erase command erases all of the bytes in the selected sector. The sector size for the flash memory is 128 Bytes. This command will not be executed if the Security lock is enabled. See Figure 4 for timing waveforms. The Byte-Program command is used for programming new data into the memory array. This command will be disabled if any security locks are enabled. See Figure 4 for timing waveforms. The Byte-Verify command allows the user to verify that the device correctly performed an Erase or Program command. This command will be disabled if any security locks are enabled. See Figure 5 for timing waveforms. The Secure-Page0, Secure-Page1, Secure-Page2, Secure-Page3, and Secure-Page4 commands program the security bit of each individual page. Once programmed, these bits can be erased using a Chip-Erase command for Secure-Page0-4. Partition0-Erase will erase Secure-Page0-3. See Figure 5 for timing waveforms. The Disable-Extern-IAP, Disable-Extern-Boot, Disable-Extern-MOVC, Disable-Extern-Host-Cmd, Enable-Clock-Double, Boot-From-User-Vector, Boot-From-Zero, and Set-User-Boot-Vector commands program the chip-level security and boot vector options. The functions of these bits are described in the Security Lock and Boot Options sections. Once programmed, these bits can only erased through a Chip Erase command. See Figure 3-3 for Chip Erase timing waveforms. External Host Mode Clock Source In external host mode, an internal oscillator will provide clocking for the device, and the oscillator is unaffected by the clock doubler logic. The on-chip oscillator will be turned on as the device enters external host mode; i.e. when PSEN# goes low while RST is high. During external host mode, the CPU core is held in reset. Upon exit from external host mode, the internal oscillator is turned off. 5

6 Flash Operation Status Detection Via External Host Handshake The device provides two methods for an external host to detect the completion of a flash memory operation to optimize the Program or Erase time. The end of a flash memory operation cycle can be detected by monitoring the Ready/Busy# bit at P3[3] or monitoring the Data# Polling bit at P0[3]. Ready/Busy# (P3[3]) The progress of the flash memory programming can be monitored by the Ready/Busy# output signal. P3[3] is driven low, some time after PSEN# goes low during a flash memory operation to indicate the Busy# status of the Flash Control Unit (FCU). P3[3] is driven high when the flash programming operation is completed to indicate the ready status. Data# Polling (P0[3]) During a Program operation, any attempts to read (Byte-Verify) while the device is busy will receive the complement of the data of the last byte loaded on P0[3] with the rest of the bits 0. During a Program operation, the Byte-Verify command is reading the data of the last byte loaded, not the data at the address specified. Instructions to Perform External Host Mode Commands To program data into the memory array, apply power supply voltage (V DD )tov DD and RST pins, and perform the following steps: 1. Maintain RST and EA# pin high and set PSEN# from logic high to low, in sequence according to the appropriate timing diagram. 2. Issue a Read-ID command to enable the External Host mode. 3. Verify that the memory partitions or sectors for programming is in the erased state, FFH. If not set to FFH, issue the appropriate Erase command. 4. Select the memory location using the address lines (P2[7:0], P1[7:0]). 5. Present the data in on P0[7:0]. 6. Set the command code on P2[7], P3[5], P3[4], and P3[2]. 7. Pulse PSEN#, observing minimum pulse width. 8. Wait for low to high transition on Ready/Busy# (P3[3]). 9. Repeat steps 4-8until programming is finished. 10. Verify the flash memory contents. Additional Read Commands in External Host Mode To issue additional Read commands, shown in Table 3-4 below, use the same procedure as the Read ID command, but with a new address. Below is a partial list of useful features: Read the user boot vector setting. Read the status of the page security bits (Page0, Page1, Page2, Page3, Page4 Read the chip-level security bits and boot-option setting bits (Boot-From-Zero, Boot-From- User-Vector, Disable-Extern-Host-Cmd, Disable-Extern-MOVC, Disable-Extern-Boot, Disable-Extern-IAP). Read the clock mode (Enable-Clock-Double) status. Note: Commands shown in Table 4 are not ARMING commands. 6

7 Table 4: Additional Read Commands in External Host Mode Address Note: x = Don t care Data 33H Boot Vector 60H x x x Page4 Page3 Page2 Page1 Page0 61H x Boot- From-Zero Boot-From- User-Vector Enable- Clock- Double Disable- Extern-Host- Cmd Disable- Extern- MOVC Disable- Extern-Boot Table 5: External Mode Flash Memory Programming/Verification Parameters 1 1. For IAP operations, the program execution overhead must be added to the above timing parameters. 2. Program and Erase times will scale inversely proportional to programming clock frequency. 3. All timing measurements are from the 50% of the input to 50% of the output. 4. Each byte must be erased before programming. Disable- Extern-IAP Parameter 2,3 Symbol Min Max Units Reset Setup Time T SU 10 ms Read-ID Command Width T RD 1 µs PSEN# Setup Time T ES 40 µs Address, Command, Data Setup T ADS 300 ns Time Chip-Erase Time T CE 36 ms Partition0 Erase Time T PE 36 ms Sector-Erase Time T SE 6 ms Program Setup Time T PROG 400 ns Address, Command, Data Hold T DH 0 ns Byte-Program Time 4 T PB 60 µs Re-map or Security bit Program T PS 100 µs Time Ready/Busy signal falling after T RBPF 400 ns PSEN# falling edge Address to Data Valid Time T VALID 80 ns Setup time for P3[6] T ST 70 ns P3[6] to Data Valid Time T DVT 400 ns T0-0.0 DS25101 T0-0.0 DS

8 Flash Memory Programming Timing Diagrams with External Host Mode T SU RST ALE/PROG# T ES PSEN# EA# P3[2], P3[4:5], P3[7] 0000b 0000b P1, P2 0030H 0031H T Valid P0 BFH Device ID P3[1], P3[6]=0 P3[0]=1 P3[3] (RY/BY#)=1 Note: Device ID = See Table 2 on page (02) F13.1 Figure 3: Read-ID Reads chip signature and identification registers at the addressed location. 8

9 TSU RST TES ALE/PROG# TADS PSEN# TPROG TDH EA# P3[3] (RY/BY#) T RBPF TCE, TPE, TSE, TPB, TPS P0 DATA P1, P2 ADDRESS P3[2], P3[4:5], P3[7] PROGRAM/ERASE COMMAND P3[1], P3[6]=0 P3[0]=1 1323(02) F14.2 Figure 4: Program/Erase Programs/Erases the code memory by using the Byte-Program, Select-Partition, Security Bit Program, Chip-Erase, Erase-Status Byte, Boot-Vector, Partition-Erase, or Sector-Erase commands. These commands are activated by driving the appropriate command values onto port pins. The values for each command are shown in Table 1. 9

10 T SU RST T ES ALE/PROG# PSEN# EA# P3[2], P3[4:5], P3[7] Verify Command T DVT T DVT P0 DO DO P1, P2 AL AH P3[6] Read Enable T ST T ST P3[0], P3[3] (RY/BY#)=1 P3[1]=0 1323(02) F15.2 Figure 5: Byte-Verify Reads the code byte from the addressed flash memory location if the security lock is not activated on that flash memory block. 10

11 Table 6: Revision History Revision Description Date 00 Initial Release of Feb Modified Table 1 on page 2 May 2008 Updated External Host Mode Commands on page 4 Revised bit names in Additional Read Commands in External Host Mode on page 6 Removed duplicate entry from Table 5 on page 7 Updated Figures 3, 4, and 5. A Applied new document format Dec 2011 Released document under letter revision system Updated Spec number from S71323(02) to DS25101 ISBN: Silicon Storage Technology, Inc a Microchip Technology Company. All rights reserved. SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and registered trademarks mentioned herein are the property of their respective owners. Specifications are subject to change without notice. Refer to for the most recent documentation. For the most current package drawings, please see the Packaging Specification located at Memory sizes denote raw storage capacity; actual usable capacity may be less. SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of Sale. For sales office locations and information, please see Silicon Storage Technology, Inc. A Microchip Technology Company 11