4 Megabit (512K x8) Multi-Purpose Flash SST39SF040
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1 Megabit (K x) Multi-Purpose Flash FEATURES: Organized as K X Single.0V Read and Write Operations Superior Reliability Endurance: 0,000 Cycles (typical) Greater than 0 years Data Retention Low Power Consumption: Active Current: ma (typical) Standby Current: 0 µa (typical) Sector-Erase Capability Uniform KByte sectors Fast Read Access Time:, and 0 ns Latched Address and Data PRODUCT DESCRIPTION Fast Erase and Byte-Program: Sector-Erase Time: ms typical Chip-Erase Time: 0 ms typical Byte-Program Time: µs typical Chip Rewrite Time: seconds typical Automatic Write Timing Internal V PP Generation End-of-Write Detection Toggle Bit Data# Polling TTL I/O Compatibility JEDEC Standard Flash EEPROM Pinouts and command sets Packages Available -Pin PDIP -Pin PLCC -Pin TSOP (mm x mm) The is a K x CMOS Multi-Purpose Flash (MPF) manufactured with SST s proprietary, high performance CMOS SuperFlash technology. The splitgate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The device writes (Program or Erase) with a.0v power supply. The device conforms to JEDEC standard pinouts for x memories. Featuring high performance Byte-Program, the device provides a maximum Byte-Program time of 0 µsec. The entire memory can be erased and programmed byte-by-byte typically in seconds, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, the device has on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the device is offered with a guaranteed endurance of,000 cycles. Data retention is rated at greater than 0 years. The device is suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the device significantly improves performance and reliability, while lowering power consumption. The inherently uses less energy during erase and program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. The device also improves flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/ Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the device is offered in -pin TSOP and -pin PLCC packages. A 00 mil, -pin PDIP is also available. See Figures, and for pinouts. Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting low while keeping low. The address bus is latched on the falling edge of or, whichever occurs last. The data bus is latched on the rising edge of or, whichever occurs first. 000 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. -0 /00 These specifications are subject to change without notice.
2 Read The Read operation of the device is controlled by and, both have to be low for the system to obtain data from the outputs. is used for device selection. When is high, the chip is deselected and only standby power is consumed. is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either or is high. Refer to the Read cycle timing diagram for further details (Figure ). Byte-Program Operation The device is programmed on a byte-bybyte basis. The Program operation consists of three steps. The first step is the three-byte-load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either or, whichever occurs last. The data is latched on the rising edge of either or, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth or, whichever occurs first. The Program operation, once initiated, will be completed, within 0 µs. See Figures and for and controlled Program operation timing diagrams and Figure for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored. Sector-Erase Operation The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of KByte. The Sector-Erase operation is initiated by executing a six-byte-command load sequence for Software Data Protection with Sector-Erase command (0H) and sector address (SA) in the last bus cycle. The address lines A-A will be used to determine the sector address. The sector address is latched on the falling edge of the sixth pulse, while the command (0H) is latched on the rising edge of the sixth pulse. The internal Erase operation begins after the sixth pulse. The End-of- Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure for timing waveforms. Any commands written during the Sector-Erase operation will be ignored. Megabit Multi-Purpose Flash Chip-Erase Operation The device provides a Chip-Erase operation, which allows the user to erase the entire memory array to the s state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte Software Data Protection command sequence with Chip-Erase command (H) with address H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth or, whichever occurs first. During the internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table for the command sequence, Figure for timing diagram, and Figure for the flowchart. Any commands written during the Chip-Erase operation will be ignored. Write Operation Status Detection The device provides two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits : Data# Polling (DQ ) and Toggle Bit (DQ ). The End-of-Write detection mode is enabled after the rising edge of which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ or DQ. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two () times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Data# Polling (DQ ) When the device is in the internal Program operation, any attempt to read DQ will produce the complement of the true data. Once the Program operation is completed, DQ will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ will produce a 0. Once the internal Erase operation is completed, DQ will produce a. The Data# Polling is valid after the rising edge of fourth (or ) pulse for Program operation. For Sector or Chip-Erase, the Data# Polling is valid after the rising edge of sixth (or ) pulse. See Figure for Data# Polling timing diagram and Figure for a flowchart.
3 Toggle Bit (DQ ) During the internal Program or Erase operation, any consecutive attempts to read DQ will produce alternating 0 s and s, i.e., toggling between 0 and. When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth (or ) pulse for Program operation. For Sector or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth (or ) pulse. See Figure for Toggle Bit timing diagram and Figure for a flowchart. Data Protection The device provides both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A or pulse of less than ns will not initiate a Write cycle. V DD Power Up/Down Detection: The Write operation is inhibited when V DD is less than.v. Write Inhibit Mode: Forcing low, high, or high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Software Data Protection (SDP) The provides the JEDEC approved Software Data Protection scheme for all data alteration operation, i.e., program and erase. Any Program operation requires the inclusion of a series of three byte sequence. The three byte-load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation FUNCTIONAL BLOCK DIAGRAM OF X-Decoder requires the inclusion of six byte load sequence. The device is shipped with the Software Data Protection permanently enabled. See Table for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode, within T RC. Product Identification The product identification mode identifies the device as the and manufacturer as SST. This mode may be accessed by hardware or software operations. The hardware operation is typically used by a programmer to identify the correct algorithm for the device. Users may wish to use the software product identification operation to identify the part (i.e., using the device code) when using multiple manufacturers in the same socket. For details, see Table for hardware operation or Table for software operation, Figure for the software ID entry and read timing diagram and Figure for the ID entry command sequence flowchart. TABLE : PRODUCT IDENTIFICATION TABLE Address Data Manufacturer s Code 0000H BF H Device Code 000H B H Product Identification Mode Exit/Reset In order to return to the standard read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Exit ID command sequence, which returns the device to the Read operation. Please note that the software reset command is ignored during an internal Program or Erase operation. See Table for software command codes, Figure for timing waveform and Figure for a flowchart.,,0 bit EEPROM Cell Array PGM T.0 A - A0 Address Buffers & Latches Y-Decoder Control Logic I/O Buffers and Data Latches DQ - DQ0 ILL B.0
4 A A A A A A V DD A A A A A A A A Standard Pinout Top View Die Up 0 0 A DQ DQ DQ DQ DQ V SS DQ DQ DQ0 A0 A A A FIGURE : PIN ASSIGNMENTS FOR -PIN TSOP (mm x mm) ILL F0.0 A A A A A A A A A A A A0 DQ0 DQ DQ VSS -Pin PDIP Top View 0 0 VDD A A A A A A A DQ DQ DQ DQ DQ FIGURE : PIN ASSIGNMENTS FOR -PIN PDIP ILL F0a.0 A A A A VDD A A A A A A A A A0 DQ0 0 -Pin PLCC Top View 0 A A A A A A DQ DQ DQ VSS DQ DQ DQ DQ ILL F0. FIGURE : PIN ASSIGNMENTS FOR -PIN PLCC
5 TABLE : PIN DESCRIPTION Symbol Pin Name Functions A -A 0 Address Inputs To provide memory addresses. During Sector-Erase A -A address lines will select the sector. DQ -DQ 0 Data Input/output To output data during Read cycles and receive input data during write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when or is high. Chip Enable To activate the device when is low. Output Enable To gate the data output buffers. Write Enable To control the Write operations. V DD Power Supply To provide.0v (± %) supply Vss Ground TABLE : OPERATION MODES SELECTION PGM T.0 Mode A DQ Address Read V IL V IL V IH A IN D OUT A IN Program V IL V IH V IL A IN D IN A IN Erase V IL V IH V IL X X Sector address, XXh for Chip-Erase Standby V IH X X X High Z X Write Inhibit X V IL X X High Z/D OUT X X X V IH X High Z/D OUT X Product Identification Hardware Mode V IL V IL V IH V H Manufacturer Code (BF) A - A = V IL, A 0 = V IL Device Code (B) A - A = V IL, A 0 = V IH Software Mode V IL V IL V IH A IN ID Code See Table PGM T.0
6 TABLE : SOFTWARE COMMAND SEQUENCE Megabit Multi-Purpose Flash Command st Bus nd Bus rd Bus th Bus th Bus th Bus Sequence Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Addr () Data Addr () Data Addr () Data Addr () Data Addr () Data Addr () Data Byte-Program H AAH AAAH H H A0H BA () Data Sector-Erase H AAH AAAH H H 0H H AAH AAAH H SAx () 0H Chip-Erase H AAH AAAH H H 0H H AAH AAAH H H H Software ID Entry H AAH AAAH H H 0H Software ID Exit XXH F0H Software ID Exit H AAH AAAH H H F0H Notes: () Address format A -A 0 (Hex), Addresses A, A, A and A are a Don t Care for the Command sequence. () SA x for Sector-Erase; uses A -A address lines () BA = Program byte address () Both Software ID Exit operations are equivalent () With A -A =0; SST Manufacturer Code = BFH, is read with A 0 = 0, SF00 Device Code = BH, is read with A 0 =. () The device does not remain in Software Product ID Mode if powered down. PGM T.0
7 Absolute Maximum Stress Ratings (Applied conditions greater than those listed under Absolute Maximum Stress Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias... - C to + C Storage Temperature... - C to +0 C D. C. Voltage on Any Pin to Ground Potential V to V DD+ 0.V Transient Voltage (<0 ns) on Any Pin to Ground Potential V to V DD +.0V Voltage on A Pin to Ground Potential V to.v Package Power Dissipation Capability (Ta = C)....0W Through Hole Lead Soldering Temperature ( Seconds) C Surface Mount Lead Soldering Temperature ( Seconds)... 0 C Output Short Circuit Current ()... 0 ma Note: () Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE Range Ambient Temp V DD Commercial 0 C to +0 C.0V ±% Industrial -0 C to + C.0V ±% AC CONDITIONS OF TEST Input Rise/Fall Time... ns Output Load... C L = 0 pf See Figures and
8 TABLE : DC OPERATING CHARACTERISTICS V DD =.0V ± % Limits Symbol Parameter Min Max Units Test Conditions I DD Power Supply Current ==V IL, =V IH, all I/Os open, Read 0 ma Address input = V IL/V IH, at f=/t RC Min., V DD =V DD Max Write 0 ma ==V IL, =V IH, V DD =V DD Max. I SB Standby V DD Current ma =V IH, V DD = V DD Max. (TTL input) I SB Standby V DD Current 0 µa =V IHC, V DD = V DD Max. (CMOS input) I LI Input Leakage Current µa V IN =GND to V DD, V DD = V DD Max. I LO Output Leakage Current µa V OUT =GND to V DD, V DD = V DD Max. V IL Input Low Voltage 0. V V DD = V DD Min. V IH Input High Voltage.0 V V DD = V DD Max. V IHC Input High Voltage (CMOS) V DD-0. V V DD = V DD Max. V OL Output Low Voltage 0. V I OL =. ma, V DD = V DD Min. V OH Output High Voltage. V I OH = -00µA, V DD = V DD Min. V H Supervoltage for A pin.. V = =V IL, = V IH I H Supervoltage Current 00 µa = = V IL, = V IH, A = V H Max. for A pin PGM T. TABLE : RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter Minimum Units T () PU-READ Power-up to Read Operation 0 µs T () PU-WRITE Power-up to Write Operation 0 µs PGM T.0 TABLE : CAPACITANCE (Ta = C, f= Mhz, other pins open) Parameter Description Test Condition Maximum C () I/O I/O Pin Capacitance V I/O = 0V pf C () IN Input Capacitance V IN = 0V pf Note: () PGM T.0 This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE : RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method N () END Endurance,000 Cycles JEDEC Standard A T () DR Data Retention 0 Years JEDEC Standard A V () ZAP_HBM ESD Susceptibility 000 Volts JEDEC Standard A Human Body Model V () ZAP_MM ESD Susceptibility 00 Volts JEDEC Standard A Machine Model I () LTH Latch Up 0 + I DD ma JEDEC Standard Note: () PGM T.0 This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
9 AC CHARACTERISTICS TABLE : READ CYCLE TIMING PARAMETERS V DD =.0V Symbol Parameter Min Max Min Max Min Max Units T RC Read Cycle Time 0 ns T CE Chip Enable Access Time 0 ns T AA Address Access Time 0 ns T OE Output Enable Access Time 0 ns T () CLZ Low to Active Output ns T () OLZ Low to Active Output ns T () CHZ High to High-Z Output 0 ns T () OHZ High to High-Z Output 0 ns T () OH Output Hold from Address Change ns TABLE : PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter Min Max Units T BP Byte-Program Time 0 µs T AS Address Setup Time 0 ns T AH Address Hold Time 0 ns T CS and Setup Time 0 ns T CH and Hold Time 0 ns T OES High Setup Time 0 ns T OEH High Hold Time ns T CP Pulse Width 0 ns T WP Pulse Width 0 ns T WPH Pulse Width High 0 ns T CPH Pulse Width High 0 ns T DS Data Setup Time 0 ns T DH Data Hold Time 0 ns T IDA Software ID Access and Exit Time 0 ns T SE Sector-Erase ms T SCE Chip-Erase 0 ms PGM T.0 Note: () This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. PGM T.
10 TRC TAA ADDRESS A-0 TCE TOE VIH TOLZ TOHZ TCHZ DQ-0 HIGH-Z TCLZ TOH DATA VALID DATA VALID HIGH-Z ILL F0.0 FIGURE : READ CYCLE TIMING DIAGRAM INTERNAL PROGRAM OPERATION STARTS T BP ADDRESS A -0 AAA ADDR T AH T WP T DH T AS T WPH T DS T CH T CS DQ -0 AA A0 DATA SW0 SW SW BYTE (ADDR/DATA) ILL F0.0 FIGURE : CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
11 INTERNAL PROGRAM OPERATION STARTS T BP ADDRESS A -0 AAA ADDR T AH T CP T DH T AS T CPH T DS DQ -0 T CS T CH AA A0 DATA SW0 SW SW BYTE (ADDR/DATA) ILL F0.0 FIGURE : CONTROLLED PROGRAM CYCLE TIMING DIAGRAM ADDRESS A -0 T CE TOEH T OES TOE DQ D D# D# D ILL F0.0 FIGURE : DATA# POLLING TIMING DIAGRAM
12 ADDRESS A-0 TCE TOEH TOE TOES DQ TWO READ CYCLES WITH SAME OUTPUTS ILL F0.0 FIGURE : TOGGLE BIT TIMING DIAGRAM SIX-BYTE CODE FOR SECTOR-ERASE T SE ADDRESS A -0 AAA AAA SA X TWP DQ-0 AA 0 AA 0 SW0 SW SW SW SW SW ILL F0.0 Note: This device also supports controlled Sector-Erase operation. The and signals are interchageable as long as minimum timings are met. (See Table ) SA X = Sector Address FIGURE : CONTROLLED SECTOR-ERASE TIMING DIAGRAM
13 SIX-BYTE CODE FOR CHIP-ERASE TSCE ADDRESS A-0 AAA AAA TWP DQ-0 AA 0 AA SW0 SW SW SW SW SW Note: This device also supports controlled Chip-Erase operation. The and signals are interchageable as long as minmum timings are met. (See Table ) ILL F.0 FIGURE : CONTROLLED CHIP-ERASE TIMING DIAGRAM Three-byte sequence for Software ID Entry ADDRESS A -0 AAA T WP T IDA DQ -0 T WPH AA 0 SW0 SW SW T AA BF B ILL F0.0 FIGURE : SOFTWARE ID ENTRY AND READ
14 THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESS A-0 AAA DQ-0 AA F0 TIDA T WP T WHP SW0 SW SW ILL F.0 FIGURE : SOFTWARE ID EXIT AND RESET
15 VIHT VILT INPUT VIT REFERENCE POINTS VOT OUTPUT FIGURE : AC INPUT/OUTPUT REFERENCE WAVEFORMS 0 ILL F. AC test inputs are driven at V IHT (.0 V) for a logic and V ILT (0 V) for a logic 0. Measurement reference points for inputs and outputs are at V IT (. V) and V OT (. V) Input rise and fall times (% «0%) are < ns. Note: V IT V INPUT Test V OT V OUTPUT Test V IHT V INPUT HIGH Test V ILT V INPUT LOW Test TEST LOAD EXAMPLE TO TESTER VDD RL HIGH TO DUT CL RL LOW ILL F.0 FIGURE : A TEST LOAD EXAMPLE
16 Start Load data: AA Address: Load data: Address: AAA Load data: A0 Address: Load Byte Address/Byte Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed ILL F.0 FIGURE : BYTE-PROGRAM ALGORITHM
17 Internal Timer Byte Program/Erase Initiated Toggle Bit Byte Program/Erase Initiated Data# Polling Byte Program/Erase Initiated Wait TBP, TSCE, or TSE Read byte Read DQ Program/Erase Completed Read same byte No Is DQ = true data? Yes No Does DQ match? Program/Erase Completed Yes Program/Erase Completed ILL F.0 FIGURE : WAIT OPTIONS
18 Software Product ID Entry Command Sequence Software Product ID Exit & Reset Command Sequence Load data: AA Address: Load data: AA Address: Load data: F0 Address: XX Load data: Address: AAA Load data: Address: AAA Wait TIDA Load data: 0 Address: Load data: F0 Address: Return to normal operation Wait TIDA Wait TIDA Read Software ID Return to normal operation ILL F.0 FIGURE : SOFTWARE PRODUCT COMMAND FLOWCHARTS
19 Chip-Erase Command Sequence Load data: AA Address: Load data: Address: AAA Load data: 0 Address: Load data: AA Address: Load data: Address: AAA Load data: Address: Wait TSCE Chip erased to FFH Sector-Erase Command Sequence Load data: AA Address: Load data: Address: AAA Load data: 0 Address: Load data: AA Address: Load data: Address: AAA Load data: 0 Address: SAX Wait TSE Sector erased to FFH FIGURE : ERASE COMMAND SEQUENCE ILL F.0
20 Device Speed Suffix Suffix - XXX - XX - XX Megabit Multi-Purpose Flash Package Modifier H = pins Numeric = Die modifier Package Type P = PDIP N = PLCC W = TSOP (die up) (mm x mm) Temperature Range C = Commercial = 0 to 0 C I = Industrial = -0 to C Minimum Endurance =,000 cycles Read Access Speed = ns, = ns, 0 = 0 ns Valid combinations --C-WH --C-NH --C-WH --C-NH -0-C-WH -0-C-NH -0-C-PH --I-WH --I-WH -0-I-WH --I-NH --I-NH -0-I-NH Example : Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. 0
21 PACKAGING DIAGRAMS pin index C L PLCS..0.0 Base Plane Seating Plane.0.00 Note: PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP) SST PACKAGE CODE: PH BSC. Complies with JEDEC publication MO-0 AP dimensions, although some dimensions may be more stringent.. All linear dimensions are in inches (min/max).. Dimensions do not include mold flash. Maximum allowable mold flash is.0 inches. TOP VIEW SIDE VIEW BOTTOM VIEW BSC 0.pdipPH-ILL. Optional Pin # Identifier R. MAX..0 x R BSC BSC..00 BSC Min..0.0 Note:. Complies with JEDEC publication MS-0 AE dimensions, although some dimensions may be more stringent.. All linear dimensions are in inches (min/max).. Dimensions do not include mold flash. Maximum allowable mold flash is.00 inches..plcc.nh-ill. -PIN PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH
22 PIN # IDENTIFIER BSC Note:. Complies with JEDEC publication MO- BA dimensions, although some dimensions may be more stringent.. All linear dimensions are in millimeters (min/max).. Coplanarity: 0. (±.0) mm..tsop-wh-ill. -PIN THIN SMALL OUTLINE PACKAGE (TSOP) MM X MM SST PACKAGE CODE: WH Silicon Storage Technology, Inc. Sonora Court Sunnyvale, CA 0 Telephone 0-- Fax or Literature FaxBack --, International --
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1 Mbit / 2 Mbit / 4 Mbit 5 Volt-only CMOS Flash Memory FEATURES Single Power Supply Operation - Low voltage range: 4.5 V - 5.5 V Memory Organization - Pm39F010: 128K x 8 (1 Mbit) - Pm39F020: 256K x 8 (2
More information1-Megabit (128K x 8) Low Voltage Paged Parallel EEPROMs AT28LV010
BDTIC www.bdtic.com/atmel Features Single 3.3V ± 10% Supply Fast Read Access Time 200 ns Automatic Page Write Operation Internal Address and Data Latches for 128 Bytes Internal Control Timer Fast Write
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Mbit / Mbit / 8 Mbit (x) Multi-Purpose Flash FEATURES: SST9LF/VF00A / 00A / 800A.0 &.7V Mb / Mb / 8Mb (x) MPF memories Organized as 8K x / K x / K x Single Voltage Read and Write Operations.0-.V for SST9LF00A/00A/800A.7-.V
More information2 Mbit / 4 Mbit / 8 Mbit (x16) Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A
2 Mbit / 4 Mbit / 8 Mbit (x6) Multi-Purpose Flash FEATURES: SST39LF/VF200A / 400A / 800A3.0 & 2.7V 2Mb / 4Mb / 8Mb (x6) MPF memories Organized as 28K x6 / 256K x6 / 52K x6 Single Voltage Read and Write
More information32 Mbit (x16) Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B
FEATURES: 32 Mbit (x16) Multi-Purpose Flash Plus SST39VF640xB2.7V 64Mb (x16) MPF+ memories Organized as 2M x16 Single Voltage Read and Write Operations 2.7-3.6V Superior Reliability Endurance: 100,000
More informationPm39LV512 / Pm39LV010 / Pm39LV020 / Pm39LV040
512 Kbit / 1Mbit / 2Mbit / 4Mbit 3.0 Volt-only CMOS Flash Memory FEATURES Single Power Supply Operation - Low voltage range: 2.7 V - 3.6 V Memory Organization - Pm39LV512: 64K x 8 (512 Kbit) - Pm39LV010:
More information1-Megabit (128K x 8) 5-volt Only Flash Memory AT29C010A. Features. Description. Pin Configurations
Features Fast Read Access Time - 70 ns 5-Volt Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 1024 Sectors (128 bytes/sector) Internal Address and Data Latches for
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FEATURES: Firmware Hub for Intel 0, 0E, 0, 0 Chipsets Mbits SuperFlash memory array for code/data storage : K x ( Mbit) Flexible Erase Capability Uniform KByte sectors Uniform KByte overlay blocks KByte
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FEATURES: 1 Mb Serial Peripheral Interface (SPI) flash memory Single 2.7-3.6V Read and Write Operations Serial Interface Architecture SPI Compatible: Mode 0 and Mode 3 20 MHz Max Clock Frequency Superior
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6 Mbit (x8) Multi-Purpose Flash Plus The are 2M x8 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST proprietary, high performance CMOS Super- Flash technology. The split-gate cell design and
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16 Mbit / 32 Mbit / 64 Mbit (x16) Multi-Purpose Flash Plus FEATURES: SST39VF160x / 320x / 640x2.7V 16Mb / 32Mb / 64Mb (x16) MPF+ memories Organized as 1M x16: SST39VF1601/1602 2M x16: SST39VF3201/3202
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Features Single Voltage Operation 5V Read 5V Reprogramming Fast Read Access Time - 70 ns Internal Program Control and Timer 16K bytes Boot Block With Lockout Fast Erase Cycle Time - 10 seconds Byte By
More informationCAT28C K-Bit Parallel EEPROM
256K-Bit Parallel EEPROM HALOGENFREE LEAD TM FREE FEATURES Fast read access times: 120/150ns Low power CMOS dissipation: Active: 25 ma max Standby: 150 µa max Simple write operation: On-chip address and
More informationMulti-Purpose Flash (MPF) + SRAM ComboMemory SST32HF202 / SST32HF402 / SST32HF802
FEATURES: SST32HF202 / 402 / 8022Mb Flash + 2Mb SRAM, 4Mb Flash + 2Mb SRAM, 8Mb Flash + 2Mb SRAM (x16) MCP ComboMemory MPF + SRAM ComboMemory SST32HF202: 128K x16 Flash + 128K x16 SRAM SST32HF402: 256K
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16 Mbit / 32 Mbit / (x16) Multi-Purpose Flash Plus FEATURES: SST39VF160x / 320x / 640x2.7V 16Mb / 32Mb / 64Mb (x16) MPF+ memories Organized as 1M x16: SST39VF1601/1602 2M x16: SST39VF3201/3202 Single Voltage
More informationFEATURES. Single Power Supply Operation - Low voltage range: 2.70 V V
FEATURES Single Power Supply Operation - Low voltage range: 2.70 V - 3.60 V - IS39LV040: 512K x 8 (4 Mbit) - IS39LV010: 128K x 8 (1 Mbit) - IS39LV512: 64K x 8 (512 Kbit) - 70 ns access time - Uniform 4
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FEATURES: 2 Mbit / 4 Mbit SPI Serial Flash SST25VF020 / 0402Mb / 4Mb Serial Peripheral Interface (SPI) flash memory Single 2.7-3.6V Read and Write Operations Serial Interface Architecture SPI Compatible:
More information64 Mbit (x16) Advanced Multi-Purpose Flash Plus SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404
The SST38VF6401/6402/6403/6404 are 4M x16 CMOS Advanced Multi-Purpose Flash Plus (Advanced MPF+) devices manufactured with proprietary, high-performance CMOS Super- Flash technology. The split-gate cell
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Features 2.7V to 3.6V Read/Write Operation Fast Read Access Time - 120 ns Internal Erase/Program Control Sector Architecture One 8K Words (16K bytes) Boot Block with Programming Lockout Two 4K Words (8K
More information512 Kbit SPI Serial Flash SST25VF512A
FEATURES: 512 Kbit SPI Serial Flash 512Kb Serial Peripheral Interface (SPI) flash memory Single 2.7-3.6V Read and Write Operations Serial Interface Architecture SPI Compatible: Mode 0 and Mode 3 33 MHz
More information64 Mbit (x16) Multi-Purpose Flash Plus SST39VF6401B / SST39VF6402B
Not recommended for new designs. Please use SST38VF6401/6402/6403/64040 A Microchip Technology Company 64 Mbit (x16) Multi-Purpose Flash Plus The devices are 4M x16, CMOS Multi-Purpose Flash Plus (MPF+)
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FEATURES: 2 Mbit SPI Serial Flash / 0402Mb / 4Mb Serial Peripheral Interface (SPI) flash memory Single 2.7-3.6V Read and Write Operations Serial Interface Architecture SPI Compatible: Mode 0 and Mode 3
More information512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit SPI Serial Flash SST25VF512 / SST25VF010 / SST25VF020 / SST25VF040
FEATURES: SST25VF512 / 010 / 020 / 040512Kb / 1Mb / 2Mb / 4Mb Serial Peripheral Interface (SPI) flash memory Single 2.7-3.6V Read and Write Operations Serial Interface Architecture SPI Compatible: Mode
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FEATURES: 512 Kbit SPI Serial Flash 512Kb Serial Peripheral Interface (SPI) flash memory Single 2.7-3.6V Read and Write Operations Serial Interface Architecture SPI Compatible: Mode 0 and Mode 3 20 MHz
More informationProduct Change Notification - SYST-13FJDM513
Product Change Notification - SYST-13FJDM513 Date: 14 Sep 2018 Product Category: Memory Affected CPNs: Notification subject: Data Sheet - SST38VF6401 / 6402 / 6403 / 6404 Data Sheet Notification text:
More information8 Mbit / 16 Mbit SPI Serial Flash SST25VF080 / SST25VF016
FEATURES: 8 Mbit / 16 Mbit SPI Serial Flash SST25VF080 / 0168Mb / 16Mb Serial Peripheral Interface (SPI) flash memory Single 2.7-3.6V Read and Write Operations Serial Interface Architecture SPI Compatible:
More information1 Megabit (128K x8) Page-Mode EEPROM SST29EE010 / SST29LE010 / SST29VE010
Megabit (K x) Page-Mode EEPROM FEAURES: Single Voltage Read and Write Operations.0V-only for the SSEE00.0-.V for the SSLE00.-.V for the SSVE00 Superior Reliability Endurance: 00,000 Cycles (typical) Greater
More informationCAT28C17A 16K-Bit CMOS PARALLEL EEPROM
16K-Bit CMOS PARALLEL EEPROM HALOGENFREE LEAD TM FREE FEATURES Fast Read Access Times: 200 ns Low Power CMOS Dissipation: Active: 25 ma Max. Standby: 100 µa Max. Simple Write Operation: On-Chip Address
More information2 Mbit / 4 Mbit Firmware Hub SST49LF002A / SST49LF004A
FEATURES: Firmware Hub for Intel 0, 0E, 0, 0 Chipsets Mbits or Mbits SuperFlash memory array for code/data storage SSTLF00A: K x ( Mbit) SSTLF00A: K x ( Mbit) Flexible Erase Capability Uniform KByte Sectors
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SST serial flash family features a four-wire, SPI-compatible interface that allows for a low pin-count package occupying less board space and ultimately lowering total system costs. SPI serial flash memory
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FEATURES: 32 Mbit SPI Serial Flash 32Mb Serial Peripheral Interface (SPI) flash memory Single Voltage Read and Write Operations 2.7-3.6V Serial Interface Architecture SPI Compatible: Mode 0 and Mode 3
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Not recommended for new designs. Please use B SST's serial flash family features a four-wire, SPI-compatible interface that allows for a low pin-count package occupying less board space and ultimately
More information64K (8K x 8) Battery-Voltage Parallel EEPROM with Page Write and Software Data Protection AT28BV64B
Features Single 2.7V to 3.6V Supply Hardware and Software Data Protection Low Power Dissipation 15mA Active Current 20µA CMOS Standby Current Fast Read Access Time 200ns Automatic Page Write Operation
More information1-Megabit (128K x 8) Low Voltage Paged Parallel EEPROMs
Features Single 3.3V ± 10% Supply Fast Read Access Time - 200 ns Automatic Page Write Operation Internal Address and Data Latches for 128 Bytes Internal Control Timer Fast Write Cycle Time Page Write Cycle
More information8 Mbit (x16) Multi-Purpose Flash Plus SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C
The are 52K x6 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain
More information2 Mbit SPI Serial Flash SST25LF020A
Not recommended for new designs. Please use SST25VF020B SST serial flash family features a four-wire, SPI-compatible interface that allows for a low pin-count package occupying less board space and ultimately
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Rev.1.1 CMOS 16K-bit PARALLEL E 2 PROM The S-2812A and the S-2817A are low power 2K 8-bit parallel E 2 PROMs. The S-2812A features wide operating voltage range, and the S-2817A features 5-V single power
More information256K (32K x 8) 3-volt Only Flash Memory
Features Single Supply Voltage, Range 3V to 3.6V 3-Volt Only Read and Write Operation Software Protected Programming Low Power Dissipation 15 ma Active Current 40 µa CMOS Standby Current Fast Read Access
More informationThe Am29F040B is not offered for new designs. Please contact your Spansion representative for alternates.
Am29F040B Data Sheet RETIRED PRODUCT The Am29F040B is not offered for new designs. Please contact your Spansion representative for alternates. The following document contains information on Spansion memory
More information256K-Bit PARALLEL EEPROM
256K-Bit PARALLEL EEPROM FEATURES Fast read access times: 120/150ns Low power CMOS dissipation: Active: 25 ma max Standby: 150 µa max Simple write operation: On-chip address and data latches Self-timed
More informationAm29F040B. Data Sheet
Am29F040B Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of
More informationDIP Top View A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND VCC A17 A14 A13 A8 A9 A11 A10 I/O7 I/O6 I/O5 I/O4 I/O3 VCC A18 A17
Features Single-voltage Operation 5V Read 5V Reprogramming Fast Read Access Time 55 ns Internal Program Control and Timer 16-Kbyte Boot Block with Lockout Fast Erase Cycle Time 10 seconds Byte-by-byte
More information1-megabit (64K x 16) 5-volt Only Flash Memory AT49F1024 AT49F1025
Features Single-voltage Operation 5V Read 5V Reprogramming Fast Read Access Time 35 ns Internal Program Control and Timer 8K Word Boot Block with Lockout Fast Erase Cycle Time 10 seconds Word-by-word Programming
More information1-Megabit (128K x 8) 5-volt Only Flash Memory AT29C010A. Features. Description. Pin Configurations
Features Fast Read Access Time - 70 ns 5-Volt Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 1024 Sectors (128 bytes/sector) Internal Address and Data Latches for
More information4-Megabit (512K x 8) 5-volt Only 256-Byte Sector Flash Memory AT29C040A. Features. Description. Pin Configurations
Features Fast Read Access Time - 120 ns 5-Volt Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 2048 Sectors (256 bytes/sector) Internal Address and Data Latches for
More informationAT28C16. 16K (2K x 8) CMOS E 2 PROM. Features. Description. Pin Configurations
Features Fast Read Access Time - 150 ns Fast Byte Write - 200 µs or 1 ms Self-Timed Byte Write Cycle Internal Address and Data Latches Internal Control Timer Automatic Clear Before Write Direct Microprocessor
More informationBattery-Voltage. 16K (2K x 8) Parallel EEPROMs AT28BV16. Features. Description. Pin Configurations
Features 2.7 to 3.6V Supply Full Read and Write Operation Low Power Dissipation 8 ma Active Current 50 µa CMOS Standby Current Read Access Time - 250 ns Byte Write - 3 ms Direct Microprocessor Control
More information4-megabit (512K x 8) Single 2.7-volt Battery-Voltage Flash Memory AT49BV040 AT49BV040T AT49LV040 AT49LV040T
Features Single Voltage for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV) Fast Read Access Time 70 ns Internal Program Control and Timer 16K Bytes Boot Block with Lockout Fast Chip Erase Cycle Time
More informationICE27C Megabit(128KX8) OTP EPROM
1- Megabit(128KX8) OTP EPROM Description The is a low-power, high-performance 1M(1,048,576) bit one-time programmable read only memory (OTP EPROM) organized as 128K by 8 bits. It is single 5V power supply
More information1-megabit (128K x 8) Paged Parallel EEPROM AT28C010
Features Fast Read Access Time 120 ns Automatic Page Write Operation Internal Address and Data Latches for 128 Bytes Internal Control Timer Fast Write Cycle Time Page Write Cycle Time 10 ms Maximum 1 to
More informationBattery-Voltage. 256K (32K x 8) Parallel EEPROMs AT28BV256. Features. Description. Pin Configurations
Features Single 2.7V - 3.6V Supply Fast Read Access Time - 200 ns Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Internal Control Timer Fast Write Cycle Times Page Write
More informationDIP Top View VCC WE A17 NC A16 A15 A12 A14 A13 A8 A9 A11 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 I/O1 I/O2 GND.
Features Fast Read Access Time - 70 ns 5-volt Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 1024 Sectors (256 bytes/sector) Internal Address and Data Latches for
More informationAm29F004B. 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS
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FEATURES: 64 Mbit SPI Serial Dual I/O Flash SST25VF032B32Mb Serial Peripheral Interface (SPI) flash memory Single Voltage Read and Write Operations 2.7-3.6V Serial Interface Architecture SPI Compatible:
More information1-megabit (64K x 16) 3-volt Only Flash Memory AT49LV1024 AT49LV1025
Features Single-voltage Operation 3V Read 3.1V Programming Fast Read Access Time 55 ns Internal Program Control and Timer 8K Word Boot Block with Lockout Fast Erase Cycle Time 10 seconds Word-by-Word Programming
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More information3.3 Volt, Byte Alterable E 2 PROM
1M X28LV010 128K x 8 Bit 3.3 Volt, Byte Alterable E 2 PROM FEATURES Access Time: 70, 90, 120, 150ns Simple Byte and Page Write Single 3.3V±10% supply No external high voltages or V PP control circuits
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High Temperature 128MB SPI Serial Flash Memory Module Temperature Rating 175 C Part No.: 128MB08SF04 CMOS 3.3 Volt 8-bit 0.0750" 0.100" at 39 plcs 0.675" 0.500" 0.075" Pin 1 Dot (Filled White) 0.428" 0.500"
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The flash memory devices are designed to be read-compatible with the Intel 82802 Firmware Hub (FWH) device for PC-BIOS application. These devices provide protection for the storage and update of code and
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128Kx8 CMOS MONOLITHIC EEPROM SMD 5962-96796 WME128K8-XXX FEATURES Read Access Times of 125, 140, 150, 200, 250, 300ns JEDEC Approved Packages 32 pin, Hermetic Ceramic, 0.600" DIP (Package 300) 32 lead,
More information4-megabit (512K x 8) Single 2.7-volt Battery-Voltage Flash Memory AT49BV040 AT49LV040
Features Single Voltage for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV) Fast Read Access Time 70 ns Internal Program Control and Timer 16K Bytes Boot Block with Lockout Fast Chip Erase Cycle Time
More informationAm29LV040B. 4 Megabit (512 K x 8-Bit) CMOS 3.0 Volt-only, Uniform Sector 32-Pin Flash Memory DISTINCTIVE CHARACTERISTICS
Am29LV040B 4 Megabit (512 K x 8-Bit) CMOS 3.0 Volt-only, Uniform Sector 32-Pin Flash Memory DISTINCTIVE CHARACTERISTICS Single power supply operation Full voltage range: 2.7 to 3.6 volt read and write
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256-Bit Nonvolatile CMOS Static RAM FEATURES Single 5V Supply Fast RAM Access Times: 200ns 300ns Infinite E 2 PROM to RAM Recall CMOS and TTL Compatible I/O Power Up/Down Protection 100,000 Program/Erase
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Features Fast Read Access Time - 90 ns 5-Volt-Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 1024 Sectors (256 bytes/sector) Internal Address and Data Latches for
More information4 Mbit (x16) Multi-Purpose Flash Plus SST39VF401C / SST39VF402C SST39LF401C / SST39LF402C
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More informationAm27C Megabit (256 K x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM V CC V SS V PP
FINAL Am27C020 2 Megabit (256 K x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS Fast access time Speed options as fast as 55 ns Low power consumption 100 µa maximum CMOS standby current JEDEC-approved
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64 kb CMOS Parallel EEPROM Description The CAT28LV65 is a low voltage, low power, CMOS Parallel EEPROM organized as 8K x 8 bits. It requires a simple interface for in system programming. On chip address
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AT28C256 Features Fast Read Access Time - 150 ns Automatic Page Write Operation Internal Address and Data Latches for 64-Bytes Internal Control Timer Fast Write Cycle Times Page Write Cycle Time: 3 ms
More informationAm27C Kilobit (8 K x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM V CC V SS V PP
FINAL Am27C64 64 Kilobit (8 K x 8-Bit) CMOS EPROM DISTINCTIVE CHARACTERISTICS Fast access time Speed options as fast as 45 ns Low power consumption 20 µa typical CMOS standby current JEDEC-approved pinout
More information64K (8K x 8) High Speed Parallel EEPROM with Page Write and Software Data Protection AT28HC64BF
Features Fast Read Access Time 70 ns Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Fast Write Cycle Times Page Write Cycle Time: 2 ms Maximum (Standard) 1 to 64-byte Page
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Features Fast Read Access Time 90 ns Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Internal Control Timer Fast Write Cycle Times Page Write Cycle Time: 3 ms or 10 ms Maximum
More information4-megabit (512K x 8) 5-volt Only 256-byte Sector Flash Memory AT29C040A
Features Fast Read Access Time 90 ns 5-volt Only Reprogramming Sector Program Operation Single Cycle Reprogram (Erase and Program) 2048 Sectors (256 Bytes/Sector) Internal Address and Data Latches for
More information64K (8K x 8) Low-voltage Parallel EEPROM with Page Write and Software Data Protection AT28LV64B. 3-Volt, 64K E 2 PROM with Data Protection
Features Single 3.3V ± 10% Supply Hardware and Software Data Protection Low-power Dissipation 15mAActiveCurrent 20 µa CMOS Standby Current Fast Read Access Time - 200 ns Automatic Page Write Operation
More information16 Mbit SPI Serial Flash T25VF016B
FEATURES: 16 Mbit SPI Serial Flash T25VF016B SST25VF016B16Mb Serial Peripheral Interface (SPI) flash memory Single Voltage Read and Write Operations 2.7-3.6V Serial Interface Architecture SPI Compatible:
More information64K-Bit CMOS PARALLEL EEPROM
64K-Bit CMOS PARALLEL EEPROM FEATURES Fast read access times: 90/120/150ns Low power CMOS dissipation: Active: 25 ma max. Standby: 100 µa max. Simple write operation: On-chip address and data latches Self-timed
More informationAm29F010B. For More Information Please contact your local sales office for additional information about Spansion memory solutions.
Am29F010B Data Sheet Am29F010B Cover Sheet The following document contains information on Spansion memory products. Continuity of Specifications There is no change to this data sheet as a result of offering
More information512K (64K x 8) 3-volt Only Flash Memory AT29LV512
Features Single Supply Voltage, Range 3V to 3.6V 3-volt Only Read and Write Operation Software Protected Programming Low-power Dissipation 15 ma Active Current 50 µa CMOS Standby Current Fast Read Access
More informationDIP Top View VCC RESET A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND A14 A13 A8 A9 A11 A10 I/O7 I/O6 I/O5 I/O4 I/O3
Features Single Supply for Read and Write: 2.7 to 3.6V (BV), 3.0 to 3.6V (LV) Fast Read Access Time - 70 ns Internal Program Control and Timer Sector Architecture One 16K Byte Boot Block with Programming
More informationAm29F040B. 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory DISTINCTIVE CHARACTERISTICS
Am29F040B 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory DISTINCTIVE CHARACTERISTICS 5.0 V ± 10% for read and write operations Minimizes system level power requirements Manufactured
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