SH-X3 Flexible SuperH Multi-core for High-performance and Low-power Embedded Systems

Transcription

1 SH-X3 Flexible SuperH Multi-core for High-performance and Low-power Embedded Systems Shinichi Shibahara 1, Masashi Takada 2, Tatsuya Kamei 1, Kiyoshi Hayase 1, Yutaka Yoshida 1, Osamu Nishii 1, Toshihiro Hattori 1 Hot Chips 19, 2007/8/20 1 Renesas Technology Corp. 2 Hitachi Ltd.

2 Requirement for Embedded Systems Trend Total scale is increasing by the introduction of advanced features. Mobile Phone 2D / 3D Mail W-CDMA GSM Camera Video Sound JAVA Requirement High Performance (for advanced features) Small Area (for smaller gadgets) Low Power (for long duration of battery) Solution: On-chip Multi-processor Process technology allows to produce easily. MP can be performance and power effective. 2

3 Multi-processor Approaches for Embedded Systems Features Application Specific: Optimize hardware & software for each system Low Power: Less than 1W (in the case of battery-run) Approaches Heterogeneous / Homogeneous AMP Integration of sub-systems / Deterministic behavior Homogeneous SMP Relatively easy programming model / Performance oriented Hybrid (Mixed system of AMP and SMP) Automatic Parallelizing Compiler AMP SMP Hybrid (AMP + SMP) Video JAVA GPS GSM Car Navigation Car Navigation GPS RTOS GPOS RTOS RTOS SMP OS SMP OS RTOS CPU0 CPU1 CPU2 CPU3 CPU0 CPU1 CPU2 CPU3 CPU0 CPU1 CPU2 CPU3 3

4 SuperH Processor Core Roadmap SH-4 SH3-DSP 5-stage pipeline up to 266MHz G LP 1.8 MIPS/MHz SH-X Superscalar 7-stage pipeline Released in 2003 Products: SH-Mobile3 SH-Navi1 G LP 1.8 MIPS/MHz SH-X2 Superscalar 8-stage pipeline Released in 2005 Products: SH-Mobile G1, G2 SH-Navi2 G LP 7.2 MIPS/MHz (4-CPU) SH-X3 MP-ready (up to 4-CPU) Superscalar (each) 8-stage pipeline First Target: Car Information Systems 4

5 SH-X3 Block Diagram Clock Controller Interrupt Controller On-chip Debugger CPU Fetch Inst. Bus I$ I- LRAM Bus I/F Controller CPU Exec UTLB Cache-RAM Bus Data Transfer Unit D- LRAM CPU #3 CPU #2 CPU #1 CPU #0 FPU / DSP Data Bus D$ URAM Snoop Bus Snoop Controller On-chip System Bus (SuperHyway Bus TM On-chip Interconnect) D-LRAM: Also called XY-RAM in SH4AL-DSP 5

6 Pipeline Structure Eight-stage dual-issue superscalar pipeline (Inherited from SH-X2) Instruction fetch Pre-dec Decode & Issue Fwd ALU I1 I2 I3 ID E1 E2 E3 Write back WB Arithmetic Execution M1 M2 M3 WB Memory Load-Store Addr calc Mem access Align Write back FPU pipe F1 F2 F3 F4 F5 F6 WB Reg read Operation Write back DSP pipe D1 D2 D3 D4 WB Decode Reg read Operation Write back 6

7 Specification Features Efficient for both SMP and AMP Cache coherency (Snoop Controller) for SMP Today s Topic Local memories (LRAM, URAM) and data transfer unit for AMP Realization of hybrid MP model Fine power management for each CPU Low-power modes according to workload (sleep, light sleep, standby etc.) Flexible clock ratio (CPU Clock : System Bus Clock = m:n (m>n), 1:n) Hierarchical clock gating Configurable and synthesizable Number of CPU (up to 4-CPU), Co-processor (DSP, FPU) Cache (8KB~64KB/4way) Local memory (LRAM: 4KB~128KB, URAM: 128KB~1MB) 7

8 Cache Coherency for Embedded Systems Problems in applying bus snooping (used in HPC servers) Performance degradation by system bus occupation Unnecessary power dissipation by snooping activity Fixed write-cache mode: MESI (Copy-back) or ESI (Write-through) MESI Fixed: HW accelerator on system bus cannot access the latest data. ESI Fixed: CPU cannot run at the best performance due to store accesses. Solution Separation of system bus and snoop bus (Reduce bus occupation) Centralized coherency control by snoop controller (Reduce bus activity) Support of mixed cache coherency protocol (Each CPU can select mode) 8

9 Cache Coherency Maintenance (Conventional: Bus Snooping) Data Bus CPU 0 CPU 3 Data Bus Cache Controller 0 Cache Controller 3 Controller Operand Cache Controller All transactions appear on bus Bus occupation, Wasting power Operand Cache Bus I/F Controller 0 Bus I/F Controller 3 Cache Operation (Fill, WB, ) Monitor All Transactions (Bus Snooping) Memory System Bus 9

10 Cache Coherency Maintenance (MESI Protocol) Data Bus (1) Operand Access (2) Search Controller (3) Fill Request CPU 0 Cache Controller 0 Operand Cache Initiator Target Initiator Target Snoop Bus (8) Response (9) Update Controller (5) Request Reduce bus occupation No bus monitoring (6) Search & Update Cache Controller 3 (7) Response (8) Dirty Transfer Snoop Controller CPU 3 Operand Cache BIC 0 (4) Search & Update (CPU0) (CPU1) (CPU2) (CPU3) BIC 3 Initiator Initiator Target Initiator 10 (8) WB Request Receive Snoop Request from PCI Express etc. System Bus BIC: Bus I/F Controller, : Duplicated Address Array

11 Snoop Latency Optimization (ESI Protocol) Controller (1) WT Request Cache Controller 0 Operand Cache Initiator Target Initiator Target (3) Response Controller (3) Request (Erase the stale) Cache Controller 3 Operand Cache No affection to WT request Execute on background (2) Search & Update BIC 0 Initiator Initiator Cache Controller 0 (3) WT Request (1) WT Request Snoop Controller BIC 3 Target Initiator Optimized System Bus (3) WT Response Response Cache Controller 3 (3) Erase Request Response Snoop Controller (2) Search Latency (3) WT Request No need to wait for snoop response 11

12 Mixed Coherency Protocol Need to consider the latest in other CPUs Write-through Copy-back Controller BIC 0 Initiator Cache Controller 0 Operand Cache Initiator Target Initiator Target (CPU1) Controller (1) WT Request (2) Request AA Merge Initiator (CPU0) WB Request AA 03 Dirty Data (CPU2) Target (3) Response (with dirty) Snoop Controller (CPU3) Cache Controller 3 Operand Cache Dirty BIC 3 Initiator System Bus 12

13 Difficulty of SMP OS Development Cache operation after process migration (Caused by time sharing processing) Conventional measure Flushing cache entries, accessed before, via inter-processor interrupt after process releases memory or virtual-physical address map is changed. Synonym problem (Caused by more than one virtual-physical address maps) Conventional measure Flushing the cache of synonym page during page allocation Preventing the synonym occurrence by using page coloring Problem in conventional measure Complicated to implement software Large software overhead Solution Broadcast of operand cache operating instructions (OCBI, OCBP, OCBWB) Hardware implementation of synonym detection and eviction 13

14 Operand Cache Operating Instructions (Conventional) Conventional Specification Operate only my own cache line Cannot operate other CPUs cache line Need inter-processor interrupt to operate others Example: Process Migration Process Migration Process X MOV.L VOID Not executed yet CPU #0 CPU #3 Dirty D$ Snoop Controller Cannot write back the dirty line D$ Process X MOV.L Executed Memory System Bus Cannot access the latest DMAC Memory Access after Process X 14 OCBWB: Write-back Cache Block

15 Broadcast of Operand Cache Operating Instructions Extended Specification Operate all CPUs cache by broadcast No need inter-processor interrupt to operate Reduce software overhead of using interrupt Example: Process Migration CPU #0 CPU #3 Dirty Broadcast via Snoop Controller D$ Snoop Controller D$ Process X MOV.L Executed System Bus Write Back Available the latest Memory DMAC Memory Access after Process X 15 OCBWB: Write-back Cache Block

16 Synonym Detection and Eviction (In the case of 4KB/Page) VPN[31:12] PPN[31:12] 1. Read Miss Adr(A) D$: 32KB/4way (Virtual Index - Physical Tag) V-Index [12:5] 0x00 A P-Tag[31:10] P-Index [12:5] Way 0 Way 1 Way 2 Way 3 (Physical Index - Physical Tag) P-Tag[31:10] V[12] Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 0x80 A 0 2. Read Miss Adr(B) Suppose = Physical Address (A) = Physical Address (B) 0x00 0x80 Synonym (Differs in VPN[12]) 3. Request from SNC 0x00 0x80 A A 0x00 Must not register Memory same address tag B Data 0x80 A B 0 1 Same Detection by SNC 0x00 Purge Request B 0x80 A B 0 1 from SNC Delete Delete SNC: SNoop Controller 16

17 RP1: Experimental Chip SH-4A CPU (including FPU) RAM K D$ 32K Shared Memory 128K I$ 32K SH-4A CPU (including FPU) RAM K D$ 32K I$ 32K SH-4A CPU (including FPU) RAM K D$ 32K SuperHyway Bus TM On-chip Interconnect DDR I/F SRAM I/F IP IP I$ 32K SH-4A CPU (including FPU) RAM K Bus Bridge I/O D$ 32K I$ 32K PCIe CPU #0 SNC CPU #2 Shared Memory CPU #1 CPU #3 IPs IPs PCIe CPG Process Technology Area I/D Cache Local Memory Performance Power Consumption 90-nm, 8-layer, Triple-Vth, Generic CMOS, 1.0V 3.88mm 2 (Each CPU excluding all memories), 7.28mm 2 (Each CPU) 32KB/4way set-associative (Each) I-LRAM 8KB, D-LRAM 16KB, URAM 128KB (Each CPU) 1.8 MIPS/MHz/CPU (Dhrystone 2.1) MHz (4-CPU Total) MHz 17

18 Application of Synonym-related Function to SMP OS OS Enhancement for SMP Applied: Linux Kernel (Not MP-ready for SuperH multi-core) Measurement: When kernel detects a synonym page, it flushes all entries of the page. Experiment (On evaluation board) Enhanced for hardware implementation of synonym-related function Executed shell command find for each CPU in parallel (Whole is stored in DDR) Not Enhanced (Using original synonym measurement) CPU Execution Time (sec) CPU CPU CPU CPU Enhanced CPU Execution Time (sec) CPU CPU CPU CPU % Performance Improvement 18

19 Summary SH-X3: SuperH multi-core for high-performance and low-power systems Efficient for both SMP and AMP Specification features for cache coherency Separation of system bus and snoop bus Centralized cache coherency by snoop controller Support of mixed cache coherency protocol Specification features for SMP OS development Broadcast of operand cache operating instructions (OCBI, OCBP, OCBWB) Hardware implementation for synonym problem (53% performance improved) Acknowledgement This work was supported by NEDO (New Energy and Industrial Technology Development Organization) P03022, a joint project of Renesas Technology Corp., Hitachi Ltd., and Waseda University. 19

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21 Backup Slides 21

22 Synonym Detection and Eviction (In the case of 4KB/Page) VPN[31:12] PPN[31:12] 1. Read Miss Adr(A) D$: 32KB/4way (Virtual Index - Physical Tag) V-Index [12:5] P-Tag[31:10] Way X 0x00 A (Physical Index - Physical Tag) P-Index [12:5] P-Tag[31:10] Way X V[12] 0x80 A 0 2. Read Miss Adr(B) 0x00 0x80 A 0x00 Must keep Overwrite 1:1 correspondence B 0x80 A B Request from SNC 0x00 0x80 A Purge Request 0x00 B 0x80 B 1 from SNC Different Detection by SNC SNC: SNoop Controller 22

23 Synonym Detection and Eviction (In the case of 4KB/Page) VPN[31:12] PPN[31:12] 1. Read Miss Adr(A) D$: 32KB/4way (Virtual Index - Physical Tag) V-Index [12:5] P-Tag[31:10] Way X P[12] (in P-Tag) (Physical Index - Physical Tag) P-Index [12:5] P-Tag[31:10] 0x00 Way X A 0x80 A 0 2. Read Miss Adr(B) 0x80 Overwrite A B Must keep 1:1 correspondence 0 1 0x00 0x80 A B 3. Request from SNC 0x80 B 1 Different Detection by Cache Controller 0x00 Invalidate Request to SNC 0x80 A B SNC: SNoop Controller 23

24 Application of Synonym-related Function to SMP OS OS Enhancement for SMP Applied: Linux Kernel (Not MP-ready for SuperH multi-core) Measurement: When kernel detects a synonym page, it flushes all entries of the page. Experiment (On evaluation board) Enhanced for hardware implementation of synonym-related function Freq. = (# of HW activation) / (# of request to SNC) Executed shell command find for each CPU in parallel (Whole is stored in DDR) Not Enhanced (Using original synonym measurement) CPU Activation Frequency of Function Execution Time (sec) CPU0 0.06% CPU1 0.05% CPU2 0.05% CPU3 0.05% Enhanced Activated by VPN[12]!= PPN[12] page mapping CPU Activation Frequency of Function Execution Time (sec) CPU0 0.16% CPU1 0.13% CPU2 0.17% CPU3 0.13% % Performance Improvement 24