SH4 RISC Microprocessor for Multimedia
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1 SH4 RISC Microprocessor for Multimedia Fumio Arakawa, Osamu Nishii, Kunio Uchiyama, Norio Nakagawa Hitachi, Ltd. 1 Outline 1. SH4 Overview 2. New Floating-point Architecture 3. Length-4 Vector Instructions 4. 3DCG Performance 5. Double Precision Support 6. Conclusions 3DCG: Three Dimension Computer Graphics 2
2 SH4 Overview - Hitachi's SuperH Series Family - For Consumer Multimedia Systems Home Video Game, Handheld PC - Excellent Performance with Consumer Price 300 VAX MIPS - Excellent 3DCG-Performance with Consumer Price 5.0 M Polygons/sec* - IEEE 754 Standard Floating-point Architecture Double-precision with Hardware Emulations * measured with an original simple geometry benchmark 3 SH4 Specifications Technology Voltage Frequency Performance Cache TLB Interfaces Peripherals 0.25 µm CMOS, 5 Layer Metals 1.8 V (I/O: 3.3 V) 167 MHz (internal) / 83,55, etc. MHz (I/O) 300 MIPS (Dhrystone), 1.17 GFLOPS (peak) 8/16 KB (Inst./Data) Direct-mapped 4/64-entry (Inst./Unified) Fully-associative SRAM, DRAM, SDRAM, burst ROM, PCMCIA DMAC, SCI, RTC, Timer 4
3 Pipeline Stages - Simple Five-stage Pipelines - Two-way Superscalar Integer Inst. Dec. Reg. Read Exec. --- Write Back Floating Point Inst. Fetch Inst. Dec. Reg. Read 1st Exec. 2nd Exec. 3rd Exec. Write Back Load / Store Inst. Dec. Reg. Read Addr. Gen. Memory Access Write Back Branch Inst. Dec. Addr. Gen. Target Inst. Fetch 5 Superscalar Issue Combinations Integer (INT) Floating Point (FP) Load / Store (LS) Branch (BR) Both INT & LS (BO) Not Superscalar (NS) INT FP LS BR BO NS X O O O O X O X O O O X O O X O O X O O O X O X O O O O O X X X X X X X INT: Add, Subtract, Shift, etc. FP: Floating-point Add, Subtract, Multiply, Divide, etc. LS: Load/Store/Transfer from/to Integer/Floating-point Register, etc. BR: Branch Always/Conditionally, etc. BO: Move between Integer Registers, Integer Compare, etc. NS: Load to Control Register, etc. 6
4 Floating-point Arch. Enhancement - Two Sets of 16 Single Precision Registers - The extra set fits 4 by 4 matrix storage - Length-4 Vector Instructions - Inner Product - Transform Vector - Register Pair Load/Store/Transfer Instructions - Enough bandwidth for vector operations - Double Precision Format Mode 7 Floating-point Instructions - Common - FADD (add) - FSUB (subtract) - FMUL (multiply) - FDIV (divide) - FSQRT (Square Root) - FCMP (Compare) - FNEG (Negate) - FABS (Absolute Value) - FLOAT (Convert Integer to float) - FTRC (Convert float to Integer) - FMOV (Move from/to Register) - Single Precision Mode Only - FMAC (multiply-accumulate) - FIPR (Inner Product) - FTRV (Transform Vector) - Double Precision Mode Only - FCNVDS (Convert Double to Single) - FCNVSD (Convert Single to Double) 8
5 Inner Product Instruction - 16 Registers = 4 (Length-4) Vector Registers fv0 = (fr0,fr1,fr2,fr3 ) fv4 = (fr4,fr5,fr6,fr7 ) fv8 = (fr8,fr9,fr10,fr11) fv12 = (fr12,fr13,fr14,fr15) - Operation frn' = (fvm,fvn) - 1 cycle Pitch - 4 cycle Latency - Vector Normalization, Intensity Calculation, Surface Judgment m,n: 0,4,8,12 n'= n+3 9 Inner Product Hardware (Mantissa) - Calculating fr7 = (fv0,fv4) Floating-point Register File fr0 fr4 fr1 fr5 fr2 fr6 fr3 fr7 8 read 1 write Multiplier Multiplier Multiplier Multiplier fr0 * fr4 fr1 * fr5 fr2 * fr6 fr3 * fr7 Shifter Shifter Shifter Shifter 4-input Adder fr0 * fr4 + fr1 * fr5 + fr2 * fr6 + fr3 * fr7 4-to-2 Compressor & 2-input Adder Normalizer Rounder 10
6 Inner Product Hardware (Exponent) - Calculating fr7 = (fv0,fv4) Floating-point Register File fr0 fr4 fr1 fr5 fr2 fr6 fr3 fr7 Adder fr0 + fr4 Adder fr1 + fr5 Adder fr2 + fr6 Adder fr3 + fr7 Maximum Exponent Selector Subtracter Subtracter Subtracter Subtracter Normalizer Rounder Shift Count Shift Count Shift Count Shift Count 11 Inner Product Accuracy - Inner Product Inst. is an Approximate Inst. - No Accurate Intermediate Value (the width is too wide to implement) - More Accurate than the Worst Order Multiply and Add Inst. Combinations - Maximum Error: (Maximum Product x 2-25 ) + (Result x 2-23 ) - If source operands are rounded values, this is enough accuracy For example: 4 Products are 2, -2, 1, 0. Accurate Result = 1. Inner Product Inst. Result = 0. 12
7 Inner Product v.s. SIMD Multiply-Add Peak Performance Latency Register Port (Read/Write) Normalizer & Rounder Floating-point Hardware Inner Product 1 4 8/ Multiply-Add 1) / ) 3) 4) 1) Inner Product Inst. and 4 Multiply-Add achieve the same peak performance, which is one inner product per cycle. 2) SH4 takes 3 cycles for Multiply-Add. 4 x 3 = 12. 3) Eight more cycles must be filled with independent insts. for the peak performance with SIMD architecture. 4) Twice more hardware is necessary for SIMD architecture. 13 Elastic Pipeline - Pipeline stages become 4 cycles for vector Inst. - In-Order Issue, Out-of-Order Completion FX F1 F2 AG MA WB F3 WB Floating-point Pipeline (Vector) Load/Store Pipeline - Only Floating-point Non-Vector Arithmetic Inst. right after Vector Inst. is interlocked. FX F1 F2 F1 F3 WB : Instruction Decode, : Register Read, FX,F1,F2,F3: Floating-point Execution, AG: Address Generation, MA: Memory Access, WB: Register Write Back F2 Interlock with Resource Conflict Floating-point Pipeline (Vector) F3 Floating-point Pipeline WB (Non-Vector) 14
8 Transform Vector Instruction - Extra 16 Registers = 4 by 4 Matrix matrix = - Operation fvn = matrix fvn - 4 cycle Pitch, 7 cycle Latency - Coordinate Transformation, Coordinate Transformation Matrix Generation - No Work Registers xf0 xf4 xf8 xf12 xf1 xf5 xf9 xf13 xf2 xf6 xf10 xf14 xf3 xf7 xf11 xf15 n: 0,4,8,12 xf: extra floating-point register 15 Why Transform Vector Instruction? - Transform Vector Operation = 4 Inner Product Insts.? NO!! - Modification for Transform Vector: frn' = (xvm,fvn) m: 0,1,2,3, n: 0,4 n'= n+m+8 "fv8 = matrix fv0" is divided into 4 Inner Products: - 4 More Work Registers - Complicated and More Operands - No Generality (Just for Transform Vector) - Transform Vector Inst. is Better. xv0 = (xf0, xf4, xf8,xf12) xv1 = (xf1, xf5, xf9,xf13) xv2 = (xf2, xf6, xf10,xf14) xv3 = (xf3, xf7, xf11,xf15) fr8 = (xv0,fv0) fr9 = (xv1,fv0) fr10 = (xv2,fv0) fr11 = (xv3,fv0) 16
9 Transform Vector Implementation fv0 = Matrix fv0 FX F1 F2 Reg. Read F3 WB FX F1 F2 fr0 = (xv0,fv0) F3 WB FX F1 F2 F3 WB FX F1 F2 Reg. Write fr1 = (xv1,fv0) fr2 = (xv2,fv0) F3 WB fr3 = (xv3,fv0) - All reg. reads complete before first reg. write. No work regs. are necessary. : Instruction Decode, : Register Read, WB: Register Write Back FX,F1,F2,F3: Floating-point Execution 17 Pair Load/Store/Transfer Mode - Normal Mode: - 4-bit Reg. Field represents 16 Regs. of one set. - Set specifier must be changed for another set access. - Pair Mode: - 4-bit Reg. Field represents 16 Pair Regs. of all sets. - All Regs. can be accessed. - Transform Vector Throughput: 1 vector / 4 cycles - Load/Store Throughput: 2 vectors (4 pairs) / 4 cycles - Enough for Storing Previous Result Vector and Loading Next Vector during Transform Vector 18
10 Simple 3DCG Geometry Benchmark y screen (z=1) x (2) normal vector (1) (3) z ray vector triangle polygon (1) Coordinate Transformation (2) Perspective Transformation (3) Intensity Calculation 19 3DCG Geometry Performance M polygons/sec M M 0 without New Arch. with New Arch. 20
11 Double Precision Support - Floating-point Libraries for WindowsCE - Double Precision - ANSI/IEEE 754 Standard - Emulation with Single Precision Hardware - Best cost-performance way - Peak performance is 27.8 MFLOPS. - Software emulation is 20 times slower. - Double precision hardware is 6 times faster but 2.5 times more. - New Double Precision Mode - Single's code becomes double's code. 21 Double Precision Hardware - Mantissa Part - Add/Subtract/Multiply/Convert: Add Feedback Path Multiplier (32b) Multiplicand (32b) Addend (32b/64b) Addend Aligner Multiply- Add Block Single : 24b x 24b + 73b Integer: 32b x 32b + 64b Aligned Addend (73b) Feedback Path for Double Precision Emulation (65b) Normalizer Rounder Pre-normalizing Result (73b) Result (32b) - Divide/Square Root: Extend from 24 to 53 bits - Exponent Part: Extend from 8 to 11 bits 22
12 Double Precision Multiply - Four multiply-adds generate product - Sticky bit is generated from partial products - required width: 106b --> 55b Mantissa (53b) Higher (21b) Lower (32b) Lower x Lower (64b) + = + = + = Lower x Higher (53b) Higher x Lower (53b) Higher x Higher (42b) Product (53b + guard/round) sticky bit 23 Conclusions - Excellent Performance with Consumer Price VAX MIPS - Excellent 3DCG-Performance with Consumer Price - New Inner Product & Vector Transformation Insts M Polygons/sec GFLOPS (peak with the new insts.) - IEEE 754 Standard Floating-point Architecture - Double-precision with Hardware Emulations MFLOPS (peak) 24
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