Low-Power Processor Solutions for Always-on Devices

Transcription

1 Low-Power Processor Solutions for Always-on Devices Pieter van der Wolf MPSoC 2014 July 7 11, Synopsys, Inc. All rights reserved. 1

2 Always-on Mobile Devices Mobile devices on the move Mobile devices are becoming context-aware Use sensors to monitor movement, heart rate, sound, etc. Enables new applications Smarter mobile devices performing new functions Changes the way users interact with the devices Always-on Always listening Microphone input Voice activation Always watching Camera input Face activation, wake-on-gesture Always sensing Sensor input Motion sensing, health & fitness monitoring Always connected Wireless links Cloud data push services, Bluetooth LE 2014 Synopsys, Inc. All rights reserved. 2

3 Wearables Always-on Mobile Devices Devices with different characteristics Android Hi-perf multicore CPU High-res graphics / video Cellular / WiFi / BT Off-chip DRAM Battery > 2000mAh Smartphone Glass Android Wear Lower-res graphics Smart watch Health / fitness band RTOS Low-power RISC-DSP No graphics Bluetooth LE On-chip memory Battery < 300mAh 2014 Synopsys, Inc. All rights reserved. 3

4 Wearables Always-on Mobile Devices Processors for always-on processing Video Applic proc GFX Sensor proc Separate core for always-on processing Smartphone Interconnect DDR Conn Periph Sensors Wake-up application processor only when needed Low power Glass Smart watch Processor for always-on Operate in different SoC contexts Fmax typically < 100 MHz Lowest power in each mode Mixed control and DSP > 10x lower power than application processor Battery in wearable needs to last weeks Multiple modes E.g. voice activation: Standby / detection mode Recognition mode Health / fitness band Sensor BT-LE Periph Sensors proc Interconnect Mixed control and DSP DSP for processing of sensor inputs 2014 Synopsys, Inc. All rights reserved. 4

5 Voice Activation Detect Sound detected False positive Recognize Wake-up Command recognized Detect System mostly resides in detect state, needs lowest power Very light workload (< 1 MHz) Recognize Activated when sound is detected Applies DSP algorithms to recognize voice command(s) Higher workload (5 10 MHz for single phrase recognition) Wake-up Trigger action in application 2014 Synopsys, Inc. All rights reserved. 5

6 Memory Configurations Closely coupled memories APB ICCM CPU Mem DMA DCCM Per1 Per2 AHB I$/D$ Per3 AHB DMA stores data in DCCM while processor sleeps DMA wakes up processor when buffer available After wake-up, processor does not have to access data over AHB bus No energy spent in bus accesses Lower latency processor can run at lower frequency 4.2x Sensor hub application Analysis of processing stage Core and bus at same frequency Bus-based with instruction fetch queue 2014 Synopsys, Inc. All rights reserved. 6

7 Voice Activation Power management Dynamic power (uw) 15 ms Detect Recognize Voice activation detect mode At 10 MHz processing duty cycle < 2.5% Opportunity for energy savings But need to allow access to DCCM for DMA Would be no different with memory on AHB bus Time 2014 Synopsys, Inc. All rights reserved. 7

8 > 20x Voice Activation Power management Dynamic power (uw) 15 ms Detect Recognize Sleep between executions of detect function Fast sleep and wake-up Low sleep power simple and effective Frequency scaling Saves sleep power (only) Requires clock domain crossings Voltage switching Saves leakage power as well Requires switch, clamps, data retention, PMU Sleep power Time 2014 Synopsys, Inc. All rights reserved. 8

9 Instruction Set Architecture It s all about power energy Minimize energy per function power x cycles Mixed control and DSP Good power and efficiency for RISC and DSP Code size Memory footprint, active memory power, I-cache miss rate Data types Fractional Q31, Q15, Q7 DSP instructions MUL/MAC operations Rounding & saturation Vector operations 2x16 & 4x8 Complex (16+16)x(16+16) Vector unpacking Vector 16x16 MAC acc.lo += a.lo * b.lo acc.hi += a.hi * b.hi Dual 16x16 MAC Inner-product style acc += a.lo * b.lo + a.hi * b.hi 2014 Synopsys, Inc. All rights reserved. 9

10 Energy Consumption For DSP workloads Q31 Q15 Energy consumption for categories of DSP functions Logic dynamic energy For Q31 & Q15 DSP functions Small code size Code size Q31: 57% Code size Q15: 89% Low power implementation Unified MUL/MAC unit Aggressive clock gating Operand gating / isolation Configurability & extensibility 2014 Synopsys, Inc. All rights reserved. 10

11 Energy Consumption For RISC and DSP workloads Note: energy consumed for executing fixed workloads 2014 Synopsys, Inc. All rights reserved. 11

12 ARC EM Processors Combining High Efficiency Control & Digital Signal Processing Power & Area Efficient Processors based on Extensible ARCv2DSP Architecture ARC EM Processors DesignWare ARC Floating Point Unit (FPU) ARC Processor EXtensions (APEX) ARCv2DSP Instruction Set Architecture (ISA) Instr. CCM IFQ Instr. Cache Execute 3 Stage Pipeline Memory Protection Unit Licensable Option EM5D Data Cache Data CCM DMP Memory MUL/MAC 32x32 Commit Divider Interrupt Controller Up to 2MB Instruction and Data CCMs EM7D I & D CCMs plus I & D Caches (up to 32K) Debug cjtag JTAG Real-Time Trace ARCv2DSP ISA adds over 100 new DSP-focused instructions Vector/SIMD, Matrix, Saturating & Complex Configurable DSP hardware features New EM5D & EM7D cores optimized for ultra low-power control and DSP Energy-efficient 3-stage RISC pipeline Unified single cycle 32x32 MUL/MAC unit Energy-efficient signal processing of voice/speech, audio and sensor data Optional Floating Point Unit (SP & DP) Easy software development with rich DSP software library & C/C++ Compiler 2014 Synopsys, Inc. All rights reserved. 12

13 Conclusions Need to optimize at all levels for low energy Efficient ISA for mixed control and DSP Energy efficient access to memories (CCMs) Low power hardware implementation (clock & operand gating) Effective sleep modes Configurability and extensibility Significant energy reductions can be achieved Good application fit is key Good design choices matter Flexibility is key to fit in different SoC contexts Memory architecture Power management schemes 2014 Synopsys, Inc. All rights reserved. 13

14 2014 Synopsys, Inc. All rights reserved. 14 Thank You