Achieves excellent performance of 1,920 MIPS and a single-chip solution for nextgeneration car information systems

Transcription

1 Renesas Technology to Release SH7776 (SH-Navi3), Industry s First Dual-Core SoC with Built-in Image Recognition Processing Function for Car Information Terminals Achieves excellent performance of 1,920 MIPS and a single-chip solution for nextgeneration car information systems Tokyo, January 19, 2009 Renesas Technology Corp. today announced the SH7776 (SH-Navi3), a dual-core system-on-chip (SoC) device with on-chip enhanced graphics functions and a highperformance image recognition processing function for the next generation high-performance car information terminals that evolved from car navigation systems. The SH7776 (SH-Navi3) integrates two CPU cores on a single chip and achieves superior processing performance of 1,920 million instructions per second (MIPS), twice that of comparable earlier single-chip SoC products from Renesas Technology. Sample shipments will begin in April 2009 in Japan. Renesas Technology has the top share* 1 in the worldwide market for microprocessors for car navigation systems, and the SH-Navi Series,* 2 a single-chip SoC device implementing functions essential for high-performance car navigation systems such as 3-D graphics, is already used in many high-end products. Car navigation systems will be evolving into next-generation car information centers, which play the central role in car information control to assure convenience, safety, and environmental considerations while driving. The new SH7776 dual-core SoC device delivers on a single chip the performance and functions essential to such a next-generation car information center. It enables display of colorful and realistic 3-D graphics use of a multimedia and information communication as well as navigations, display of 2-D/3-D graphics use of a graphical user interface (GUI)* 3 for enhanced user-friendliness, and image recognition for functions such as lane detection and preceding vehicle tracking. In addition, functions for strengthening the system reliability of the dualcore architecture are embedded on the chip. The features of the SH7776 (SH-Navi3) are summarized below. (1) Dual-core architecture for excellent processing performance up to 1,920 MIPS The SH7776 (SH-Navi3) integrates dual Renesas Technology SH-4A high-performance 32-bit CPU cores, which have a proven track record in applications such as car navigation systems, and delivers superior processing performance of up to 1,920 MIPS (960 MIPS 2) when operating at 533 MHz together with low power consumption. This is approximately double the processing performance of Renesas Technology s second-generation SoC product for car navigation systems (the SH-Navi2) and fully supports the high-speed and complex information processing needed to display a wide variety of graphics and image recognition.

2 (2) 3-D graphics engine for colorful and more realistic 3-D images as well as 2-D and 3-D graphics processor The 3-D graphics engine incorporates PowerVR* 4 SGX, sophisticated 3-D graphics IP from the British company Imagination Technologies Limited (IMG). It enables polygon performance of approximately twice that of PowerVR MBX, which is used in the earlier SH-Navi1 and SH-Navi2. This provides support not only for 3-D rendering in navigation applications, but also for multimedia applications such as Human Machine Interface (HMI) that demand more colorful and realistic 3-D rendering. The SH7776 (SH-Navi3) is also provided with a 2-D and 3-D graphics processor for detailed map rendering and more easy-to-use operation screens. Supported features include 2-D rendering functions such as bold- line rendering as well as 3-D rendering functions such as triangle 3-D rendering, for enhanced three-dimensionality, and texture mapping, for more realistic textures. They enable representation of a wide range of 3-D objects (such as high-rise buildings) in maps and a detailed and high-quality GUI as well as maps, icons, and menus. (3) Industry s first dual-core SoC product for car navigation systems with on-chip image recognition processing function The SH7776 (SH-Navi3) is the industry s first dual-core SoC product to incorporate an image recognition processing function such as lane detection for driving assist systems. Renesas Technology already mass-produces the SH7774 (SH-Navi2V) with on-chip image recognition processing function. The new SH7776 (SH-Navi3) builds on the track record of its predecessor to deliver even better performance, achieving approximately 3.5 times faster processing through greater internal parallelism and doubled bus width. It can execute multiple external environment recognition programs simultaneously and in real time, for example lane detection and detection and tracking of preceding vehicles. This facilitates the contribution to improving driving safety. <This image recognition processing intellectual property (IP) incorporated in SH7776 (SH-Navi3) was developed jointly with Hitachi, Ltd.> In addition, the distortion compensation module enables transformation into any shape of image data captured by a camera. For example, image data from a camera fitted with a fisheye lens could be used to generate a bird s-eye view of the periphery of the vehicle. (4) DDR3-SDRAM memory interface and PCI Express interface for ultra-high-speed data transfer The SH7776 (SH-Navi3) is the industry s first dual-core SoC product for car navigation systems to incorporate a DDR3-SDRAM memory interface which is a two-channel 16-bit dedicated bus interface operating at 533 MHz for connecting high-speed DDR3-SDRAM, enabling ultra-highspeed data transfer at a maximum of 4.27 gigabytes per second. Both channels of the dedicated bus can be accessed at the same time. In addition, the dedicated I/O of PCI Express interface* 5 allows high-speed transfer of data at a maximum of 250 megabytes per second to and from an external device equipped with a PCI Express interface. (5) Comprehensive range of peripheral functions improving the user-friendliness of car information terminals, including serial ATA interface The SH7776 (SH-Navi3) integrates on-chip rich peripheral modules required by car navigation systems, including a serial-ata interface* 6 achieving high-speed connection to hard disks, sound interfaces including an audio encoder, a USB 2.0 Host/Function interface, a TS interface for receiving terrestrial digital TV broadcasts, and a GPS* 7 baseband processing module. This full and varied complement of peripheral functions makes it possible to reduce the total number of components and achieve a high-performance system at reduced cost.

3 (6) Support for enhanced reliability and reduced development time for dual-core systems The dual-core architecture supports the following two types of processing, providing flexibility to meet a wide range of customer requirements. Symmetric multiprocessing (SMP), in which the operations of a single program running under a single OS are divided between two CPU cores for parallel processing, is supported. Asymmetric multiprocessing (AMP), in which different OSes (or multiple instances of the same OS) and completely different programs run on each of the CPU cores, is supported. Note: In this case, a mechanism allowing both OSes to interoperate and a mechanism for separating the operations of the two OSes (a mechanism to prevent one CPU from accessing and changing data in some area of memory while the other CPU is performing processing that accesses the same area of memory) are incorporated into the chip. Since such support, which is usually implemented in software, is implemented in hardware (in the SH7776 chip), high reliability in the development of systems incorporating a dual-core processor can be achieved. < Product Background > In recent years, car information terminals such as car navigation systems have come to offer more advanced navigation functions, including 3-D displays, improved legibility, and enhanced realism. Functions increasingly in demand include display capabilities for enhanced ease of use, real-time access to information via mobile phone links, recreational information system capabilities such as music and video playback, reception of terrestrial digital TV broadcasts, and even some of the functions of safe driving assist systems. As these systems continue to become more multifunctional and sophisticated, they are evolving into a nucleus of vehicle information control functionality intended to assure convenience, safety, and environmental considerations while driving. Ever better performance is demanded of the processors or system-on-chip (SoC) devices used to process the enormous volumes of information required by such applications, but meeting this need through more ultrafine processes or faster operating speeds raises problems such as increased power consumption. In response, the use of multi-core technology, in which multiple CPUs are integrated on a single chip and processing tasks are handled by the individual CPU cores either in parallel or in distributed fashion to increase efficiency, is expanding as a way to boost CPU performance and reduce power consumption at the same time. Renesas Technology embraced multi-core technology early on, launching the SH7786 dual-core processor with two SH-4A CPU cores (max. 1,920 MIPS [when operating at 533 MHz]) in In response to demand for multi-core SoC devices for vehicle information terminals, Renesas Technology has developed the SH7776 dual-core SoC as a new addition to the SH-Navi Series, which has contributed to the advancement of car navigation systems and has a large market share and established track record in the car navigation system field. The SH7776 integrates two SH-4A CPU cores, supports high-performance and faster graphics functions, an image recognition processing function, and provides a number of high-functionality interfaces.

4 < Product Details > CPU core The SH7776 employs a core architecture that integrates two of Renesas Technology s SH-4A 32-bit reduced instruction set computer (RISC) CPU cores. It supports both symmetric multiprocessing (SMP), in which the processing of a single program running under a single OS is divided between two CPU cores, and asymmetric multiprocessing (AMP), in which different OSes (or multiple instances of the same OS) and completely different programs run on each of the CPU cores. This allows the customer maximum flexibility in system configuration. A snoop controller is provided to support SMP. It handles data updates to the internal cache from the two CPU cores and maintains cache coherency. In addition, the clock frequency and any of four low-power modes can be set independently for each CPU. For example, when only one CPU core is operating, the other CPU core can be set to a lowpower mode to reduce power consumption. In this way the overall power consumption can be kept to a minimum while accommodating the processing requirements of the system. Each CPU core is also equipped with a floating-point processing unit (FPU) with a maximum operating frequency of 533 MHz. These FPUs support single-precision and double-precision calculations and can achieve a maximum processing performance in single-precision mode of 7.46 GFLOPS (giga [billion] floating-point operations per second). This can speed up codec processing of still image and video, for example. In addition, most existing software resources developed for products incorporating SoC devices built around the SH-4A core, such as the SH-Navi1, can be reused with the SH7776 (SH-Navi3) without modification. This helps reduce the time needed for system development. 3-D graphics engine The cutting-edge shader engine, incorporating the PowerVR SGX 3-D graphics IP from IMG, supports shadow processing for each peak as well as for individual pixels, enabling more realistic image rendering that previously possible. Use of the industry-standard API OpenGL ES* 8 ensures the scalability of embedded applications. Image recognition processing function The image processing required to recognize aspects of the driving environment based on image data from cameras and other sensors. The SH7776 incorporates an image recognition processing IP that delivers processing performance approximately 3.5 times faster than the IP of the earlier SH7774 through greater internal parallelism and doubled bus width. Internal processing has been upgraded from 8-bit to 16-bit format to provide support for high-resolution cameras. Among the many other on-chip peripheral functions ideal for vehicle image recognition processing systems are a threechannel video input interface and a two-channel display function with support for resolutions up to WXGA (1, pixels). There are also plans to release an image recognition library product with approximately 200 functions to simplify development of image recognition applications. DDR3-SDRAM memory interface The SH7776 has a two-channel 16-bit dedicated bus interface operating at 533 MHz for connecting high-speed DDR3-SDRAM, enabling ultra-high-speed data transfer at a maximum of 4.27 gigabytes per second. Both channels of the dedicated bus can be accessed at the same time. For example, separate blocks of DDR memory can be assigned to the graphical display and to a CPU, respectively, allowing advanced display of graphics and high-speed processing by the CPU to take place simultaneously, or separate blocks could be assigned to the two CPU cores.

5 The assignment of resources can be tailored to the product concept, providing an easy way to boost system performance. Package The package is a 653-pin BGA (25 mm 25 mm). Development environment A multi-core version of the E10A-USB on-chip debugging emulator is available as a development environment. It supports concurrent execution, concurrent break, single-cpu break, and re-execution as well as synchronous debugging functions, providing plenty of flexibility for developers. A user system development reference platform offering the following features is also available, enabling the user to carry out efficient system development. (1) Includes car information system oriented peripheral circuits, providing a user system actual device verification environment. (2) Can be used as a software development tool for application software, etc. (3) Allows easy addition of custom user functions. < Supplements to Development Environment > In addition to the development environment described above, distributed function system building support technology is currently under development to facilitate the development of distributed function systems utilizing multi-core products. It will be available in late FY2009. In a distributed function system, the individual CPU cores of a multi-core processor are assigned to separate systems (domains) with different characteristics or functions. The individual CPU cores interoperate to provide integrated operation for the system as a whole. Renesas Technology s distributed function system building support includes communication interface technology to enable integration between the OSes of multiple domains: EXREAL-ExARIA* 9 and technology to prevent interference between OSes: EXREAL-ExVisor* 9. It eliminates the need to build complex new software for multi-core interoperation and allows reuse of many existing software resources originally designed for single-os systems. This makes it possible to build in a short amount of time distributed function systems utilizing multi-core products. In addition, it enables highly reliable operation of multiple CPU cores running different OSes. Renesas Technology will continue to contribute to the progress of the car navigation system market by releasing new products in a timely manner in response to market demand, developing new SoC devices with multi-core technology for enhanced CPU performance, increased speed, and superior functions for high-end systems, and moving forward with products offering performance and functions optimized for low-end and midrange systems. < Notes > Notes: 1. Source: Renesas Technology estimate based on figures from Strategic Analytics Inc. 2. SH-Navi Series: A series of SoC products for information terminals such as car navigation systems that are built around the SuperH 32-bit RISC CPU core from Renesas Technology. At present three products in the series are in mass production, including the SH7774 with an on-chip image recognition processing engine. SuperH is a trademark of Renesas Technology Corp. 3. Graphical user interface (GUI): A user interface in which the information is graphically displayed and can be operated intuitively by pointing devices and the like.

6 4. PowerVR is a trademark or a registered trademark of Imagination Technologies Limited of the U.K. 5. PCI Express interface: An I/O interface for serial data transfer. 6. Serial ATA interface: An extension of the IDE (ATA) standard for connecting personal computers and storage devices such as hard disk drives. 7. GPS stands for global positioning system. 8. OpenGL ES is a programming interface for 3-D graphics processing developed by US company Silicon Graphics Inc. as a leader and characterized by its platform-independence. It is API for embedded systems corresponding to a subset of OpenGL. The Khronos Group, a standard-setting organization, formulates the specification. 9. EXREAL-ExARIA and EXREAL-ExVisor: Developed in collaboration with Hitachi, Ltd., these are technologies for distributed-function systems employing multi-core architecture that are applied in Renesas Technology s Exreal Platform, which provides an integrated solution covering system-on-chip (SoC) device development through development of the customer s system. (Exreal Platform is a mother platform that provides a basis for the development of separate field-specific platforms.) * Other product names, company names, or brands mentioned are the property of their respective owners. < Typical Applications > Car information terminals: Car navigation systems, etc. Game consoles, etc. < Prices in Japan > *For Reference Product Name Package Sample Price [Tax Included] (Yen) SH7776(R8A77760DBGV) 653-pin BGA 12,000

7 < Specifications > Item Product No. Power supply voltage Max. operating frequency Processing performance SH7776 Specifications R8A77760DBGV 1.25 V (internal)/3.3 V, 1.5 V (external) 533 MHz CPU cores SH-4A core 2 On-chip RAM 1,920 MIPS, 7.46 GFLOPS (at 533 MHz) ILRAM: 8 KB + OLRAM: 16 KB Cache memory Cache memory: Divided into 32 KB instruction/32 KB data 2 4-way set associative, cache coherency support External memory Support for connecting two channels of DDR3-SDRAM (DDR1066) modules via dedicated DDR3 bus with 16-bit bus width (Both channels of the dedicated bus can be accessed at the same time) Max. operating frequency: 533 MHz Support for direct connection of SRAM or ROM to expansion bus Expansion bus Address space: 64 MB 6 Main on-chip peripheral Renesas graphics processor (2-D/3-D), functions 3-D graphics engine Display unit 2 channels Video input interface 3 channels Image recognition processing accelerator Distortion compensation module Serial ATA interface SD* 1 host interface 2 channels AAC encoding accelerator I/O for sound interfaces 5 channels USB 2.0 Host/Function interface TS interface GPS baseband processing module FM multiplex decoder PCI Express interface Dedicated DMAC 26 channels Controller Area Network (CAN) * 2 interface 1 channel Media local bus interface 1 channel Serial communication interface (SCIF) 9 channels I 2 C bus interface 2 channels Serial peripheral interface (HSPI) 2 channels Media transaction serial bus (MTS-B) interface Remote control interface 1 channel Timer 11 channels A/D converter interface (12-bit) 1 channel Interrupt controller (INTC) Clock pulse generator (CPG): Integrated PLL On-chip debug function Temperature sensor

8 Low-power modes Package Sleep mode Light sleep mode Clock stop mode DDR-SDRAM power supply backup mode 653-pin BGA (25 mm 25 mm) Notes: 1. The SD memory card is a small memory card whose specification was originally formulated by 3C (Panasonic Corporation, Toshiba Corporation, and SanDisk Corporation) and has been progressively extended by the SD Card Association (SDA). It is necessary to obtain an SD card license in order to use the SD memory card interface in a product. 2. CAN stands for Controller Area Network, an automotive network specification promoted by Robert Bosch GmbH of Germany. -###- *** Information contained in this news release is current as of the date of the press announcement, but may be subject to change without prior notice. ***