Academic Course Description. EM2101 Computer Architecture

Transcription

1 Academic Course Description SRM University Faculty of Engineering and Technology Department of Electronics and Communication Engineering EM2101 Computer Architecture Third Semester, (Odd Semester) EM2101 Computer Architecture Course (catalog) description To introduce students with general concepts of computer architecture basics to enable them to use the processors effectively Compulsory/Elective course: Elective course Credit hours: 3 credits Course coordinator K.Vadivukkarasi, Assistant Professor (OG), Department of ECE Instructor(s) Name of the instructor Mrs. K.Vadivukkarasi Class handl ing Office location Office phone Consultations A 1203 vadivukarasi.k@ktr.srmuniv.ac.in All day oder-1.35pm to 3.20pm Relationship to other courses Pre-requisites : Nil Reference books and/or required materials 1. Kai Hwang & Naresh Jotwani, Advanced Computer Architecture, McGraw Hill, Inc John L. Hennessey and David A. Patterson, Computer Architecture: A Quantitative Approach, 3rd Edition, Morgan Kaufmann, Class schedule: Three 50 minutes lecture sessions per week, for 15 weeks Section M.Tech EST Schedule Day1,Day 3 &Day to Broad area: Communication Signal Processing Electronics VLSI Embedded Page 1 of 5

2 Test Schedule S. No. Test Portions Duration 1 Cycle Test-1 Session 1 to 18 2 Periods 2 Model Test Session 1 to 45 3 Hours Course objectives Course Objective 1. To familiarize with fundamentals of computer design. 2. To learn parallel and pipeline architectures. 3. To learn principles of parallel programming. Syllabus Contents UNIT I - PROCESSOR AND MEMORY HIERARCHY (9 hours) Multiprocessors and Multicomputers Multivector and SIMD computers Architectural Development Tracks Processors and Memory Hierarchy Advanced Processor Technology Superscalar and vector Processor Memory Hierarchy technology-virtual memory technology. UNIT II - FUNDAMENTALS OF COMPUTER DESIGN (9 hours) Elements of modern computers-system attributes to performance-bus, Cache and Shared memory-bus Systems Cache Memory Organizations Shared memory Organization Sequential and weak consistency models. UNIT III - PARALLEL AND SCALABLE ARCHITECTURES (9 hours) Multiprocessor System Interconnects Cache Coherence and Synchronization Mechanisms Message- Passing Mechanisms Vector Processing Principles Multivector Multiprocessors Performance-Directed Design Rules Fujitsu VP2000 and VPP500 SIMD Computer Organizations Implementation models The MasPar MP-1 ArchitectureLatency - Hiding Techniques Principles of Multithreading Scalable and Multithreaded Architectures - The Tera Multiprocessor System. UNIT IV - PIPELINING AND SUPER SCALAR TECHNIQUES (9 hours) Introduction Basics of a RISC Instruction set Implementation of five stage Pipeline for a RISC processor Performance issues hurdle of pipelining simple implementation of MIPS extending the MIPS pipeline to handle multicycle operations cross cutting issues. UNIT V - SOFTWARE FOR PARALLEL PROGRAMMING (9 hours) Parallel programming models parallel languages and compliers code optimization and scheduling scalar optimization with basic blocks code generation and scheduling trace scheduling compilation parallelization and wave fronting software pipelining parallel programming environments Y-MP, Paragon and CM-5 environments synchronization and multiprocessing modes principles of synchronization - multiprocessor execution modes shared-variable program structures locks for protected access semaphores and applications message-passing program development. Page 2 of 5

3 Teaching plan SESSION TOPICS TEXT / CHAPTER UNIT-I 1 Multiprocessors and Multicomputer [1] chapter(s) -1 2 Multivector and SIMD computers [1] chapter(s) -1 3 Architectural Development Tracks [1] chapter(s) -1 Design Space of Processors & Instruction Set [1] chapter(s) -4 4 Architectures 5 CISC Scalar Processors [1] chapter(s) -4 6 RISC Scalar Processors [1] chapter(s) -4 7 Superscalar and vector Processor [1] chapter(s) -4 8 Memory Hierarchy technology [1] chapter(s) -4 9 Virtual memory technology [1] chapter(s) -4 UNIT-II 10 Elements of modern computers [1] chapter(s) System attributes to performance [1] chapter(s) -1 Backplane Bus Specification, Addressing and Timing [1] chapter(s) Protocols Arbitration, Transaction and Interrupt, IEEE Futurebus [1] chapter(s) and other Standards Cache addressing models & Direct Mapping and [1] chapter(s) Associative Caches Set-Associative and Sector Caches & Cache [1] chapter(s) Performance Issues Shared memory Organization- Interleaved Memory [1] chapter(s) Organization, Bandwidth and Fault Tolerance 17 Memory Allocation Schemes [1] chapter(s) Sequential and weak consistency models. [1] chapter(s) -5 Page 3 of 5

4 UNIT-III [1] chapter(s) Multiprocessor System Interconnects 20 Cache Coherence and Synchronization Mechanisms [1] chapter(s) Message-Passing Mechanisms [1] chapter(s) Vector Processing Principles [1] chapter(s) -8 Multivector Multiprocessors Performance-Directed [1] chapter(s) Design Rules Fujitsu VP2000 and VPP500 SIMD Computer Organizations Implementation [1] chapter(s) models The MasPar MP-1 Architecture 25 Latency - Hiding Techniques [1] chapter(s) Principles of Multithreading [1] chapter(s) -9 Scalable and Multithreaded Architectures -.The Tera [1] chapter(s) Multiprocessor System UNIT-IV 28 Introduction to Pipelining [2]chapter(s) - A1 29 Basics of a RISC Instruction set [2]chapter(s) - A1 Implementation of five stage Pipeline for a RISC [2]chapter(s) - A1 30 processor 31 Performance issues [2]chapter(s) - A1 32 Hurdle of pipelining- Structural and Data hazards [2]chapter(s) A2 33 Branch Hazards [2]chapter(s) A2 34 Simple implementation of MIPS [2]chapter(s) A3 Extending the MIPS pipeline to handle multicycle [2]chapter(s) A5 35 operations 36 Cross cutting issues. [2]chapter(s) A8 UNIT-V 37 Parallel Programming Models [1] chapter(s) Parallel Languages And Compliers [1] chapter(s) Code Optimization And Scheduling [1] chapter(s) -10 Scalar Optimization With Basic Blocks Code [1] chapter(s) Generation And Scheduling, Trace Scheduling Compilation Page 4 of 5

5 Parallelization And Wave Fronting, Software [1] chapter(s) Pipelining Parallel Programming Environments Y-MP, Paragon [1] chapter(s) And CM-5 Environments Synchronization And Multiprocessing Modes [1] chapter(s) Principles Of Synchronization - Multiprocessor Execution Modes Shared-Variable Program Structures Locks For [1] chapter(s) Protected Access Semaphores And Applications 45 Message-Passing Program Development [1] chapter(s) -11 Evaluation methods Cycle Test I - 20% Model Test - 20% Surprise Test - 5% Term paper - 5% Final exam - 50% Prepared by: Mrs. K. Vadivukkarasi, Assistant Professor (O.G), Department of ECE Dated: 22 nd June 2015 Revision No.: 00 Date of revision: NA Course Coordinator (K. Vadivukkarasi) HOD/ECE (Dr.S.Malarvizhi) Page 5 of 5