Academic Course Description. VL2003 Digital Processing Structures for VLSI First Semester, (Odd semester)

Transcription

1 Academic Course Description SRM University Faculty of Engineering and Technology Department of Electronics and Communication Engineering VL2003 Digital Processing Structures for VLSI First Semester, (Odd semester) Course (catalog) description: DSPs are used in many application areas and hence has become an essential part of VLSIs. Hence to introduce the student about DSP structures, this subject is included. Compulsory/Elective course: Compulsory Course for M. Tech (VLSI Design) I year students Credit hours: 4 credits Course coordinator(s): K. Ferents Koni Jiavana, Assistant Professor (O.G), Department of ECE Instructor(s) Name of the instructor K. Ferents Koni Jiavana Class handling Office location Office phone Consultation VLSI -A TP10S ferentskoni.k@ktr.srmuniv.ac.in Day 5: 2-4 p.m Relationship to other courses Pre-requisites : Nil Assumed knowledge : Knowledge of basic Digital Signal Processing. Following courses : VL2108- DSP Architectures and Applications References 1. K.K Parhi, VLSI Digital Signal Processing Systems, John Wiley & Sons, NY, John G. Proakis, Dimitris G. Monalakis, Digital Signal Processing, Prentice Hall of India Pvt., Ltd., New Delhi, Class schedule: Four minutes Lecture sessions per week, for 15 weeks Section Schedule VLSI - A Day 1-6hr, Day 3 3 hr, Day 4-5hr, Day 5-1 hr Professional component General - 0% Basic Sciences - 0% Engineering sciences & Technical arts - 0% Professional subject - 100% Broad area: Communication Signal Processing Electronics VLSI Embedded Page 1 of 5

2 Test Schedule - Theory S. No. Test Portions Duration 1 Cycle Test Session 1 to 7 1 hr 40 min 2 Model Exam Weeks 8 to 15 3 hrs Course Objectives To understand the fundamentals of DSP To learn various DSP structures and their implementation. To know designing constraints of various filters. Weekly teaching plan Session No. Topics to be covered Page 2 of 5 Time Study Material (min) Reference, Text Book 1 Linear System Theory- Introduction Ref. [2], Chapter-1 Ref. [1], Chapter-1, 2 Convolution : Introduction, Linear Convolution with a problem Section 1.2, Ref. [2], Chapter-2. 3 Correlation : Introduction and mathematical expressions Section DFT Time Domain & Frequency Domain Analysis with a Ref. [2], Chapter-3, Problem Session FFT Problems to analyze the frequency spectrum using DIT and Ref. [2], Chapter-4 DIF algorithm in detail. Session Basic concepts in FIR Filters: basic mathematical expressions & theory of operation. session Basic concepts in IIR Filters: basic mathematical expressions & 7 theory of operation. session Filter Realizations : Basic FIR filter Realization Technique: DF- Ref. [2], Chapter-5, I and DF-II session Filter Realizations: Basic FIR filter Realization Technique: Ref. [2], Chapter 5, Series and parallel configuration. session Representation of DSP Algorithms Block Diagram session Representation of DSP Algorithms - SFG session Representation of DSP Algorithms - DFG session Data-Flow Graph Representations session Loop Bound and Iteration Bound session 2.3

3 15 Algorithms for Computing Iteration Bound : Introduction session Longest Path Matrix Algorithm for iteration bound Computation with a problem set. session Pipelining and Parallel Processing An Introduction session 3.1, Pipelining of FIR Digital Filters Data Broadcast structure, Fine-grain pipelining. session Parallel Processing - design of parallel FIR Filter session Pipelining for Low Power session Parallel Processing for Low Power session Combining Pipelining & Parallel Processing - Introduction Ref. [1], Chapter-3 session Retiming: Definitions- Properties and problems Ref. [1], Chapter-4, session 4.1, Solving Systems of Inequalities Retiming techniques cutest retiming Ref. [1], Chapter-4, and pipelining session 4.3, Introduction of Fast Convolution techniques for VLSI DSP Implementation session Cook-Toom Algorithm- mathematical derivation for 2x2, 2x3 linear convolution session Modified Cook-Toom Algorithm ; Derivation for 2x2, 2x3 linear convolution session Comparison between cook-toom and modified cook-toom algorithm. Design of Fast Convolution Algorithm by Inspection session 8.2.3, Parallel FIR filters formation using polyphase decomposition session Fast FIR algorithms Two, Three parallel structures- Introduction Ref. [1], Chap. -9 session Two Parallel and three Parallel mathematical derivation session Parallel architectures for Rank Order filters session Odd Even Merge sort architecture session Rank Order filter architecture session Parallel Rank Order filters session Running Order Merge Order Sorter session Low power Rank Order filter session Pipeline Interleaving in Digital Filters- Introduction. session Pipeline Interleaving in Digital Filters Inefficient Single/multi- Channel interleaving session Page 3 of 5

4 Pipeline Interleaving in Digital Filters Efficient single channel interleaving session Pipeline Interleaving in Digital Filters Efficient multi channel interleaving session Pipelining in 1st Order IIR Digital Filters : Introduction session 10.3 Pipelining in 1st Order IIR Digital Filters ; Look-Ahead pipelining technique session Pipelining in 1st Order IIR Digital Filters ; Power-of-2 Decomposition session Pipelining in Higher IIR Digital Filters - Introduction session Pipelining in Higher IIR Digital Filters session 10.4 Introduction to Clustered Look Ahead Filter Design session Introduction to Stable Clustered Look Ahead Filter Design session 10.4 Parallel Processing in IIR Digital Filters session 10.5 Introduction to Scaling Noise : Introduction, mathematical derivation session Introduction to Round off Noise : Introduction. session State Variable Description of Digital Filters. session 11.3 Scaling Computation Mathematical derivation & problem solution. session Round off Noise Computation Mathematical derivation &problem Solution. session Round off Noise Computation in pipelined IIR Filters First Order. session Round off Noise Computation in pipelined IIR Filters Second order filter. session Round off noise computation using State Variable Description 1 st order filter. session 11.6 Round off noise computation using State Variable Description 2 nd order filter. session 11.6 Slow down transformation technique. Retiming mechanism in higher-order IIR filter design. Pipelining in higher-order IIR filter design. Page 4 of 5

5 Evaluation methods Cycle Test - 20% Model Test - 20% Term Paper/surprise test - 10% Final exam - % Prepared by: K. Ferents Koni Jiavana, Assistant Professor(O.G), Department of ECE Dated: 29 th July 2015 Revision No.: 00 Date of revision: NA Page 5 of 5