2 Mbit / 4 Mbit / 8 Mbit (x16) Multi-Purpose Flash SST39LF200A / SST39LF400A / SST39LF800A SST39VF200A / SST39VF400A / SST39VF800A

Transcription

1 Mbit / Mbit / 8 Mbit (x) Multi-Purpose Flash FEATURES: SST9LF/VF00A / 00A / 800A.0 &.7V Mb / Mb / 8Mb (x) MPF memories Organized as 8K x / K x / K x Single Voltage Read and Write Operations.0-.V for SST9LF00A/00A/800A.7-.V for SST9VF00A/00A/800A Superior Reliability Endurance: 00,000 Cycles (typical) Greater than 00 years Data Retention Low Power Consumption (typical values at MHz) Active Current: 9 ma (typical) Standby Current: µa (typical) Sector-Erase Capability Uniform KWord sectors Block-Erase Capability Uniform KWord blocks Fast Read Access Time and ns for SST9LF00A ns for SST9LF00A/800A 70 ns for SST9VF00A/00A/800A Latched Address and Data Fast Erase and Word-Program Sector-Erase Time: 8 ms (typical) Block-Erase Time: 8 ms (typical) Chip-Erase Time: 70 ms (typical) Word-Program Time: µs (typical) Chip Rewrite Time: seconds (typical) for SST9LF/VF00A seconds (typical) for SST9LF/VF00A 8 seconds (typical) for SST9LF/VF800A Automatic Write Timing Internal V PP Generation End-of-Write Detection Toggle Bit Data# Polling CMOS I/O Compatibility JEDEC Standard Flash EEPROM Pinouts and command sets Packages Available 8-lead TSOP (mm x 0mm) 8-ball TFBGA (mm x 8mm) 8-ball WFBGA (mm x mm) 8-bump XFLGA (mm x mm) and 8Mbit All non-pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST9LF00A/00A/800A and SST9VF00A/00A/ 800A devices are 8K x / K x / K x CMOS Multi-Purpose Flash (MPF) manufactured with SST proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST9LF00A/00A/800A write (Program or Erase) with a.0-.v power supply. The SST9VF00A/00A/800A write (Program or Erase) with a.7-.v power supply. These devices conform to JEDEC standard pinouts for x memories. Featuring high-performance Word-Program, the SST9LF00A/00A/800A and SST9VF00A/00A/ 800A devices provide a typical Word-Program time of µsec. The devices use Toggle Bit or Data# Polling to detect the completion of the Program or Erase operation. To protect against inadvertent write, they have on-chip hardware and software data protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 00,000 cycles. Data retention is rated at greater than 00 years. The SST9LF00A/00A/800A and SST9VF00A/00A/ 800A devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. When programming a flash device, the total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. 007 Silicon Storage Technology, Inc. S /07 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice.

2 To meet surface mount requirements, the SST9LF00A/ 00A/800A and SST9VF00A/00A/800A are offered in 8-lead TSOP packages and 8-ball TFBGA packages as well as Micro-Packages. See Figures,, and for pin assignments. Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting low while keeping CE# low. The address bus is latched on the falling edge of or CE#, whichever occurs last. The data bus is latched on the rising edge of or CE#, whichever occurs first. Read The Read operation of the SST9LF00A/00A/800A and SST9VF00A/00A/800A is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure ). Word-Program Operation The SST9LF00A/00A/800A and SST9VF00A/00A/ 800A are programmed on a word-by-word basis. Before programming, the sector where the word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or, whichever occurs last. The data is latched on the rising edge of either CE# or, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 0 µs. See Figures and 7 for and CE# controlled Program operation timing diagrams and Figure 8 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. Mbit / Mbit / 8 Mbit Multi-Purpose Flash Sector/Block-Erase Operation The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-byblock) basis. The SST9LF00A/00A/800A and SST9VF00A/00A/800A offers both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of KWord. The Block-Erase mode is based on uniform block size of KWord. The Sector- Erase operation is initiated by executing a six-byte command sequence with Sector-Erase command (0H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (0H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth pulse, while the command (0H or 0H) is latched on the rising edge of the sixth pulse. The internal Erase operation begins after the sixth pulse. The End-of- Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures and for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored. Chip-Erase Operation The SST9LF00A/00A/800A and SST9VF00A/00A/ 800A provide a Chip-Erase operation, which allows the user to erase the entire memory array to the state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (0H) at address H in the last byte sequence. The Erase operation begins with the rising edge of the sixth or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table for the command sequence, Figure 0 for timing diagram, and Figure for the flowchart. Any commands issued during the Chip-Erase operation are ignored. Write Operation Status Detection The SST9LF00A/00A/800A and SST9VF00A/00A/ 800A provide two software means to detect the completion of a write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ 7 ) and Toggle Bit (DQ ). The End-of-Write detection mode is enabled after the rising edge of, which initiates the internal Program or Erase operation.

3 The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ 7 or DQ. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two () times. If both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. Data# Polling (DQ 7 ) When the SST9LF00A/00A/800A and SST9VF00A/ 00A/800A are in the internal Program operation, any attempt to read DQ 7 will produce the complement of the true data. Once the Program operation is completed, DQ 7 will produce true data. Note that even though DQ 7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of µs. During internal Erase operation, any attempt to read DQ 7 will produce a 0. Once the internal Erase operation is completed, DQ 7 will produce a. The Data# Polling is valid after the rising edge of fourth (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth (or CE#) pulse. See Figure 8 for Data# Polling timing diagram and Figure 9 for a flowchart. Toggle Bit (DQ ) During the internal Program or Erase operation, any consecutive attempts to read DQ will produce alternating s and 0s, i.e., toggling between and 0. When the internal Program or Erase operation is completed, the DQ bit will stop toggling. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth (or CE#) pulse. See Figure 9 for Toggle Bit timing diagram and Figure 9 for a flowchart. Data Protection The SST9LF00A/00A/800A and SST9VF00A/00A/ 800A provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A or CE# pulse of less than ns will not initiate a write cycle. V DD Power Up/Down Detection: The Write operation is inhibited when V DD is less than.v. Write Inhibit Mode: Forcing OE# low, CE# high, or high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Software Data Protection (SDP) The SST9LF00A/00A/800A and SST9VF00A/00A/ 800A provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. This group of devices are shipped with the Software Data Protection permanently enabled. See Table for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ -DQ 8 can be V IL or V IH, but no other value, during any SDP command sequence. Common Flash Memory Interface (CFI) The SST9LF00A/00A/800A and SST9VF00A/00A/ 800A also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write three-byte sequence, same as Software ID Entry command with 98H (CFI Query command) to address H in the last byte sequence. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables through 9. The system must write the CFI Exit command to return to Read mode from the CFI Query mode.

4 Product Identification The Product Identification mode identifies the devices as the SST9LF/VF00A, SST9LF/VF00A and SST9LF/ VF800A and manufacturer as SST. This mode may be accessed by software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table for software operation, Figure for the Software ID Entry and Read timing diagram, and Figure 0 for the Software ID Entry command sequence flowchart. TABLE : Product Identification Address Data Manufacturer s ID 0000H 00BFH Device ID SST9LF/VF00A 000H 789H SST9LF/VF00A 000H 780H SST9LF/VF800A 000H 78H T. 7 Product Identification Mode Exit/ CFI Mode Exit In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/ CFI Exit command is ignored during an internal Program or Erase operation. See Table for software command codes, Figure for timing waveform, and Figure 0 for a flowchart. X-Decoder SuperFlash Memory Memory Address Address Buffer & Latches Y-Decoder CE# OE# Control Logic I/O Buffers and Data Latches DQ - DQ 0 7 B. FIGURE : Functional Block Diagram

5 SST9LF/VF800A SST9LF/VF00A SST9LF/VF00A SST9LF/VF00A SST9LF/VF00A SST9LF/VF800A A A A A A A0 A9 A8 A8 A7 A7 A A A A A A A A A A A A0 A9 A8 A7 A7 A A A A A A A A A A A A0 A9 A8 A7 A A A A A A Standard Pinout Top View Die Up A V SS DQ DQ7 DQ DQ DQ DQ DQ DQ V DD DQ DQ DQ0 DQ DQ9 DQ DQ8 DQ0 OE# V SS CE# A0 A V SS DQ DQ7 DQ DQ DQ DQ DQ DQ V DD DQ DQ DQ0 DQ DQ9 DQ DQ8 DQ0 OE# V SS CE# A0 A V SS DQ DQ7 DQ DQ DQ DQ DQ DQ V DD DQ DQ DQ0 DQ DQ9 DQ DQ8 DQ0 OE# V SS CE# A0 7 8-tsop P0. FIGURE : Pin Assignments for 8-Lead TSOP TOP VIEW (balls facing down) SST9LF/VF00A A A9 A7 A A A8 A A A0 A A A A A A A DQ VSS DQ7 DQ DQ DQ DQ DQ VDD DQ DQ DQ0 DQ DQ DQ0 DQ8 DQ9 DQ A0 CE# OE# VSS A B C D E F G H 7 8-tfbga P0_.0 TOP VIEW (balls facing down) SST9LF/VF00A TOP VIEW (balls facing down) SST9LF/VF800A A A9 A7 A A A8 A7 A A A0 A A A A A A A DQ VSS DQ7 DQ DQ DQ DQ DQ VDD DQ DQ DQ0 DQ DQ DQ0 DQ8 DQ9 DQ A0 CE# OE# VSS A B C D E F G H 7 8-tfbga P0_.0 A A9 A7 A A A8 A7 A A A0 A8 A A A A A A A DQ VSS DQ7 DQ DQ DQ DQ DQ VDD DQ DQ DQ0 DQ DQ DQ0 DQ8 DQ9 DQ A0 CE# OE# VSS A B C D E F G H 7 8-tfbga P0_8.0 FIGURE : Pin Assignments for 8-Ball TFBGA

6 Mbit / Mbit / 8 Mbit Multi-Purpose Flash A A A0 A A A A A7 CE# DQ8 DQ0 V SS OE# DQ0 DQ9 DQ DQ TOP VIEW (balls facing down) SST9VF00A DQ A9 A A0 A8 DQ DQ A A DQ DQ A A A DQ7 V DD DQ DQ DQ DQ V SS A B C D E F G H J K L 7 8-xflga P0_.0 A A A0 A A A A A7 A7 CE# DQ8 DQ0 V SS OE# DQ0 DQ9 DQ DQ TOP VIEW (balls facing down) SST9LF/VF00A DQ A9 A A0 A8 DQ DQ A A DQ DQ A A A DQ7 V DD DQ DQ DQ DQ V SS A B C D E F G H J K L 7 8-xflga P0_.0 A A A0 A A A A A7 A8 A7 CE# DQ8 DQ0 V SS OE# DQ0 DQ9 DQ DQ TOP VIEW (balls facing down) SST9LF/VF800A DQ A9 A A0 A8 DQ DQ A A DQ DQ A A A DQ7 V DD DQ DQ DQ DQ V SS A B C D E F G H J K L 7 8-xflga P0_8.0 FIGURE : Pin Assignments for 8-Ball WFBGA and 8-Bump XFLGA

7 TABLE : Pin Description Symbol Pin Name Functions A MS -A 0 Address Inputs To provide memory addresses. During Sector-Erase A MS -A address lines will select the sector. During Block-Erase A MS -A address lines will select the block. DQ -DQ 0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. Write Enable To control the Write operations. V DD Power Supply To provide power supply voltage:.0-.v for SST9LF00A/00A/800A.7-.V for SST9VF00A/00A/800A V SS Ground No Connection Unconnected pins.. A MS = Most significant address A MS = A for SST9LF/VF00A, A 7 for SST9LF/VF00A, and A 8 for SST9LF/VF800A T. 7 TABLE : Operation Modes Selection Mode CE# OE# DQ Address Read V IL V IL V IH D OUT A IN Program V IL V IH V IL D IN A IN Erase V IL V IH V IL X Sector or Block address, XXH for Chip-Erase Standby V IH X X High Z X Write Inhibit X V IL X High Z/ D OUT X X X V IH High Z/ D OUT X Product Identification Software Mode V IL V IL V IH See Table. X can be V IL or V IH, but no other value. T. 7 7

8 TABLE Command Sequence : Software Command Sequence st Bus Write Cycle nd Bus Write Cycle Mbit / Mbit / 8 Mbit Multi-Purpose Flash rd Bus Write Cycle th Bus Write Cycle th Bus Write Cycle th Bus Write Cycle Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Word-Program H AAH AAAH H H A0H WA Data Sector-Erase H AAH AAAH H H 80H H AAH AAAH H SA X 0H Block-Erase H AAH AAAH H H 80H H AAH AAAH H BA X 0H Chip-Erase H AAH AAAH H H 80H H AAH AAAH H H 0H Software ID Entry, H AAH AAAH H H 90H CFI Query Entry H AAH AAAH H H 98H Software ID Exit 7 / XXH F0H CFI Exit Software ID Exit 7 / CFI Exit H AAH AAAH H H F0H. Address format A -A 0 (Hex), Addresses A MS- A can be V IL or V IH, but no other value, for the Command sequence. A MS = Most significant address A MS = A for SST9LF/VF00A, A 7 for SST9LF/VF00A, and A 8 for SST9LF/VF800A. DQ -DQ 8 can be V IL or V IH, but no other value, for the Command sequence. WA = Program word address. SA X for Sector-Erase; uses A MS -A address lines BA X for Block-Erase; uses A MS -A address lines. The device does not remain in Software Product ID mode if powered down.. With A MS -A = 0; SST Manufacturer s ID = 00BFH, is read with A 0 = 0, SST9LF/VF00A Device ID = 789H, is read with A 0 =. SST9LF/VF00A Device ID = 780H, is read with A 0 =. SST9LF/VF800A Device ID = 78H, is read with A 0 =. 7. Both Software ID Exit operations are equivalent T. 7 TABLE : CFI Query Identification String for SST9LF00A/00A/800A and SST9VF00A/00A/800A Address Data Data 0H 00H Query Unique ASCII string QRY H 00H H 009H H 000H Primary OEM command set H 0007H H 0000H Address for Primary Extended Table H 0000H 7H 0000H Alternate OEM command set (00H = none exists) 8H 0000H 9H 0000H Address for Alternate OEM extended Table (00H = none exits) AH 0000H. Refer to CFI publication 00 for more details. T.0 7 8

9 TABLE : System Interface Information for SST9LF00A/00A/800A and SST9VF00A/00A/800A Address Data Data BH 007H V DD Min (Program/Erase) 000H DQ 7 -DQ : Volts, DQ -DQ 0 : 00 millivolts CH 00H V DD Max (Program/Erase) DQ 7 -DQ : Volts, DQ -DQ 0 : 00 millivolts DH 0000H V PP min (00H = no V PP pin) EH 0000H V PP max (00H = no V PP pin) FH 000H Typical time out for Word-Program N µs ( = µs) 0H 0000H Typical time out for min size buffer program N µs (00H = not supported) H 000H Typical time out for individual Sector/Block-Erase N ms ( = ms) H 000H Typical time out for Chip-Erase N ms ( = ms) H 000H Maximum time out for Word-Program N times typical ( x = µs) H 0000H Maximum time out for buffer program N times typical H 000H Maximum time out for individual Sector/Block-Erase N times typical ( x = ms) H 000H Maximum time out for Chip-Erase N times typical ( x = 8 ms). 000H for SST9LF00A/00A/800A and 007H for SST9VF00A/00A/800A T. 7 TABLE 7: Device Geometry Information for SST9LF/VF00A Address Data Data 7H 00H Device size = N Byte (H = 8; 8 = KByte) 8H 000H Flash Device Interface description; 000H = x-only asynchronous interface 9H 0000H AH 0000H Maximum number of bytes in multi-byte write = N (00H = not supported) BH CH 000H Number of Erase Sector/Block sizes supported by device DH 00FH Sector Information (y + = Number of sectors; z x B = sector size) EH 0000H y = + = sectors (00FH = ) FH 000H 0H 0000H z = x Bytes = KByte/sector (000H = ) H 000H Block Information (y + = Number of blocks; z x B = block size) H 0000H y = + = blocks (000H = ) H 0000H H 000H z = x Bytes = KByte/block (000H = ) T7. 7 9

10 TABLE 8: Device Geometry Information for SST9LF/VF00A Mbit / Mbit / 8 Mbit Multi-Purpose Flash Address Data Data 7H 00H Device size = N Byte (H = 9; 9 = KByte) 8H 000H Flash Device Interface description; 000H = x-only asynchronous interface 9H 0000H AH 0000H Maximum number of bytes in multi-byte write = N (00H = not supported) BH 0000H CH 000H Number of Erase Sector/Block sizes supported by device DH 007FH Sector Information (y + = Number of sectors; z x B = sector size) EH 0000H y = 7 + = 8 sectors (007FH = 7) FH 000H 0H 0000H z = x Bytes = KByte/sector (000H = ) H 0007H Block Information (y + = Number of blocks; z x B = block size) H 0000H y = 7 + = 8 blocks (0007H = 7) H 0000H H 000H z = x Bytes = KByte/block (000H = ) T8. 7 TABLE 9: Device Geometry Information for SST9LF/VF800A Address Data Data 7H 00H Device size = N Bytes (H = 0; 0 = MByte) 8H 000H Flash Device Interface description; 000H = x-only asynchronous interface 9H 0000H AH 0000H Maximum number of bytes in multi-byte write = N (00H = not supported) BH 0000H CH 000H Number of Erase Sector/Block sizes supported by device DH 00FFH Sector Information (y + = Number of sectors; z x B = sector size) EH 0000H y = + = sectors (00FFH = ) FH 000H 0H 0000H z = x Bytes = KByte/sector (000H = ) H 000FH Block Information (y + = Number of blocks; z x B = block size) H 0000H y = + = blocks (000FH = ) H 0000H H 000H z = x Bytes = KByte/block (000H = ) T

11 Absolute Maximum Stress Ratings (Applied conditions greater than those listed under Absolute Maximum Stress Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias C to + C Storage Temperature C to +0 C D. C. Voltage on Any Pin to Ground Potential V to V DD +0.V Transient Voltage (<0 ns) on Any Pin to Ground Potential V to V DD +.0V Voltage on A 9 Pin to Ground Potential V to.v Package Power Dissipation Capability (T A = C) W Surface Mount Solder Reflow Temperature C for 0 seconds Output Short Circuit Current ma. Excluding certain with-pb -PLCC units, all packages are 0 C capable in both non-pb and with-pb solder versions. Certain with-pb -PLCC package types are capable of 0 C for 0 seconds; please consult the factory for the latest information.. Outputs shorted for no more than one second. No more than one output shorted at a time. Operating Range: SST9LF00A/00A/800A Range Ambient Temp V DD Commercial 0 C to +70 C.0-.V Operating Range: SST9VF00A/00A/800A Range Ambient Temp V DD Commercial 0 C to +70 C.7-.V Industrial -0 C to +8 C.7-.V AC Conditions of Test Input Rise/Fall Time ns Output Load C L = 0 pf for SST9LF00A/00A/800A Output Load C L = 00 pf for SST9VF00A/00A/800A See Figures and 7

12 Mbit / Mbit / 8 Mbit Multi-Purpose Flash TABLE 0: DC Operating Characteristics V DD =.0-.V for SST9LF00A/00A/800A and.7-.v for SST9VF00A/00A/800A Limits Symbol Parameter Min Max Units Test Conditions I DD Power Supply Current Address input=v ILT /V IHT, at f=/t RC Min, V DD =V DD Max Read 0 ma CE#=V IL, OE#==V IH, all I/Os open Program and Erase 0 ma CE#==V IL, OE#=V IH I SB Standby V DD Current 0 µa CE#=V IHC, V DD =V DD Max I LI Input Leakage Current µa V IN =GND to V DD, V DD =V DD Max I LO Output Leakage Current 0 µa V OUT =GND to V DD, V DD =V DD Max V IL Input Low Voltage 0.8 V DD =V DD Min V IH Input High Voltage 0.7V DD V V DD =V DD Max V IHC Input High Voltage (CMOS) V DD -0. V V DD =V DD Max V OL Output Low Voltage 0. V I OL =00 µa, V DD =V DD Min V OH Output High Voltage V DD -0. V I OH =-00 µa, V DD =V DD Min. Typical conditions for the Active Current shown on page are average values at C (room temperature), and V DD = V for VF devices. Not 00% tested.. Values are for 70 ns conditions. See the Multi-Purpose Flash Power Rating application note for further information. T0.7 7 TABLE : Recommended System Power-up Timings Symbol Parameter Minimum Units T PU-READ Power-up to Read Operation 00 µs T PU-WRITE Power-up to Program/Erase Operation 00 µs T.0 7. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE : Capacitance (T A = C, f= Mhz, other pins open) Parameter Description Test Condition Maximum C I/O I/O Pin Capacitance V I/O = 0V pf C IN Input Capacitance V IN = 0V pf T.0 7. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE : Reliability Characteristics Symbol Parameter Minimum Specification Units Test Method N, END Endurance 0,000 Cycles JEDEC Standard A7 T DR Data Retention 00 Years JEDEC Standard A0 I LTH Latch Up 00 + I DD ma JEDEC Standard 78 T. 7. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.. N END endurance rating is qualified as a 0,000 cycle minimum for the whole device. A sector- or block-level rating would result in a higher minimum specification.

13 AC CHARACTERISTICS TABLE : Read Cycle Timing Parameters V DD =.0-.V SST9LF00A- SST9LF00A/00A/800A- Symbol Parameter Min Max Min Max Units T RC Read Cycle Time ns T CE Chip Enable Access Time ns T AA Address Access Time ns T OE Output Enable Access Time 0 0 ns T CLZ CE# Low to Active Output 0 0 ns T OLZ OE# Low to Active Output 0 0 ns T CHZ CE# High to High-Z Output ns T OHZ OE# High to High-Z Output ns T OH Output Hold from Address Change 0 0 ns T.7 7. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE : Read Cycle Timing Parameters V DD =.7-.V SST9VF00A/00A/800A-70 Symbol Parameter Min Max Units T RC Read Cycle Time 70 ns T CE Chip Enable Access Time 70 ns T AA Address Access Time 70 ns T OE Output Enable Access Time ns T CLZ CE# Low to Active Output 0 ns T OLZ OE# Low to Active Output 0 ns T CHZ CE# High to High-Z Output 0 ns T OHZ OE# High to High-Z Output 0 ns T OH Output Hold from Address Change 0 ns T.7 7. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

14 TABLE : Program/Erase Cycle Timing Parameters Symbol Parameter Min Max Units T BP Word-Program Time 0 µs T AS Address Setup Time 0 ns T AH Address Hold Time 0 ns T CS and CE# Setup Time 0 ns T CH and CE# Hold Time 0 ns T OES OE# High Setup Time 0 ns T OEH OE# High Hold Time 0 ns T CP CE# Pulse Width 0 ns T WP Pulse Width 0 ns T WPH Pulse Width High 0 ns T CPH CE# Pulse Width High 0 ns T DS Data Setup Time 0 ns T DH Data Hold Time 0 ns T IDA Software ID Access and Exit Time 0 ns T SE Sector-Erase ms T BE Block-Erase ms T SCE Chip-Erase 00 ms T.0 7. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.

15 T RC T AA ADDRESS A MS-0 T CE CE# T OE OE# VIH T OLZ T OHZ T CLZ T OH T CHZ DQ -0 HIGH-Z DATA VALID DATA VALID HIGH-Z Note: AMS = Most significant address AMS = A for SST9LF/VF00A, A7 for SST9LF/VF00A and A8 for SST9LF/VF800A 7 F0. FIGURE : Read Cycle Timing Diagram INTERNAL PROGRAM OPERATION STARTS T BP ADDRESS A MS-0 AAA ADDR T AH T WP T DH T AS T WPH T DS OE# T CH CE# T CS DQ -0 Note: XXAA XX XXA0 DATA SW0 SW SW WORD (ADDR/DATA) AMS = Most significant address AMS = A for SST9LF/VF00A, A7 for SST9LF/VF00A and A8 for SST9LF/VF800A X can be VIL or VIH, but no other value. 7 F0. FIGURE : Controlled Program Cycle Timing Diagram

16 INTERNAL PROGRAM OPERATION STARTS T BP ADDRESS A MS-0 AAA ADDR T AH T CP T DH CE# T AS T CPH T DS OE# T CH T CS DQ -0 XXAA XX XXA0 DATA SW0 SW SW WORD (ADDR/DATA) Note: A MS = Most significant address A MS = A for SST9LF/VF00A, A 7 for SST9LF/VF00A and A 8 for SST9LF/VF800A X can be V IL or V IH, but no other value. 7 F0. FIGURE 7: CE# Controlled Program Cycle Timing Diagram ADDRESS A MS-0 T CE CE# T OEH T OES OE# T OE DQ 7 DATA DATA# DATA# DATA Note: A MS = Most significant address A MS = A for SST9LF/VF00A, A 7 for SST9LF/VF00A and A 8 for SST9LF/VF800A 7 F0. FIGURE 8: Data# Polling Timing Diagram

17 ADDRESS A MS-0 T CE CE# T OEH T OE T OES OE# DQ Note: TWO READ CYCLES WITH SAME OUTPUTS A MS = Most significant address A MS = A for SST9LF/VF00A, A 7 for SST9LF/VF00A and A 8 for SST9LF/VF800A 7 F07. FIGURE 9: Toggle Bit Timing Diagram SIX-BYTE CODE FOR CHIP-ERASE T SCE ADDRESS A MS-0 AAA AAA CE# OE# T WP DQ -0 XXAA XX XX80 XXAA XX XX0 SW0 SW SW SW SW SW Note: This device also supports CE# controlled Chip-Erase operation. The and CE# signals are interchageable as long as minimum timings are met. (See Table ) A MS = Most significant address A MS = A for SST9LF/VF00A, A 7 for SST9LF/VF00A and A 8 for SST9LF/VF800A X can be V IL or V IH, but no other value. 7 F08.7 FIGURE 0: Controlled Chip-Erase Timing Diagram 7

18 SIX-BYTE CODE FOR BLOCK-ERASE T BE ADDRESS A MS-0 AAA AAA BA X CE# OE# T WP DQ -0 XXAA XX XX80 XXAA XX XX0 SW0 SW SW SW SW SW Note: This device also supports CE# controlled Block-Erase operation. The and CE# signals are interchageable as long as minimum timings are met. (See Table ) BA X = Block Address A MS = Most significant address A MS = A for SST9LF/VF00A, A 7 for SST9LF/VF00A and A 8 for SST9LF/VF800A X can be V IL or V IH, but no other value. FIGURE : Controlled Block-Erase Timing Diagram 7 F7.9 SIX-BYTE CODE FOR SECTOR-ERASE T SE ADDRESS A MS-0 AAA AAA SA X CE# OE# T WP DQ -0 XXAA XX XX80 XXAA XX XX0 SW0 SW SW SW SW SW Note: This device also supports CE# controlled Sector-Erase operation. The and CE# signals are interchageable as long as minimum timings are met. (See Table ) SA X = Sector Address A MS = Most significant address A MS = A for SST9LF/VF00A, A 7 for SST9LF/VF00A and A 8 for SST9LF/VF800A X can be V IL or V IH, but no other value. 7 F8.8 FIGURE : Controlled Sector-Erase Timing Diagram 8

19 THREE-BYTE SEQUEE FOR SOFTWARE ID ENTRY ADDRESS A -0 AAA CE# OE# T WP T IDA T WPH TAA DQ -0 XXAA XX XX90 00BF Device ID SW0 SW SW Device ID = 789H for SST9LF/VF00A, 780H for SST9LF/VF00A and 78H for SST9LF/VF800A Note: X can be V IL or V IH, but no other value. 7 F09. FIGURE : Software ID Entry and Read THREE-BYTE SEQUEE FOR CFI QUERY ENTRY ADDRESS A -0 AAA CE# OE# T WP T IDA T WPH T AA DQ -0 XXAA XX XX98 SW0 SW SW Note: X can be V IL or V IH, but no other value. 7 F0. FIGURE : CFI Query Entry and Read 9

20 Mbit / Mbit / 8 Mbit Multi-Purpose Flash THREE-BYTE SEQUEE FOR SOFTWARE ID EXIT AND RESET ADDRESS A -0 AAA DQ -0 XXAA XX XXF0 T IDA CE# OE# T WP T WHP SW0 SW SW Note: X can be V IL or V IH, but no other value. 7 F0. FIGURE : Software ID Exit/CFI Exit 0

21 V IHT INPUT V IT REFEREE POINTS V OT OUTPUT V ILT 7 F. AC test inputs are driven at V IHT (0.9 V DD ) for a logic and V ILT (0. V DD ) for a logic 0. Measurement reference points for inputs and outputs are V IT (0. V DD ) and V OT (0. V DD ). Input rise and fall times (0% 90%) are < ns. FIGURE : AC Input/Output Reference Waveforms Note: V IT - V INPUT Test V OT - V OUTPUT Test V IHT - V INPUT HIGH Test V ILT - V INPUT LOW Test TO TESTER TO DUT C L FIGURE 7: A Test Load Example 7 F.

22 Mbit / Mbit / 8 Mbit Multi-Purpose Flash Start Load data: XXAAH Load data: XXH Address: AAAH Load data: XXA0H Load Word Address/Word Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed Note: X can be V IL or V IH, but no other value. 7 F. FIGURE 8: Word-Program Algorithm

23 Internal Timer Toggle Bit Data# Polling Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated Wait TBP, TSCE, TSE or TBE Read word Read DQ7 Program/Erase Completed Read same word No Is DQ7 = true data? Yes No Does DQ match? Yes Program/Erase Completed Program/Erase Completed 7 F.0 FIGURE 9: Wait Options

24 Mbit / Mbit / 8 Mbit Multi-Purpose Flash CFI Query Entry Command Sequence Software ID Entry Command Sequence Software ID Exit/CFI Exit Command Sequence Load data: XXAAH Load data: XXAAH Load data: XXAAH Load data: XXF0H Address: XXH Load data: XXH Address: AAAH Load data: XXH Address: AAAH Load data: XXH Address: AAAH Wait TIDA Load data: XX98H Load data: XX90H Load data: XXF0H Return to normal operation Wait TIDA Wait TIDA Wait TIDA Read CFI data Read Software ID Return to normal operation 7 F. Note: X can be V IL or V IH, but no other value. FIGURE 0: Software ID/CFI Command Flowcharts

25 Chip-Erase Command Sequence Sector-Erase Command Sequence Block-Erase Command Sequence Load data: XXAAH Load data: XXAAH Load data: XXAAH Load data: XXH Address: AAAH Load data: XXH Address: AAAH Load data: XXH Address: AAAH Load data: XX80H Load data: XX80H Load data: XX80H Load data: XXAAH Load data: XXAAH Load data: XXAAH Load data: XXH Address: AAAH Load data: XXH Address: AAAH Load data: XXH Address: AAAH Load data: XX0H Load data: XX0H Address: SAX Load data: XX0H Address: BAX Wait TSCE Wait TSE Wait TBE Chip erased to FFFFH Sector erased to FFFFH Block erased to FFFFH Note: X can be V IL or V IH, but no other value. 7 F. FIGURE : Erase Command Sequence

26 PRODUCT ORDERING INFORMATION SST 9 VF 00A C - BK E XX XX XXXX - XXX - XX - XXX X Environmental Attribute E = non-pb Package Modifier K = 8 leads or balls Q = 8 balls or bumps ( possible positions) Package Type B = TFBGA (0.8mm pitch, mm x 8mm) C = XFLGA (0.mm pitch, mm x mm) E = TSOP (type, die up, mm x 0mm) M = WFBGA (0.mm pitch, mm x mm) Y = WFBGA (panel-based, 0.mm pitch, mm x mm) Temperature Range C = Commercial = 0 C to +70 C I = Industrial = -0 C to +8 C Minimum Endurance = 0,000 cycles Read Access Speed = ns = ns 70 = 70 ns Version A = Special Feature Version Device Density 800 = 8 Mbit 00 = Mbit 00 = Mbit Voltage L =.0-.V V =.7-.V Product Series 9 = Multi-Purpose Flash. Environmental suffix E denotes non-pb solder. SST non-pb solder devices are RoHS Compliant.

27 Valid combinations for SST9LF00A SST9LF00A--C-EKE SST9LF00A--C-BKE SST9LF00A--C-EKE SST9LF00A--C-BKE Valid combinations for SST9VF00A SST9VF00A-70-C-EKE SST9VF00A-70-C-BKE SST9VF00A-70-C-MQE SST9VF00A-70-C-YQE SST9VF00A-70-I-EKE SST9VF00A-70-I-BKE SST9VF00A-70-I-MQE SST9VF00A-70-I-YQE Valid combinations for SST9LF00A SST9LF00A--C-EKE SST9LF00A--C-BKE Valid combinations for SST9VF00A SST9VF00A-70-C-EKE SST9VF00A-70-C-BKE SST9VF00A-70-C-CQE SST9VF00A-70-C-MQE SST9VF00A-70-I-EKE SST9VF00A-70-I-BKE SST9VF00A-70-I-CQE SST9VF00A-70-I-MQE Valid combinations for SST9LF800A SST9LF800A--C-EKE SST9LF800A--C-BKE Valid combinations for SST9VF800A SST9VF800A-70-C-EKE SST9VF800A-70-C-BKE SST9VF800A-70-C-CQE SST9VF800A-70-C-MQE SST9VF800A-70-C-YQE SST9VF800A-70-I-EKE SST9VF800A-70-I-BKE SST9VF800A-70-I-CQE SST9VF800A-70-I-MQE SST9VF800A-70-I-YQE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. 7

28 PACKAGING DIAGRAMS Mbit / Mbit / 8 Mbit Multi-Purpose Flash Pin # Identifier 0.0 BSC max. Note:. Complies with JEDEC publication 9 MO- DD dimensions, although some dimensions may be more stringent.. All linear dimensions are in millimeters (max/min).. Coplanarity: 0. mm. Maximum allowable mold flash is 0. mm at the package ends, and 0. mm between leads. FIGURE : 8-Lead Thin Small Outline Package (TSOP) mm x 0mm SST Package Code: EK DETAIL mm tsop-EK-8 0-8

29 TOP VIEW BOTTOM VIEW 8.00 ± ± 0.0 (8X).00 ± A B C D E F G H H G F E D C B A A CORNER SIDE VIEW.0 ± 0.0 A CORNER SEATING PLANE 0. ± mm Note:. Complies with JEDEC Publication 9, MO-0, variant 'AB-', although some dimensions may be more stringent.. All linear dimensions are in millimeters.. Coplanarity: 0. mm. Ball opening size is 0.8 mm (± 0.0 mm) 8-tfbga-BK-x8-0mic- FIGURE : 8-Ball Thin-Profile, Fine-pitch Ball Grid Array (TFBGA) mm x 8mm SST Package Code: BK TOP VIEW.00 ± ± BOTTOM VIEW ±0.0 (8X) A B C D E F G H J K L 0.0 L K J H G F E D C B A A CORNER A INDICATOR DETAIL 0. ± 0.0 SIDE VIEW SEATING PLANE 0.0 ± mm Note:. Complies with JEDEC Publication 9, MO-07, Variant CB-, dimensions except nominal ball width is larger.. All linear dimensions are in millimeters.. Coplanarity: 0.08 mm.. No ball is present in position A; a gold-colored indicator is present.. Ball opening size is 0.9 mm (± 0.0 mm). 8-wfbga-MQ-x-mic-.0 FIGURE : 8-Ball Very-Very-Thin-Profile, Fine-Pitch Ball Grid Array (WFBGA) mm x mm SST Package Code: MQ 9

30 Mbit / Mbit / 8 Mbit Multi-Purpose Flash TOP VIEW.00 ± ± BOTTOM VIEW ±0.0 (8X) A B C D E F G H J K L 0.0 L K J H G F E D C B A A CORNER DETAIL 0. max. 0.7 nom. A INDICATOR SIDE VIEW SEATING PLANE / mm Note:. Complies with JEDEC Publication 9, MO-07, variant CZB-, dimensions except bump height is much less.. All linear dimensions are in millimeters.. Coplanarity: 0.0 mm.. No ball is present at A; a gold-colored indicator is present.. Bump opening size is 0.9 (±0.0 mm). 8-xflga-CQ-x-9mic-.0 FIGURE : 8-Bump Extremely-Thin-Profile, Fine-Pitch Land Grid Array (XFLGA) mm x mm SST Package Code: CQ TOP VIEW BOTTOM VIEW.00 ± ± ±0.0 (8X) A B C D E F G H J K L 0.0 L K J H G F E D C B A A CORNER A INDICATOR DETAIL 0. ±0.0 SIDE VIEW SEATING PLANE 0. ± mm Note:. Complies with JEDEC Publication 9, MO-07, variant CZB-, dimensions except nominal ball width is larger.. All linear dimensions are in millimeters.. Coplanarity: 0.08 mm. No ball is present in position A; a gold-colored indicator is present.. Ball width at interface to package body surface is 0.9 mm. FIGURE : 8-Ball Very-Very-Thin-Profile, Fine-Pitch Ball Grid Array (WFBGA) mm x mm (Panel-based) SST Package Code: YQ 0 8-wfbga-YQ-x-0mic--.0

31 TABLE 7: Revision History Number Description Date 0 00 Data Book May 00 0 Added footnotes for MPF power usage and Typical conditions to Table 0 on page Mar 00 Clarified the Test Conditions for Power Supply Current and Read parameters in Table 0 on page Part number changes - see page 7 for additional information New Micro-Package part numbers added for SST9VF00A and SST9VF800A 0 New Micro-Package part numbers added for SST9VF00A / 800A (see page 7) Oct Data Book Nov 00 Updated the BK, MQ, and CQ package diagrams Added non-pb MPNs and removed footnote (see page 7) 08 Added MQ/MQE MPNs for the SSTVF00A device on page 7 Apr 00 Removed 90ns MPNs and footnote for the SSTVFx00A devices on page 7 Added RoHS compliance information on page and in the Product Ordering Information on page Clarified the solder temperature profile under Absolute Maximum Stress Ratings on page. 09 Removed valid combinations SST9LF00A--C-EK, SST9LF00A--C-BK, SST9LF00A--C-EKE, and SST9LF00A--C-BKE due to EOL Applied new format styles. 0 Add YQE package Removed all pb parts Feb 007 Aug 007 Silicon Storage Technology, Inc. 7 Sonora Court Sunnyvale, CA 908 Telephone Fax or