8 Mbit / 16 Mbit (x16) Multi-Purpose Flash SST39LF800 / SST39LF160 / SST39VF800 / SST39VF160

Transcription

1 Mbit / Mbit (x) Multi-Purpose Flash FEATURES: Organized as K x / M x Single Voltage Read and Write Operations -.0-.V for SSTLF00/0 -.-.V for SSTVF00/0 Superior Reliability - Endurance: 00,000 Cycles (typical) - Greater than 00 years Data Retention Low Power Consumption: - Active Current: ma (typical) - Standby Current: µa (typical) - Auto Low Power Mode: µa (typical) Sector-Erase Capability - Uniform KWord sectors Block-Erase Capability - Uniform KWord blocks Fast Read Access Time: - ns for SSTLF00/0-0 and 0 ns for SSTVF00/0 PRODUCT DESCRIPTION The SSTLF00/0 and SSTVF00/0 devices are K x / M x CMOS Multi-Purpose Flash (MPF) manufactured with SST s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SSTLF00/0 write (Program or Erase) with a.0-.v power supply. The SSTVF00/ 0 write (Program or Erase) with a.-.v power supply. These devices conform to JEDEC standard pinouts for x memories. Featuring high performance Word-Program, the SSTLF00/0 and SSTVF00/0 devices provide a typical Word-Program time of µsec.these devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 0,000 cycles. Data retention is rated at greater than 00 years. The SSTLF00/0 and SSTVF00/0 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering Latched Address and Data Fast Erase and Word-Program: - Sector-Erase Time: ms (typical) - Block-Erase Time: ms (typical) - Chip-Erase Time: 0 ms (typical) - Word-Program Time: µs (typical) - Chip Rewrite Time: seconds (typical) for SSTLF/VF00 seconds (typical) for SSTLF/VF0 Automatic Write Timing - Internal V PP Generation End-of-Write Detection - Toggle Bit - Data# Polling CMOS I/O Compatibility JEDEC Standard - Flash EEPROM Pinouts and command sets Packages Available - -Pin SOIC (00mil) - -Pin TSOP (mm x 0mm) - -Ball TFBGA (mm x 0mm) power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/ Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SSTLF00/0 and SSTVF00/0 are offered in -pin SOIC, -pin TSOP and -pin TFBGA packages. See Figures, and for pinouts. Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting low while Silicon Storage Technology, Inc.The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. -0 /00 These specifications are subject to change without notice.

2 keeping low. The address bus is latched on the falling edge of or, whichever occurs last. The data bus is latched on the rising edge of or, whichever occurs first. The SSTLF00/0 and SSTVF00/0 also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the I DD active read current from typically ma to typically µa. The Auto Low Power mode reduces the typical I DD active read current to the range of ma/mhz of read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Read The Read operation of the SSTLF00/0 and SSTVF00/0 is controlled by and, both have to be low for the system to obtain data from the outputs. is used for device selection. When is high, the chip is deselected and only standby power is consumed. is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either or is high. Refer to the Read cycle timing diagram for further details (Figure ). Word-Program Operation The SSTLF00/0 and SSTVF00/0 are programmed on a word-by-word basis. The Program operation consists of three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either or, whichever occurs last. The data is latched on the rising edge of either or, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth or, whichever occurs first. The Program operation, once initiated, will be completed within 0 µs. See Figures and for and controlled Program operation timing diagrams and Figure for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. Sector/Block-Erase Operation The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-byblock) basis. The SSTLF00/0 and SSTVF00/ 0 offer both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of Mbit / Mbit Multi-Purpose Flash KWord. The Block-Erase mode is based on uniform block size of KWord. The Sector-Erase operation is initiated by executing a six-byte command sequence with Sector- Erase command (0H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (0H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth pulse, while the command (0H or 0H) is latched on the rising edge of the sixth pulse. The internal Erase operation begins after the sixth pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 0 and for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored. Chip-Erase Operation The SSTLF00/0 and SSTVF00/0 provide a Chip-Erase operation, which allows the user to erase the entire memory array to the state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (0H) at address H in the last byte sequence. The Erase operation begins with the rising edge of the sixth or, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table for the command sequence, Figure for timing diagram, and Figure 0 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. Write Operation Status Detection The SSTLF00/0 and SSTVF00/0 provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ ) and Toggle Bit (DQ ). The End-of- Write detection mode is enabled after the rising edge of, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ or DQ. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two () times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid.

3 Data# Polling (DQ ) When the SSTLF00/0 and SSTVF00/0 are in the internal Program operation, any attempt to read DQ will produce the complement of the true data. Once the Program operation is completed, DQ will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ will produce a 0. Once the internal Erase operation is completed, DQ will produce a. The Data# Polling is valid after the rising edge of fourth (or ) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth (or ) pulse. See Figure for Data# Polling timing diagram and Figure for a flowchart. Toggle Bit (DQ ) During the internal Program or Erase operation, any consecutive attempts to read DQ will produce alternating s and 0 s, i.e., toggling between and 0. When the internal Program or Erase operation is completed, the DQ bit will stop toggling. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth (or ) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth (or ) pulse. See Figure for Toggle Bit timing diagram and Figure for a flowchart. Data Protection The SSTLF00/0 and SSTVF00/0 provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A or pulse of less than ns will not initiate a write cycle. V DD Power Up/Down Detection: The Write operation is inhibited when V DD is less than.v. Write Inhibit Mode: Forcing low, high, or high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Software Data Protection (SDP) The SSTLF00/0 and SSTVF00/0 provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. These devices are shipped with the Software Data Protection permanently enabled. See Table for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode within T RC. The contents of DQ -DQ are Don t Care during any SDP command sequence. Common Flash Memory Interface (CFI) The SSTLF00/0 and SSTVF00/0 also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write three-byte sequence, same as product ID entry command with H (CFI Query command) to address H in the last byte sequence. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in tables through. The system must write the CFI Exit command to return to Read mode from the CFI Query mode. Product Identification The Product Identification mode identifies the devices as the SSTLF/VF00, SSTLF/VF0 and manufacturer as SST. This mode may be accessed by hardware or software operations. The hardware operation is typically used by a programmer to identify the correct algorithm for the SSTLF00/0 and SSTVF00/0. Users may wish to use the Software Product Identification operation to identify the part (i.e., using the device code) when using multiple manufacturers in the same socket. For details, see Table for hardware operation or Table for software operation, Figure for the Software ID Entry and Read timing diagram and Figure for the Software ID Entry command sequence flowchart. TABLE : PRODUCT IDENTIFICATION TABLE Address Data Manufacturer s Code 0000H 00BFH Device Code SSTLF/VF00 000H H Device Code SSTLF/VF0 000H H PGM T.0 Product Identification Mode Exit/CFI Mode Exit In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read operation. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program or Erase operation. See Table for software command codes, Figure for timing waveform and Figure for a flowchart. 0

4 FUTIONAL BLOCK DIAGRAM X-Decoder EEPROM Cell Array Memory Address Address Buffer & Latches Y-Decoder Control Logic I/O Buffers and Data Latches DQ - DQ0 ILL B.0 SSTLF/VF0 SSTLF/VF00 SSTLF/VF00 SSTLF/VF0 A A A A A A0 A A A A A A A A A A A A A A A A A A0 A A A A A A A A A A A 0 0 Standard Pinout Top View Die Up 0 0 A V SS DQ DQ DQ DQ DQ DQ DQ DQ V DD DQ DQ DQ0 DQ DQ DQ DQ DQ0 V SS A0 A V SS DQ DQ DQ DQ DQ DQ DQ DQ V DD DQ DQ DQ0 DQ DQ DQ DQ DQ0 V SS A0 FIGURE : PIN ASSIGNMENTS FOR -PIN TSOP ILL F0.0 TOP VIEW (balls facing down) TOP VIEW (balls facing down) A A A A A A A A A A0 A A A A A A A A DQ VSS DQ DQ DQ DQ DQ DQ VDD DQ DQ DQ0 DQ DQ DQ0 A0 DQ DQ DQ VSS A A A A A A A A A A0 A A A A A A A A A DQ VSS DQ DQ DQ DQ DQ DQ VDD DQ DQ DQ0 DQ DQ DQ0 A0 DQ DQ DQ VSS A B C D E F G H SSTLF/VF00 ILL F0b.0 A B C D E F G H SSTLF/VF0 ILL F0.0 FIGURE : PIN ASSIGNMENTS FOR -BALL TFBGA

5 A A A A A A A A A A0 VSS DQ0 DQ DQ DQ DQ DQ0 DQ DQ 0 0 Top View Die Up SSTLF/VF FIGURE : PIN ASSIGNMENTS FOR -PIN SOIC TABLE : PIN DESCRIPTION TABLE : OPERATION MODES SELECTION A A A0 A A A A A A VSS DQ DQ DQ DQ DQ DQ DQ DQ VDD ILL F0a. A A A A A A A A A A0 VSS DQ0 DQ DQ DQ DQ DQ0 DQ DQ 0 0 Top View Die Up SSTLF/VF0 0 0 ILL F0b. Symbol Pin Name Functions A MS-A 0 Address Inputs To provide memory addresses. During Sector-Erase A MS-A address lines will select the sector. During Block-Erase A MS-A address lines will select the block. DQ -DQ 0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a write cycle. The outputs are in tri-state when or is high. Chip Enable To activate the device when is low. Output Enable To gate the data output buffers. Write Enable To control the Write operations. V DD Power Supply To provide power supply voltage:.0-.v for SSTLF00/0.-.V for SSTVF00/0 Vss Ground No Connection Unconnected pins. Note: A MS = Most significant address A MS = A for SSTLF/VF00 and A for SSTLF/VF0 PGM T. Mode A DQ Address Read V IL V IL V IH A IN D OUT A IN Program V IL V IH V IL A IN D IN A IN Erase V IL V IH V IL X X Sector or block address, XXh for Chip-Erase Standby V IH X X X High Z X Write Inhibit X V IL X X High Z/ D OUT X X X V IH X High Z/ D OUT X Product Identification Hardware Mode V IL V IL V IH V H Manufacturer Code (00BF) Device Code () A () MS - A = V IL, A 0 = V IL A () MS - A = V IL, A 0 = V IH Software Mode V IL V IL V IH A IN See Table Note: () Device Code for SSTLF/VF00 and for SSTLF/VF0 () A MS = Most significant address A MS = A for SSTLF/VF00 and A for SSTLF/VF0 A A A A0 A A A A A A VSS DQ DQ DQ DQ DQ DQ DQ DQ VDD PGM T.0 0

6 TABLE : SOFTWARE COMMAND SEQUEE Mbit / Mbit Multi-Purpose Flash Command st Bus nd Bus rd Bus th Bus th Bus th Bus Sequence Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Write Cycle Addr () Data Addr () Data Addr () Data Addr () Data Addr () Data Addr () Data Word-Program H AAH AAAH H H A0H WA () Data Sector-Erase H AAH AAAH H H 0H H AAH AAAH H () SA x 0H Block-Erase H AAH AAAH H H 0H H AAH AAAH H () BA x 0H Chip-Erase H AAH AAAH H H 0H H AAH AAAH H H 0H Software ID Entry H AAH AAAH H H 0H CFI Query Entry H AAH AAAH H H H Software ID Exit/ XXH F0H CFI Exit Software ID Exit/ H AAH AAAH H H F0H CFI Exit Notes: () Address format A-A0 (Hex). Addresses A, A, A, and A are Don t Care for Command sequence for SSTLF/VF00. Addresses A, A, A, A and A are "Don't Care" for Command sequence for SSTLF/VF0. () SA x for Sector-Erase; uses A MS-A address lines BA x, for Block-Erase; uses A MS-A address lines AMS = Most significant address AMS = A for SSTLF/VF00 and A for SSTLF/VF0 () WA = Program word address () Both Software ID Exit operations are equivalent () DQ - DQ are Don t Care for Command sequence () With A MS -A =0; SST Manufacturer Code = 00BFH, is read with A 0 = 0, SSTLF/VF00 Device Code = H, is read with A 0 =. SSTLF/VF0 Device Code = H, is read with A 0 =. A MS = Most significant address A MS = A for SSTLF/VF00 and A for SSTLF/VF0 () The device does not remain in Software Product ID Mode if powered down. PGM T.0 TABLE : CFI QUERY IDENTIFICATION STRING FOR SSTLF/VF00 AND SSTLF/VF0 Address Data Data 0H 00H H 00H Query Unique ASCII string QRY H 00H H 000H Primary OEM command set H 000H H 0000H Address for Primary Extended Table H 0000H H 0000H Alternate OEM command set (00H = none exists) H 0000H H 0000H Address for Alternate OEM extended Table (00H = none exits) AH 0000H Note : Refer to CFI publication 00 for more details. PGM T.0

7 TABLE : SYSTEM INTERFACE INFORMATION FOR SSTLF/VF00 AND SSTLF/VF0 Address Data Data BH 00H () V DD Min. (Program/Erase) 000H () DQ-DQ: Volts, DQ-DQ0: 00 millivolts CH 00H V DD Max. (Program/Erase) DQ-DQ: Volts, DQ-DQ0: 00 millivolts DH 0000H V PP min. (00H = no V PP pin) EH 0000H V PP max. (00H = no V PP pin) FH 000H Typical time out for Word-Program N µs ( = µs) 0H 0000H Typical time out for min. size buffer program N µs (00H = not supported) H 000H Typical time out for individual Sector/Block-Erase N ms ( = ms) H 000H Typical time out for Chip-Erase N ms ( = ms) H 000H Maximum time out for Word-Program N times typical ( x = µs) H 0000H Maximum time out for buffer program N times typical H 000H Maximum time out for individual Sector/Block-Erase N times typical ( x = ms) H 000H Maximum time out for Chip-Erase N times typical ( x = ms) Note: () 000H for SSTLF00/0 and 00H for SSTVF00/0 PGM T. TABLE A: DEVICE GEOMETRY INFORMATION FOR SSTLF/VF00 Address Data Data H 00H Device size = N Bytes (H = 0; 0 = M Bytes) H 000H Flash Device Interface description; 000H = x-only asynchronous interface H 0000H AH 0000H Maximum number of byte in multi-byte write = N (00H = not supported) BH 0000H CH 000H Number of Erase Sector/Block sizes supported by device DH 00FFH Sector Information (y + = Number of sectors; z x B = sector size) EH 0000H y = + = sectors (00FFH = ) FH 000H 0H 0000H z = x Bytes = KBytes/sector (000H = ) H 000FH Block Information (y + = Number of blocks; z x B = block size) H 0000H y = + = blocks (000FH = ) H 0000H H 000H z = x Bytes = KBytes/block (000H = ) PGM Ta.0 TABLE B: DEVICE GEOMETRY INFORMATION FOR SSTLF/VF0 Address Data Data H 00H Device size = N Byte (H = ; = M Bytes) H 000H Flash Device Interface description; 000H = x-only asynchronous interface H 0000H AH 0000H Maximum number of byte in multi-byte write = N (00H = not supported) BH 0000H CH 000H Number of Erase Sector/Block sizes supported by device DH 00FFH Sector Information (y + = Number of sectors; z x B = sector size) EH 000H y = + = sectors (0FF = ) FH 000H 0H 0000H z = x Bytes = KBytes/sector (000H = ) H 00FH Block Information (y + = Number of blocks; z x B = block size) H 0000H y = + = blocks (00F = ) H 0000H H 000H z = x Bytes = KBytes/block (000H = ) PGM T.0 0

8 Absolute Maximum Stress Ratings (Applied conditions greater than those listed under Absolute Maximum Stress Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias... - C to + C Storage Temperature... - C to +0 C D. C. Voltage on Any Pin to Ground Potential V to V DD + 0.V Transient Voltage (<0 ns) on Any Pin to Ground Potential V to V DD +.0V Voltage on A Pin to Ground Potential V to.v Package Power Dissipation Capability (Ta = C)....0W Surface Mount Lead Soldering Temperature ( Seconds)... 0 C Output Short Circuit Current ()... 0 ma Note: () Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE FOR SSTLF00/0 Range Ambient Temp V DD Commercial 0 C to +0 C.0 -.V OPERATING RANGE FOR SSTVF00/0 Range Ambient Temp V DD Commercial 0 C to +0 C. -.V Industrial -0 C to + C. -.V AC CONDITIONS OF TEST Input Rise/Fall Time... ns Output Load... C L = 0 pf for SSTLF00/0 C L = 00 pf for SSTVF00/0 See Figures and

9 TABLE : DC OPERATING CHARACTERISTICS VDD =.0-.V FOR SSTLF00/0 AND.-.V FOR SSTVF00/0 Limits Symbol Parameter Min Max Units Test Conditions I DD Power Supply Current ==V IL, =V IH, all I/Os open, Read 0 ma Address input = V IL/V IH, at f=/t RC Min. Program and Erase ma ==V IL, =V IH, V DD =V DD Max. I SB Standby V DD Current 0 µa =V IHC, V DD = V DD Max. I ALP Auto Low Power Current 0 µa =V ILC, V DD = V DD Max., all inputs = V IHC or V ILC, = V IHC I LI Input Leakage Current µa V IN =GND to V DD, V DD = V DD Max. I LO Output Leakage Current µa V OUT =GND to V DD, V DD = V DD Max. V IL Input Low Voltage 0. V V DD = V DD Min. V ILC Input Low Voltage (CMOS) 0. V V DD = V DD Max. V IH Input High Voltage 0. V DD V V DD = V DD Max. V IHC Input High Voltage (CMOS) V DD -0. V V DD = V DD Max. V OL Output Low Voltage 0. V I OL = 00 µa, V DD = V DD Min. V OH Output High Voltage V DD-0. V I OH = -00 µa, V DD = V DD Min. V H Supervoltage for A pin.. V = =V IL, = V IH I H Supervoltage Current 00 µa = = V IL, = V IH, A = V H Max. for A pin TABLE : RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter Minimum Units T () PU-READ Power-up to Read Operation 00 µs T () PU-WRITE Power-up to Program/Erase 00 µs Operation PGM T0.0 Note: () This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 0: CAPACITAE (Ta = C, f= Mhz, other pins open) Parameter Description Test Condition Maximum C () I/O I/O Pin Capacitance V I/O = 0V pf C () IN Input Capacitance V IN = 0V pf TABLE : RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method N () END Endurance 0,000 Cycles JEDEC Standard A T () DR Data Retention 00 Years JEDEC Standard A0 V () ZAP_HBM ESD Susceptibility 000 Volts JEDEC Standard A Human Body Model V () ZAP_MM ESD Susceptibility 00 Volts JEDEC Standard A Machine Model I () LTH Latch Up 00 + I DD ma JEDEC Standard PGM T.0 PGM T.0 Note: () This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. PGM T.0 Note: () This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 0

10 AC CHARACTERISTICS TABLE : READ CYCLE TIMING PARAMETERS VDD =.0-.V FOR SSTLF00/0 AND VDD =.-.V FOR SSTVF00/0 SSTLF00/0- SSTVF00/0-0 SSTVF00/0-0 Symbol Parameter Min Max Min Max Min Max Units T RC Read Cycle Time 0 0 ns T CE Chip Enable Access Time 0 0 ns T AA Address Access Time 0 0 ns T OE Output Enable Access Time 0 ns T () CLZ Low to Active Output ns T () OLZ Low to Active Output ns T () CHZ High to High-Z Output 0 0 ns T () OHZ High to High-Z Output 0 0 ns T () OH Output Hold from Address ns Change Note: () This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. PGM T. TABLE : PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter Min Max Units T BP Word-Program Time 0 µs T AS Address Setup Time 0 ns T AH Address Hold Time 0 ns T CS and Setup Time 0 ns T CH and Hold Time 0 ns T OES High Setup Time 0 ns T OEH High Hold Time 0 ns T CP Pulse Width 0 ns T WP Pulse Width 0 ns T WPH () Pulse Width High 0 ns T CPH () Pulse Width High 0 ns T DS Data Setup Time 0 ns T DH () Data Hold Time 0 ns T IDA () Software ID Access and Exit Time 0 ns T SE Sector-Erase ms T BE Block-Erase ms T SCE Chip-Erase 00 ms PGM T.0 Note: () This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. 0

11 TRC TAA ADDRESS AMS-0 DQ -0 Note: VIH FIGURE : READ CYCLE TIMING DIAGRAM TCE TOLZ TOE HIGH-Z T CLZ T OH TCHZ DATA VALID A MS = Most significant address A MS = A for SSTLF/VF00 and A for SSTLF/VF0 DATA VALID TOHZ HIGH-Z ILL F0.0 INTERNAL PROGRAM OPERATION STARTS T BP ADDRESS A MS-0 T AS AAA ADDR T AH T WP T WPH T DS T DH 0 T CH T CS DQ -0 Note: XXAA XX XXA0 DATA SW0 SW SW WORD (ADDR/DATA) A MS = Most significant address A MS = A for SSTLF/VF00 and A for SSTLF/VF0 ILL F0.0 FIGURE : CONTROLLED PROGRAM CYCLE TIMING DIAGRAM

12 INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 AAA ADDR TAH TCP TDH TAS TCPH TDS TCH T CS DQ -0 XXAA XX XXA0 DATA Note: SW0 SW SW WORD (ADDR/DATA) A MS = Most significant address A MS = A for SSTLF/VF00 and A for SSTLF/VF0 ILL F0.0 FIGURE : CONTROLLED PROGRAM CYCLE TIMING DIAGRAM ADDRESS A MS-0 T CE T OEH T OES T OE DQ DATA DATA# DATA# DATA Note: A MS = Most significant address A MS = A for SSTLF/VF00 and A for SSTLF/VF0 ILL F0.0 FIGURE : DATA# POLLING TIMING DIAGRAM

13 ADDRESS AMS-0 TCE TOEH TOE TOES DQ Note: TWO READ CYCLES WITH SAME OUTPUTS A MS = Most significant address A MS = A for SSTLF/VF00 and A for SSTLF/VF0 ILL F0.0 FIGURE : TOGGLE BIT TIMING DIAGRAM SIX-BYTE CODE FOR CHIP-ERASE T SCE ADDRESS A MS-0 AAA AAA 0 T WP DQ -0 Note: AA 0 AA SW0 SW SW SW SW SW FIGURE : CONTROLLED CHIP-ERASE TIMING DIAGRAM 0 This device also supports controlled Chip-Erase operation. The and signals are interchageable as long as minimum timings are met. (See Table ) A MS = Most significant address A MS = A for SSTLF/VF00 and A for SSTLF/VF0 ILL F0.0

14 SIX-BYTE CODE FOR BLOCK-ERASE T BE ADDRESS A MS-0 AAA AAA BA X T WP DQ -0 AA 0 AA 0 SW0 SW SW SW SW SW Note: This device also supports controlled Block-Erase operation. The and signals are interchageable as long as minimum timings are met. (See Table ) BA X = Block Address A MS = Most significant address A MS = A for SSTLF/VF00 and A for SSTLF/VF0 ILL F.0 FIGURE 0: CONTROLLED BLOCK-ERASE TIMING DIAGRAM SIX-BYTE CODE FOR SECTOR-ERASE T SE ADDRESS A MS-0 AAA AAA SA X T WP DQ -0 AA 0 AA 0 SW0 SW SW SW SW SW Note: This device also supports controlled Sector-Erase operation. The and signals are interchageable as long as minimum timings are met. (See Table ) SA X = Sector Address A MS = Most significant address A MS = A for SSTLF/VF00 and A for SSTLF/VF0 ILL F.0 FIGURE : CONTROLLED SECTOR-ERASE TIMING DIAGRAM

15 THREE-BYTE SEQUEE FOR SOFTWARE ID ENTRY ADDRESS A -0 AAA T WP T IDA DQ -0 XXAA T WPH XX XX0 SW0 SW SW T AA 00BF Device ID ILL F0. Device ID = for SSTLF/VF00 and for SSTLF/VF0 FIGURE : SOFTWARE ID ENTRY AND READ ADDRESS A-0 THREE-BYTE SEQUEE FOR CFI QUERY ENTRY AAA 0 TWP TIDA DQ-0 XXAA TWPH XX XX TAA FIGURE : CFI QUERY ENTRY AND READ SW0 SW SW ILL F0.0

16 THREE-BYTE SEQUEE FOR SOFTWARE ID EXIT AND RESET ADDRESS A-0 AAA DQ-0 AA F0 TIDA T WP T WHP SW0 SW SW ILL F0.0 FIGURE : SOFTWARE ID EXIT/CFI EXIT

17 V IHT V ILT INPUT V IT REFEREE POINTS V OT OUTPUT AC test inputs are driven at V IHT (0. V DD ) for a logic and V ILT (0. V DD ) for a logic 0. Measurement reference points for inputs and outputs are V IT (0. V DD ) and V OT (0. V DD ). Inputs rise and fall times (0% «0%) are < ns. FIGURE : AC INPUT/OUTPUT REFEREE WAVEFORMS ILL F. Note: V IT V INPUT Test V OT V OUTPUT Test V IHT V INPUT HIGH Test V ILT V INPUT LOW Test TO TESTER FIGURE : A TEST LOAD EXAMPLE TO DUT ILL F. CL 0

18 Start Load data: AA Address: Load data: Address: AAA Load data: A0 Address: Load Word Address/Word Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed ILL F.0 FIGURE : WORD-PROGRAM ALGORITHM

19 Internal Timer Toggle Bit Data# Polling Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated Wait TBP, TSCE, TSE or TBE Read word Read DQ Program/Erase Completed Read same word No Is DQ = true data? Yes No Does DQ match? Program/Erase Completed Yes Program/Erase Completed ILL F.0 0 FIGURE : WAIT OPTIONS

20 CFI Query Entry Command Sequence Software Product ID Entry Command Sequence Software ID Exit/CFI Exit Command Sequence Load data: XXAA Address: Load data: XXAA Address: Load data: XXAA Address: Load data: XXF0 Address: XX Load data: XX Address: AAA Load data: XX Address: AAA Load data: XX Address: AAA Wait TIDA Load data: XX Address: Load data: XX0 Address: Load data: XXF0 Address: Return to normal operation Wait TIDA Wait TIDA Wait TIDA Read CFI data Read Software ID Return to normal operation ILL F.0 FIGURE : SOFTWARE PRODUCT ID/CFI COMMAND FLOWCHARTS 0

21 Chip-Erase Command Sequence Sector-Erase Command Sequence Block-Erase Command Sequence Load data: XXAA Address: Load data: XXAA Address: Load data: XXAA Address: Load data: XX Address: AAA Load data: XX Address: AAA Load data: XX Address: AAA Load data: XX0 Address: Load data: XX0 Address: Load data: XX0 Address: Load data: XXAA Address: Load data: XXAA Address: Load data: XXAA Address: Load data: XX Address: AAA Load data: XX Address: AAA Load data: XX Address: AAA Load data: XX0 Address: Load data: XX0 Address: SAX Load data: XX0 Address: BAX 0 Wait TSCE Wait TSE Wait TBE Chip erased to FFFFH Sector erased to FFFFH Block erased to FFFFH ILL F.0 FIGURE 0: ERASE COMMAND SEQUEE

22 Device Speed Suffix Suffix SSTxFxxx - XXX - XX - XX Mbit / Mbit Multi-Purpose Flash Package Modifier J = pins K = pins Numeric = Die modifier Package Type E = TSOP (mm x 0mm) B = TFBGA (0. mm pitch; mm x 0mm) S = SOIC (00 mil) Temperature Range C = Commercial = 0 to 0 C I = Industrial = -0 to C Minimum Endurance = 0,000 cycles Read Access Speed = ns, 0 = 0 ns, 0 = 0 ns Device Density 00 = Megabit 0 = Megabit Voltage L =.0-.V V =.-.V SSTLF00 Valid combinations SSTLF00--C-EK SSTLF00--C-BK SSTLF00--C-SJ SSTVF00 Valid combinations SSTVF00-0-C-EK SSTVF00-0-C-BK SSTVF00-0-C-SJ SSTVF00-0-C-EK SSTVF00-0-C-BK SSTVF00-0-C-SJ SSTVF00-0-I-EK SSTVF00-0-I-BK SSTVF00-0-I-SJ SSTVF00-0-I-EK SSTVF00-0-I-BK SSTVF00-0-I-SJ SSTLF0 Valid combinations SSTLF0--C-EK SSTLF0--C-BK SSTLF0--C-SJ SSTVF0 Valid combinations SSTVF0-0-C-EK SSTVF0-0-C-BK SSTVF0-0-C-SJ SSTVF0-0-C-EK SSTVF0-0-C-BK SSTVF0-0-C-SJ SSTVF0-0-I-EK SSTVF0-0-I-BK SSTVF0-0-I-SJ SSTVF0-0-I-EK SSTVF0-0-I-BK SSTVF0-0-I-SJ Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.

23 PACKAGING DIAGRAMS PIN # IDENTIFIER BSC Note:. Complies with JEDEC publication MO- DD dimensions, although some dimensions may be more stringent.. All linear dimensions are in millimeters (min/max).. Coplanarity: 0. (±.0) mm..tsop-ek-ill. -PIN THIN SMALL OUTLINE PACKAGE (TSOP) MM X 0MM SST PACKAGE CODE: EK A CORNER TOP VIEW A B C D E F G H SIDE VIEW.0 ± ± BOTTOM VIEW 0.00 ± H G F E D C B A A CORNER 0.0 ± 0.0 (X) 0 SEATING PLANE 0. ± ba TFBGA.BKx0-ILL. Note:. Complies with the general requirements of JEDEC publication MO-0, although some dimensions may be more stringent. (This specific outline variant has not yet been registered). All linear dimensions are in millimeters (min/max).. Coplanarity: 0. (±.0) mm. -BALL THIN PROFILE FINE-PITCH BALL GRID ARRAY (TFBGA) MM X 0MM SST PACKAGE CODE: BK

24 ..0.. Pin # Identifier soic00mil-SJ-ILL. Note:. All linear dimensions are in millimeters (min/max).. Coplanarity: 0. (±.0) mm. -PIN SMALL OUTLINE IC (SOIC/00MIL) SST PACKAGE CODE: SJ Silicon Storage Technology, Inc. Sonora Court Sunnyvale, CA 0 Telephone 0--0 Fax or Literature FaxBack --, International --