PM PDRB X DATA SHEET. Memory Module Part Number. PM MByte Non ECC BUFFALO INC. (1/15)

Transcription

1 DATA SHEET Memory Module Part Number PM MByte Non ECC (1/15)

2 Table of Contents 1. Description 2. Module Specification 3. Module Pinout 4. Mechanical Design 5. Block Diagram 6. Electrical Specifications 6.1 Absolute Maximum Rating 6.2 Recommended Operating Conditions 6.3 Pin Capacitance 6.4 D.C. Characters 6.5 A.C. Timing Characters 7. Serial Presence Detect (SPD) Data Structure 8. Packing Specification 9. Seal / Label Specification 10. Revision History (2/15)

3 1. Description 100pin Unbuffered DIMM (100MHz CL=2) 2. Module Specification Items Memory Size Specification 256MByte Module Bank 2 ECC bit Data Bus Width Clock Frequency Interface Operating Voltage Burst Length DRAM Organization PCB Contact Tab PCB Dimension SPD Non ECC 32bit 100MHz(CL=2) LVTTL 3.3V±0.3V 1,2,4,8,Full 32Mx8bit SDRAM X0X8KPM-B 100pin GOLD Flash Plating Ni : min 2.00µm Au : min 0.05µm 90.19mmx29.20mmx1.27mm Support (3/15)

4 3. Module Pinout Front side Back side Pin No. Signal name Pin No. Signal name Pin No. Signal name Pin No. Signal name 1 Vss 26 Vss 51 Vss 76 Vss 2 DQ0 27 CKE0 52 DQ8 77 CKE1 3 DQ1 28 /WE 53 DQ9 78 NC 4 DQ2 29 /S0 54 DQ10 79 /S1 5 DQ3 30 /S2 55 DQ11 80 /S3 6 Vcc 31 Vcc 56 Vcc 81 Vcc 7 DQ4 32 NC 57 DQ12 82 NC 8 DQ5 33 NC 58 DQ13 83 NC 9 DQ6 34 NC 59 DQ14 84 NC 10 DQ7 35 NC 60 DQ15 85 NC 11 DQMB0 36 Vss 61 DQMB1 86 Vss 12 Vss 37 DQMB2 62 Vss 87 DQMB3 13 A0 38 DQ16 63 A1 88 DQ24 14 A2 39 DQ17 64 A3 89 DQ25 15 A4 40 DQ18 65 A5 90 DQ26 16 A6 41 DQ19 66 A7 91 DQ27 17 A8 42 Vcc 67 A9 92 Vcc 18 A10 43 DQ20 68 BA0 93 DQ28 19 BA1 44 DQ21 69 A11 94 DQ29 20 A12 45 DQ22 70 A13 95 DQ30 21 Vcc 46 DQ23 71 Vcc 96 DQ31 22 NC 47 Vss 72 /RAS 97 Vss 23 NC 48 SDA 73 /CAS 98 SA0 24 NC 49 SCL 74 NC 99 SA1 25 CK0 50 Vcc 75 CK1 100 SA2 (4/15)

5 Pin Function Signal Name A0 to A12 A13 BA0, BA1 DQ0 to DQ31 CK0, CK1 CKE0, CKE1 Function Address Input Not Used (Address Input) Bank Select Address Input Data Input / Output Clock Input Clock Enable Input /S0 to /S3 Chip Select Input /RAS /CAS /WE DQMB0 to DQMB3 SDA SCL SA0 to SA2 Vcc Vss NC Row Address Strobe Input Column Address Strobe Input Write Enable Input Byte Data Mask Input Data Input / Output for Serial PD Clock Input for Serial PD Serial Address Input Primary Positive Power Supply Ground Not Connected (5/15)

6 4. Mechanical Design 90.19± max 2-R ± ± A B C 2-φ3.00± ± ± min 3.125± R1 2-R1 2.50± ± ± ±0.1 1± DETAIL A DETAIL B DETAIL C Tolerance: JIS B0405 f-class Unit: mm Except V-cut area (6/15)

7 5. Block Diagram /S1 /S0 DQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 /S3 /S2 DQMB2 DQMB /S DQMB /S DQMB /S DQMB /S I/O 7 I/O 0 DQ16 I/O 7 I/O 0 I/O 6 DQ17 I/O 6 D1 D5 D3 I/O 5 DQ18 I/O 5 D7 I/O 4 DQ19 I/O 4 I/O 4 I/O 5 I/O 6 DQ20 DQ21 DQ22 I/O 7 I/O 6 I/O 5 I/O 0 I/O 7 DQ23 I/O 0 I/O 4 DQMB1 DQMB3 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB /S I/O 4 I/O 5 D2 I/O 6 I/O 7 I/O 0 DQMB /S D6 I/O 0 I/O 4 I/O 5 I/O 6 I/O 7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQMB /S DQMB /S I/O 7 I/O 0 I/O 6 D4 I/O 5 D8 I/O 4 I/O 4 I/O 5 I/O 6 I/O 0 I/O 7 Note : All resistor values are 10ohm unless otherwise specified. BA(1:0) A(12:0) /RAS /CAS /WE CKE0 CKE1 BA(1:0):SDRAMS D1-D8 A(12:0):SDRAMS D1-D8 /RAS:SDRAMS D1-D8 /CAS:SDRAMS D1-D8 /WE:SDRAMS D1-D8 CKE:SDRAMS D1-D4 CKE:SDRAMS D5-D8 SCL Vcc SERIAL PD SDA WP A0 A1 A2 SA0 SA1 SA2 D1-D8 47kohm Vss D1-D8 Bypass :Sixteen 0.33μF CK0 10ohm SDRAM D1 SDRAM D2 CK1 10ohm SDRAM D5 SDRAM D6 10ohm SDRAM D3 SDRAM D4 10ohm SDRAM D7 SDRAM D8 (7/15)

8 6. Electrical Specifications 6.1 Absolute Maximum Rating Parameter Symbol Value Unit Voltage Any Pin Relative to Vss V T -0.3~Vcc+0.3 (MAX 4.6) V Supply Voltage Relative to Vss V CC -0.3~4.6 V Power Dissipation P D 8 W Short Circuit Output Current I O 50 ma 6.2 Recommended Operating Conditions Parameter Symbol MIN MAX Unit Supply Voltage V CC V High Level Input Voltage V IH 2.0 Vcc+0.3 V Low Level Input Voltage V IL V Operating Ambient Temperature T A 0 70 C (8/15)

9 6.3 Pin Capacitance (Vcc=3.3V,T A =25 C,f=1MHz) Parameter Symbol Maximum Pin Capacitance Unit CK Input Pin Capacitance (CK0) CK Input Pin Capacitance (CK1) /S Input Pin Capacitance (/S0) /S Input Pin Capacitance (/S1) /S Input Pin Capacitance (/S2) /S Input Pin Capacitance (/S3) CKE Input Pin Capacitance (CKE0) CKE Input Pin Capacitance (CKE1) DQM Input Pin Capacitance (DQMB0-3) Other Input Pin Capacitance (A,BA,/RAS,/CAS,/WE) DQ Input / Output Pin Capacitance (DQ0-DQ31) C ICK1 20 pf C ICK2 20 pf C IS1 10 pf C IS2 10 pf C IS3 10 pf C IS4 10 pf C ICKE1 20 pf C ICKE2 20 pf C IDQM1 10 pf C IN 40 pf C OUT 13 pf (9/15)

10 6.4 D.C. Characters Parameter Symbol Value Unit Test Condition Operating current I CC1 MAX 1320 ma Precharge Standby current in power down mode Precharge Standby current in non power down mode Active standby current in power down mode Active standby current in non power down mode Operating current (Burst mode) I CC2P MAX 24 ma I CC2PS MAX 16 ma I CC2N MAX 320 ma I CC2NS MAX 160 ma I CC3P MAX 80 ma I CC3PS MAX 48 ma I CC3N MAX 480 ma I CC3NS MAX 240 ma I CC4 MAX 1120 ma Burst length=1, t RC t RC (min), I O =0mA, One bank active CKE V IL (max), t CK = 15ns CKE V IL (max), t CK = CKE, /S V IH (min), t CK = 15ns CKE V IH (min), t CK = CKE V IL (max), t CK = 15ns CKE V IL (max), t CK = CKE, /S V IH (min), t CK = 15ns CKE V IH (min), t CK = t CK t CK (min) Io=0mA, One bank active Auto refresh current I CC5 MAX 2560 ma t RC t RC (min) Self refresh current I CC6 MAX 40 ma CKE 0.2V MIN -80 µa Input leakage current I IL MAX 80 µa All other pins are not under test=0v 0V V IN V CC Output High Voltage V OH MIN 2.4 V I OH = -2mA Output Low Voltage V OL MAX 0.4 V I OL = 2mA (10/15)

11 6.5 A.C. Timing Characters Parameter Symbol MIN MAX Unit Clock Period /CAS Latency = 2 /CAS Latency = 3 t CLK ns Clock High Time t CH 3.0 ns Clock Low Time t CL 3.0 ns Input Setup Times t SI 2.0 ns Input Hold Times t HI 1.0 ns Output Valid From Clock /CAS Latency = 2 /CAS Latency = 3 t AC ns Output Hold From Clock t OH 2.7 ns /RAS to /CAS Delay t RCD 20 ns /RAS Active Time t RAS ,000 ns /RAS Precharge Time t RP 20 ns Act to Act Command Period t RRD 20 ns Refresh Time t REF 64 (8192cycle) ms Mode Register cycle time t MRC 20 ns Table Timing Specification Reference Level is set at 1.4V. (11/15)

12 7. Serial Presence Detect (SPD) Data Structure Byte No. Function Hex Value Function Supported 0 Defines # of bytes written into serial memory at module manufacturer 80h 128Bytes 1 Total # of bytes of SPD memory device 08h 256Bytes (2k bit) 2 Fundamental memory type (FPM, EDO, SDRAM..) 04h SDRAM 3 # of row addresses on this assembly 0Dh 13 4 # Column Addresses on this assembly 0Ah 10 5 # Module Banks on this assembly 02h 2BANK 6 Data Width of this assembly 20h 7... Data Width continuation 00h 32bit 8 Voltage interface standard of this assembly 01h LVTTL 9 SDRAM Cycle time (highest CAS latency) A0h 10.0ns (CAS Latency =3) 10 SDRAM Access from Clock (highest CAS latency) 60h 6.0ns (CAS Latency =3) 11 DIMM Configuration type (non-parity,ecc) 00h NonECC 12 Refresh Rate/Type 82h 7.8µs 13 Primary SDRAM Width 08h x8bit 14 Error Checking SDRAM width 00h None 15 Minimum Clock Delay Back to Back Random Column Address 01h 1CLK 16 Burst Lengths Supported 8Fh Burst Lengths (1,2,4,8,FULL) 17 # of Banks on Each SDRAM Device 04h 4Bank 18 CAS# Latency 06h CAS Latency =2,3 19 CS# Latency 01h CS Latency =0 20 Write Latency 01h WE Latency =0 21 SDRAM Module Attributes 00h UnBuffered 22 SDRAM Device Attributes: General 0Eh SDRAM Cycle time (2nd highest CAS latency) A0h 10.0ns (CAS Latency =2) 24 SDRAM Access from Clock (2nd highest CAS latency) 60h 6.0ns (CAS Latency =2) 25 SDRAM Cycle time (3rd highest CAS latency) 00h Undefined 26 SDRAM Access from Clock (3rd highest CAS latency) 00h Undefined 27 Minimum Row Precharge Time 14h 20ns 28 Row Activate to Row Activate Min. 14h 20ns 29 RAS to CAS Delay Min 14h 20ns 30 Minimum RAS Pulse Width 32h 50ns 31 Density of each bank on module 20h 128MB 32 Command and Address signal input setup time 20h 2.0ns 33 Command and Address signal input hold time 10h 1.0ns 34 Data signal input setup time 20h 2.0ns 35 Data signal input hold time 10h 1.0ns Superset Information (may be used in future) 00h Undefined 62 SPD Data Revision Code 01h Rev 1 63 Checksum for bytes 0-62 E9h Checksum 64 83h Manufacturer s JEDEC ID code per JEP-106 7Fh BUFFALO h 72 Manufacturing Location 01h Manufacturing Location Manufacturer s Part Number 20h blank Revision Code 00h Undefined Manufacturing Date Undefined Assembly Serial Number Undefined Manufacturer Specific Data Undefined 126 Intel specification frequency 00h Undefined 127 Intel Specification CAS# Latency support 00h Undefined 128+ Unused storage locations Undefined (12/15)

13 8. Packing Specification 1 Part number label 2 MAX 100 modules 3 Part Number (13/15)

14 9. Seal / Label Specification Part Number Label(Front side) PM *** PC100U Z 64Mx32 SDRAM 256MB 100MHz CL2 nonecc Unbuffered Assembled in Japan S/N: ****** (14/15)

15 10. Revision History Rev. Date Changes Issued 01 Jun T.Kotegawa Changed D.C.Characters I CC2NS 112mA 160mA I CC3NS 200mA 240mA I OH -4mA -2mA I OL 4mA 2mA 02 Jan Changed A.C.Timing Characters t OH 3.0ns 2.7ns S.Fukui(A11) Changed SPD Data Value (No Manufacturing Data:00 Undefined Value) (No Assembly Serial Number:00 Undefined Value) (No Manufacturer Specific Data:00 Undefined Value) (No.128+ Unused storage locations:00 Undefined Value) 03 Nov Corrected error on Module label M.Goto(A13) (15/15)