Product Specification

Transcription

1 General Information VL466S285CC-GA/GH/GL 1GB 128Mx64 SDRAM PC100/PC1 SODIMM WITH CONFORMAL COATING Description: The VL466S285CC is a 128M x 64 Synchronous Dynamic RAM high deity memory module. This memory module coists of thirty-two CMOS 2Mx8 bits with 4 banks Synchronous DRAMs intsop-ii package and a 2K EEPROM in 8-pin TSSOP package. This module is a 144-pin stacked PCB Dual-In line-memory Module and is intended for mounting into a connector socket. Decoupling capacitors are mounted on the printed circuit board for each SDRAM. Features: Unbuffered 8 byte SDRAM 144pin SODIMM High Speed - 100MHz/1MHz CL2/CL Burst Mode Operation Auto & Self refresh Capability (4096 Cycles/64ms) LVTTL compatible inputs and outputs Single.V ±0. V power supply 1/10/2 Addressing (Row/Column/Bank) MRS cycle with address key programs EPROM Serial Presence Detect Gold (Au) contacts Stacked PCB Conformal coating Pin A0-A12 BA0, BA1 Name - CLK0 0 ~ 0 ~ RAS CAS Function Address inputs Bank Select Address Data Input/Outpu t Clock Inpu t Clock Enable Inp ut Chip Select Inpu t Row Address Strobe Column Address Inpu t WE DM0-DM7 VDD VSS Write Enable Data Mask Power Supply Ground Order Information: VL466S285CC-GA S X DRAM DIE (Option) DRAM MANUFACTURER S -SAMSUNG MODULE SPEED GA: CL GH: CL2 GL: CL CC: Conformal coating VL: Lead-free/RoHS * VREF Power Supply for Referenc e SDA SCL NC Serial Data Input/Outpu t SPD Clock Inpu t No Connect * These pi are not used in this module. Page 1 of 8

2 Pin Configuration Pin Front Number Side 1 VSS DQ 11 VDD VSS VDD 29 A0 1 A1 A2 5 VSS 7 DQ8 9 DQ VDD VSS 57 NC 59 NC 61 CLK0 6 VDD 65 RAS 67 WE Pin Back Number Side 2 VSS 4 6 DQ 8 10 DQ5 12 VDD 14 DQ6 16 DQ7 18 DQ8 20 DQ9 22 VSS VDD 0 A 2 A4 4 A5 6 VSS VDD VSS 58 NC 60 NC VDD 66 CAS A12 72 NC Pin Front Number Side 7 DU 75 VSS VDD VSS ` VDD 10 A6 105 A8 107 VSS 109 A9 111 A10/AP 11 VDD VSS VDD DQ VSS 141 SDA 14 VDD Pin Back Number Side 74 *CLK1 76 VSS VDD VSS VDD 104 A7 106 BA0 108 VSS 110 BA1 112 A VDD VSS VDD VSS 142 SCL 144 VDD * These pi are not used in this module. Page 2 of 8

3 Functional Block Diagram R R4 R2 R1 R5 NOTE: R1,R2,R = 0 Ohm: Enables all 4 R4,R5 = 0 Ohm: Enables only 0 & DQ DQ U1 DQ DQ U9 DQ DQ U17 DQ DQ U DQ8 DQ8 DQ8 DQ8 DQ9 DQ9 DQ9 DQ DQ U2 1 DQ U10 1 DQ U18 1 DQ U DQ U 9 DQ U11 9 DQ U19 9 DQ U DQ U4 7 DQ U12 7 DQ U20 7 DQ U DQ0 DQ0 DQ0 DQ DQ DQ DQ DQ DQ5 DQ U5 DQ5 DQ U1 DQ5 DQ U21 DQ5 DQ U29 DQ6 DQ6 DQ6 DQ6 DQ7 DQ7 DQ7 DQ7 DQ8 DQ8 DQ8 DQ8 DQ9 DQ9 DQ9 DQ DQ U6 DQ U14 DQ U22 DQ U DQ U7 1 DQ U15 1 DQ U2 1 DQ U DQ U8 9 DQ U DQ U DQ U2 A0 ~ A12, BA0 ~ 1 RAS CAS WE DQn 10 Ohm SDRAM U1 ~ U2 CLK0 SDRAM U1 ~ U2 SDRAM U1 ~ U2 SDRAM U1 ~ U2 Every DQ pin of SDRAM 10 Ohm 12 CLK IY0 IY1 IY2 CDCF IY 2510 IY4 IY5 IY6 IY7 FIBIN FBOUT SDRAM U1,U2,U9,U10 SDRAM U,U4,U11,U12 SDRAM U5,U6,U1,U14 SDRAM U7,U8,U15,U16 SDRAM U17,U18,U25,U26 SDRAM U19,U20,U27,U28 SDRAM U21,U22,U29,U0 SDRAM U2,U24,U1,U2 SERIAL PD SCL WP SA0 SA1 SA2 47 KOhm SDA Two 0.1uF 060 Capacitors per each SDRAM To all SDRAMs The actual cap values will depend upon the PLL chosen Page of 8

4 Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V Voltage on V DD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V Storage temperature TSTG -55 ~ +150 C Power dissipation PD 2 W Short circuit current IOS 50 ma Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Recommended DC Operating Conditio (T A = 0 C to +70 C) Parameter Symbol Min Typ Max Unit Note Supply voltage VDD.0..6 V Input high voltage VIH VDDQ+0. V 1 Input low voltage VIL V 2 Output high voltage VOH V IOH = -2mA Output low voltage VOL V IOL = 2mA Input leakage current (Inputs) IIL ua Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is.. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. Capacitance (T A =25, f=1mhz, V DD =.V) Pin Symbol Min Max Unit Address (A0 ~ A12, BA0 ~ BA1) RAS, CAS, WE CADD CIN (0 ~ ) Clock (CLK0) (0 ~ ) C CCLK C (0 ~ 7) DQ ( ~ ) C COUT Page 4 of 8

5 DC Characteristics (Recommended operating condition unless otherwise noted, TA = 0 to 70 C) Value Parameter Symbol Test Condition -GA -GH -GL Unit Note Operating current (One bank active) ICC1 Burst length = 1 trc trc(min) IO = 0 ma ma 1 Precharge standby current in power-down mode Precharge standby current in non power-down mode ICC2P VIL(max), tcc = 10 2 ICC2PS & CLK VIL(max), tcc = 2 ICC2N ICC2NS VIH(min), VIH(min), tcc = 10 Input signals are changed one time during 20 VIH(min), CLK VIL(max), tcc = Input signals are stable ma ma Active standby current in power-down mode Active standby current in non power-down mode (One bank active) ICCP VIL(max), tcc = ICCPS & CLK VIL(max), tcc = 80 ICCN ICCNS VIH(min), VIH(min), tcc = 10 Input signals are changed one time during 20 VIH(min), CLK VIL(max), tcc = Input signals are stable ma 480 ma 400 ma Operating current (Burst mode) ICC4 IO = 0 ma Page burst 4Banks activated tccd = 2CLKs ma 1 Refresh current ICC5 trc trc(min) ma 2 Self refresh current ICC6 0.2V 2 ma Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. Page 5 of 8

6 0 AC Operating Test Conditio (Vdd=.v, 0-70 C) Parameter Value Unit AC input levels (Vih/Vil) 2.4/0.4 V Input timing measurement reference level 1.4 V Input rise and fall time tr/tf = 1/1 Output timing measurement reference level 1.4 V Output load condition See Fig. 2.V Vtt = 1.4V 1200Ω 50Ω Output VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50Ω 870Ω (Fig. 1) DC output load circuit Operating AC Parameter (Fig. 2) AC output load circuit Parameter Symbol Version Row active to row active delay trrd(min) RAS to CAS delay trcd(min) Row precharge time trp(min) tras(min) Row active time 1 tras(max) 100 us Row cycle time trc(min) Last data in to row precharge trdl(min) 2 CLK 2 Last data in to Active delay tdal(min) 2 CLK Last data in to new col. address delay tcdl(min) 1 CLK 2 Last data in to burst stop tbdl(min) 1 CLK 2 Col. address to col. address delay tccd(min) 1 CLK Number of valid output data Notes : CAS latency= 2 CAS latency=2 1 -GL Unit Note ea 4 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write.. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. -GA -GH Page 6 of 8

7 Operating AC Parameters Parameter Symbol Min GA Max Unit Note CLK cycle time CAS latency = tcc CAS latency = CLK to valid output delay CAS latency = tsac CAS latency = , 2 Output data hold time CAS latency = toh CAS latency = 2-2 CLK high pulse width CLK low pulse width Input setup time Input hold time tch 2. 5 tcl 2. 5 tss 1. 5 tsh 0. 8 CLK to output in Low-Z tslz 1 2 CLK to output in Hi-z CAS latency = tshz CAS latency = Notes: 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1, (tr/2-0.5) should. Assumed input rise and fall time (tr & tf) = 1. if tr & tf is longer than 1, traient timecompeation should i.e.,[(tr + tf)/2-1] should be added to the parameter. be added to the parameter. be coidered, Page 7 of 8

8 Package Dimeio Units : Inches (Millimeters) 2.66 (67.60) 2.50 (6.60) 2-R Min (2.00 Min) 0.16 ± 0.09 (4.00 ± 0.10) 0.24 (6.0) 0.79 (20.00) (29.21) 0.1 (.0) 0.15 (.70) 0.91 (2.20) 0.10 (2.50) 0.18 (4.60) 0.08 (2.10) Z 1.29 (2.80) Y (1.80) Min (4.00 Min) Max (7.112 Max) ± (1.016 ± 0.10) Detail Z 0.06 ± (1.50 ± 0.1) 0.16 ± (4.00 ± 0.10) 0.10 Min (2.55 Min) 0.0 TYP (0.80 TYP) Detail Y ± (0.60 ± 0.05) 0.01 Max (0.25 Max) Tolerances : ±.005(.1) unless otherwise specified Page 8 of 8