SPI Serial EEPROMs 8K (1024 x 8) 16K (2048 x 8) 32K (4096 x 8) 64K (8192 x 8) AT25080 AT25160 AT25320 AT25640

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1 Features Serial Peripheral Interface (SPI) Compatible Supports SPI Modes (,) and 3 (1,1) Low-voltage and Standard-voltage Operation.7 (V CC =.7V to 5.5V) 1.8 (V CC = 1.8V to 5.5V) 3. MHz Clock Rate (5V) 3-byte Page Mode Block Write Protection Protect 1/4, 1/, or Entire Array Write Protect (WP) Pin and Write Disable Itructio for both Hardware and Software Data Protection Self-timed Write Cycle (5 ms Typical) High-reliability Endurance: One Million Write Cycles Data Retention: 1 Years Automotive Grade Devices Available 8-lead PDIP, 8-lead JEDEC SOIC and 14-lead TSSOP Packages Description The AT58/16/3/64 provides 819/16384/3768/65536 bits of serial electrically-erasable programmable read only memory (EEPROM) organized as 14/48/496/819 words of 8 bits each. The device is optimized for use in many industrial and commercial applicatio where low-power and low-voltage operation are essential. The AT58/16/3/64 is available in space saving 8-lead PDIP, 8- lead JEDEC SOIC and 14-lead TSSOP packages. The AT58/16/3/64 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface coisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate ERASE cycle is required before WRITE. SPI Serial EEPROMs 8K (14 x 8) 16K (48 x 8) 3K (496 x 8) 64K (819 x 8) AT58 AT516 AT53 AT564 Pin Configuration 8-lead PDIP Pin Name CS SCK Function Chip Select Serial Data Clock CS SO WP GND VCC HOLD SCK SI SI Serial Data Input 8-lead SOIC SO GND VCC Serial Data Output Ground Power Supply CS SO WP GND VCC HOLD SCK SI WP HOLD NC DC Write Protect Suspends Serial Input No Connect Don t Connect CS SO NC NC NC WP GND 14-lead TSSOP VCC HOLD NC NC NC SCK SI 1

2 BLOCK WRITE protection is enabled by programming the status register with one of four blocks of write protection. Separate program enable and program disable itructio are provided for additional data protection. Hardware data protection is provided via the WP pin to protect agait inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Absolute Maximum Ratings* Operating Temperature C to +15 C Storage Temperature C to +15 C Voltage on Any Pin with Respect to Ground...-1.V to +7.V Maximum Operating Voltage V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio beyond those indicated in the operational sectio of this specification is not implied. Exposure to absolute maximum rating conditio for extended periods may affect device reliability. DC Output Current ma Block Diagram AT58/16/3/64

3 AT58/16/3/64 Pin Capacitance (1) Applicable over recommended operating range from T A = 5 C, f = 1. MHz, V CC = +5.V (unless otherwise noted). Symbol Test Conditio Max Units Conditio C OUT Output Capacitance (SO) 8 pf V OUT = V C IN Input Capacitance(CS, SCK, SI, WP, HOLD) 6 pf V IN = V Note: 1. This parameter is characterized and is not 1% tested. DC Characteristics (1) Applicable over recommended operating range from: T AI = -4 C to +85 C, V CC = +1.8V to +5.5V, V CC = +1.8V to +5.5V (unless otherwise noted). Symbol Parameter Test Condition Min Typ Max Units V CC1 Supply Voltage V V CC Supply Voltage V V CC3 Supply Voltage V I CC1 Supply Current V CC = 5.V at 1 MHz, SO = Open, Read 3. ma V I CC Supply Current CC = 5.V at MHz, SO = Open, 5. ma Read, Write I SB1 Standby Current V CC = 1.8V, CS = V CC.1 1. µa I SB Standby Current V CC =.7V, CS = V CC.. µa I SB3 Standby Current V CC = 5.V, CS = V CC. 5. µa I IL Input Leakage V IN = V to V CC -3. µa I OL Output Leakage V IN = V to V CC, T AC = C to 7 C µa V IL (1) V IH (1) Input Low-voltage -.6 V CC x.3 V Input High-voltage V CC x.7 V CC +.5 V V OL1 Output Low-voltage I OL = 3. ma.4 V 4.5V V CC 5.5V V OH1 Output High-voltage I OH = -1.6 ma V CC -.8 V V OL Output Low-voltage I OL =.15 ma. V 1.8V V CC 3.6V V OH Output High-voltage I OH = -1 µa V CC -. V Note: 1. V IL min and V IH max are reference only and are not tested. 3

4 AC Characteristics Applicable over recommended operating range from T AI = -4 C to +85 C, V CC = As Specified, CL = 1 TTL Gate and 1 pf (unless otherwise noted). Symbol Parameter Voltage Min Max Units f SCK SCK Clock Frequency MHz t RI Input Rise Time µs t FI Input Fall Time µs t WH SCK High Time t WL SCK Low Time t CS CS High Time t CSS CS Setup Time t CSH CS Hold Time t SU Data In Setup Time t H Data In Hold Time t HD Hold Setup Time t CD Hold Hold Time 4 t V Output Valid t HO Output Hold Time 4 AT58/16/3/64

5 AT58/16/3/64 AC Characteristics (Continued) Applicable over recommended operating range from T AI = -4 C to +85 C, V CC = As Specified, CL = 1 TTL Gate and 1 pf (unless otherwise noted). Symbol Parameter Voltage Min Max Units t LZ t HZ t DIS t WC Hold to Output Low Z Hold to Output High Z Output Disable Time Write Cycle Time Note: 1. This parameter is characterized and is not 1% tested. Endurance (1) 5.V, 5 C, Page Mode 1M Write Cycles ms 5

6 Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT58/16/3/64 always operates as a slave. TRANSMITTER/RECEIVER: The AT58/16/3/64 has separate pi designated for data tramission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit tramitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contai the op-code that defines the operatio to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT58/16/3/64, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT58/16/3/64 is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT58/16/3/64. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operatio when held high. When the WP pin is brought low and WPEN bit is 1, all write operatio to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is. This will allow the user to itall the AT58/16/3/64 in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functio are enabled when the WPEN bit is set to 1. 6 AT58/16/3/64

7 AT58/16/3/64 SPI Serial Interface 7

8 Functional Description The AT58/16/3/64 is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 685 and 68HC11 series of microcontrollers. The AT58/16/3/64 utilizes an 8-bit itruction register. The list of itructio and their operation codes are contained in Table 1. All itructio, addresses, and data are traferred with the MSB first and start with a high-to-low CS traition. Table 1. Itruction Set for the AT58/16/3/64 Itruction Name Itruction Format Operation WREN X11 Set Write Enable Latch WRDI X1 Reset Write Enable Latch RDSR X11 Read Status Register WRSR X1 Write Status Register READ X11 Read Data from Memory Array WRITE X1 Write Data to Memory Array WRITE ENABLE (WREN): The device will power-up in the write disable state when V CC is applied. All programming itructio must therefore be preceded by a Write Enable itruction. WRITE DISABLE (WRDI): To protect the device agait inadvertent writes, the Write Disable itruction disables all programming modes. The WRDI itruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register itruction provides access to the status register. The READY/BUSY and Write Enable status of the device can be determined by the RDSR itruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR itruction. Table. Status Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit Bit 1 Bit WPEN X X X BP1 BP WEN RDY Table 3. Read Status Register Bit Definition Bit Bit (RDY) Bit 1 (WEN) Definition Bit = (RDY) indicates the device is READY. Bit = 1 indicates the write cycle is in progress. Bit 1= indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates the device is WRITE ENABLED. Bit (BP) See Table 4 on page 9. Bit 3 (BP1) See Table 4 on page 9. Bits 4-6 are s when device is not in an internal write cycle. Bit 7 (WPEN) See Table 5 on page 9. Bits - 7 are 1s during an internal write cycle. 8 AT58/16/3/64

9 AT58/16/3/64 WRITE STATUS REGISTER (WRSR): The WRSR itruction allows the user to select one of four levels of protection. The AT58/16/3/64 is divided into four array segments. One quarter (1/4), one half (1/), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be READ only. The block write protection levels and corresponding status register control bits are shown in Table 4. The three bits, BP, BP1, and WPEN are nonvolatile cells that have the same properties and functio as the regular memory cells (e.g. WREN, t WC, RDSR). Table 4. Block Write Protect Bits Level Status Register Bits Array Addresses Protected BP1 BP AT58 AT516 AT53 AT564 None None None None 1(1/4) 1 (1/) 1 3(All) FF 6-7FF C -FFF 18-1FFF The WRSR itruction also allows the user to enable or disable the write protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is 1. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is. When the device is hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the blockprotected sectio in the memory array are disabled. Writes are only allowed to sectio of the memory which are not block-protected. NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to, as long as the WP pin is held low. Table 5. WPEN Operation WPEN WP WEN -3FF -3FF Protected Blocks 4-7FF -7FF 8 -FFF -FFF Unprotected Blocks 1-1FFF -1FFF Status Register X Protected Protected Protected X 1 Protected Writable Writable 1 Low Protected Protected Protected 1 Low 1 Protected Writable Protected X High Protected Protected Protected X High 1 Protected Writable Writable 9

10 READ SEQUENCE (READ): Reading the AT58/16/3/64 via the SO (Serial Output) pin requires the following sequence. After the CS line is pulled low to select a device, the READ op-code is tramitted via the SI line followed by the byte address to be read (A15 - A, Refer to Table 6). Upon completion, any data on the SI line will be ignored. The data (D7 - D) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The READ sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous READ cycle. WRITE SEQUENCE (WRITE): In order to program the AT58/16/3/64, two separate itructio must be executed. First, the device must be write enabled via the Write Enable (WREN) Itruction. Then a Write (WRITE) Itruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the Block Write Protection Level. During an internal write cycle, all commands will be ignored except the RDSR itruction. A Write Itruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE op-code is tramitted via the SI line followed by the byte address (A15 - A) and the data (D7 - D) to be programmed (Refer to Table 6). Programming will start after the CS pin is brought high. (The LOW-to-High traition of the CS pin must occur during the SCK low-time immediately after clocking in the D (LSB) data bit. The READY/BUSY status of the device can be determined by initiating a READ STATUS REGISTER (RDSR) Itruction. If Bit = 1, the WRITE cycle is still in progress. If Bit =, the WRITE cycle has ended. Only the READ STATUS REGISTER itruction is enabled during the WRITE programming cycle. The AT58/16/3/64 is capable of a 3-byte PAGE WRITE operation. After each byte of data is received, the five low order address bits are internally incremented by one; the high order bits of the address will remain cotant. If more than 3 bytes of data are tramitted, the address counter will roll over and the previously written data will be overwritten. The AT58/16/3/64 is automatically returned to the write disable state at the completion of a WRITE cycle. NOTE: If the device is not Write enabled (WREN), the device will ignore the Write itruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to re-initiate the serial communication. Table 6. Address Key Address AT58 AT516 AT53 AT564 A N A 9 - A A 1 - A A 11 - A A 1 - A Don't Care Bits A 15 - A 1 A 15 - A 11 A 15 - A 1 A 15 - A 13 1 AT58/16/3/64

11 AT58/16/3/64 Timing Diagrams Synchronous Data Timing (for Mode ) t CS CS V IH V IL tcss t CSH SCK V IH t WH t WL V IL t SU t H SI V IH V IL VALID IN t V t HO t DIS SO V OH HI-Z HI-Z V OL WREN Timing WRDI Timing 11

12 RDSR Timing CS SCK SI INSTRUCTION DATA OUT HIGH IMPEDANCE SO MSB WRSR Timing CS SCK SI INSTRUCTION DATA IN SO HIGH IMPEDANCE READ Timing CS SCK SI INSTRUCTION BYTE ADDRESS SO HIGH IMPEDANCE 7 MSB 6 DATA OUT AT58/16/3/64

13 AT58/16/3/64 WRITE Timing CS SCK SI INSTRUCTION BYTE ADDRESS DATA IN SO HIGH IMPEDANCE HOLD Timing CS t CD t CD SCK t HD HO LD t HD t HZ SO t LZ 13

14 AT58 Ordering Information Ordering Code Package Operation Range AT58-1PI-.7 Industrial AT58N-1SI-.7 (-4 C to 85 C) AT58T1-1TI-.7 14A AT58-1PI-1.8 Industrial AT58N-1SI-1.8 (-4 C to 85 C) AT58T1-1TI A Note: For.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables. Package Type 14A 8-lead,.3" Wide, Plastic Dual Inline Package (PDIP) 8-lead,.15" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 14-lead,.17" Wide, Thin Shrink Small Outline Package (TSSOP) Optio -.7 Low Voltage (.7V to 5.5V) -1.8 Low Voltage (1.8V to 5.5V) 14 AT58/16/3/64

15 AT58/16/3/64 AT516 Ordering Information Ordering Code Package Operation Range AT516-1PI-.7 Industrial AT516N-1SI-.7 (-4 C to 85 C) AT516T1-1TI-.7 14A AT516-1PI-1.8 Industrial AT516N-1SI-1.8 (-4 C to 85 C) AT516T1-1TI A Note: For.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables. Package Type 14A 8-lead,.3" Wide, Plastic Dual Inline Package (PDIP) 8-lead,.15" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 14-lead,.17" Wide, Thin Shrink Small Outline Package (TSSOP) Optio -.7 Low Voltage (.7V to 5.5V) -1.8 Low Voltage (1.8V to 5.5V) 15

16 AT53 Ordering Information Ordering Code Package Operation Range AT53-1PI-.7 Industrial AT53N-1SI-.7 (-4 C to 85 C) AT53T1-1TI-.7 14A Note: For.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables. Package Type 14A 8-lead,.3" Wide, Plastic Dual Inline Package (PDIP) 8-lead,.15" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 14-lead,.17" Wide, Thin Shrink Small Outline Package (TSSOP) Optio -.7 Low Voltage (.7V to 5.5V) 16 AT58/16/3/64

17 AT58/16/3/64 AT564 Ordering Information Ordering Code Package Operation Range AT564-1PI-.7 Industrial AT564N-1SI-.7 (-4 C to 85 C) AT564T1-1TI-.7 14A AT564-1PI-1.8 Industrial AT564N-1SI-1.8 (-4 C to 85 C) AT564T1-1TI A Note: For.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables. Package Type 14A 8-lead,.3" Wide, Plastic Dual Inline Package (PDIP) 8-lead,.15" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 14-lead,.17" Wide, Thin Shrink Small Outline Package (TSSOP) Optio -.7 Low Voltage (.7V to 5.5V) -1.8 Low Voltage (1.8V to 5.5V) 17

18 Packaging Information PDIP 1 E E1 N Top View c ea End View D1 D e A A COMMON DIMENSIONS (Unit of Measure = inches) SYMBOL MIN NOM MAX NOTE A.1 A b b b c b3 4 PLCS b b L D D1.5 3 E E Side View e.1 BSC ea.3 BSC 4 L Notes: R 1. This drawing is for general information only; refer to JEDEC Drawing MS-1, Variation BA for additional information.. Dimeio A and L are measured with the package seated in JEDEC seating plane Gauge GS D, D1 and E1 dimeio do not include mold Flash or protrusio. Mold Flash or protrusio shall not exceed.1 inch. 4. E and ea measured with the leads cotrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease iertion. 6. b and b3 maximum dimeio do not include Dambar protrusio. Dambar protrusio shall not exceed.1 (.5 mm). 35 Orchard Parkway San Jose, CA TITLE, 8-lead,.3" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 1/9/ REV. B 18 AT58/16/3/64

19 AT58/16/3/64 JEDEC SOIC C 1 E E1 N L Top View End View e B A COMMON DIMENSIONS (Unit of Measure = mm) D Side View A1 SYMBOL MIN NOM MAX NOTE A A1.1.5 b C.17.5 D E E e 1.7 BSC L Note: These drawings are for general information only. Refer to JEDEC Drawing MS-1, Variation AA for proper dimeio, tolerances, datums, etc. 1/7/3 R 115 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 896 TITLE, 8-lead (.15" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. REV. B 19

20 14A TSSOP b L L1 E E1 End View e COMMON DIMENSIONS (Unit of Measure = mm) Top View SYMBOL MIN NOM MAX NOTE D , 5 A D A E 6.4 BSC E , 5 A 1. A b Side View e.65 BSC L L1 1. REF Notes: 1. This drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation AB-1, for additional information.. Dimeion D does not include mold Flash, protrusio or gate burrs. Mold Flash, protrusio and gate burrs shall not exceed.15 mm (.6 in) per side. 3. Dimeion E1 does not include inter-lead Flash or protrusio. Inter-lead Flash and protrusio shall not exceed.5 mm (.1 in) per side. 4. Dimeion b does not include Dambar protrusion. Allowable Dambar protrusion shall be.8 mm total in excess of the b dimeion at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is.7 mm. 5. Dimeion D and E1 to be determined at Datum Plane H. 1/8/1 R 35 Orchard Parkway San Jose, CA TITLE 14A,14-lead (4.4 x 5 mm Body),.65 Pitch, Thin Shrink Small Outline Package (TSSOP) DRAWING NO. 14A REV. A AT58/16/3/64

21 Atmel Corporation 35 Orchard Parkway San Jose, CA 95131, USA Tel: 1(48) Fax: 1(48) Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 8 CH-175 Fribourg Switzerland Tel: (41) Fax: (41) Asia Room 119 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (85) Fax: (85) Japan 9F, Tonetsu Shinkawa Bldg Shinkawa Chuo-ku, Tokyo Japan Tel: (81) Fax: (81) Atmel Operatio Memory 35 Orchard Parkway San Jose, CA 95131, USA Tel: 1(48) Fax: 1(48) Microcontrollers 35 Orchard Parkway San Jose, CA 95131, USA Tel: 1(48) Fax: 1(48) La Chantrerie BP Nantes Cedex 3, France Tel: (33) Fax: (33) ASIC/ASSP/Smart Cards Zone Industrielle 1316 Rousset Cedex, France Tel: (33) Fax: (33) East Cheyenne Mtn. Blvd. Colorado Springs, CO 896, USA Tel: 1(719) Fax: 1(719) Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 QR, Scotland Tel: (44) Fax: (44) RF/Automotive Theresietrasse Postfach Heilbronn, Germany Tel: (49) Fax: (49) East Cheyenne Mtn. Blvd. Colorado Springs, CO 896, USA Tel: 1(719) Fax: 1(719) Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP Saint-Egreve Cedex, France Tel: (33) Fax: (33) Literature Requests Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company s standard warranty which is detailed in Atmel s Terms and Conditio located on the Company s web site. The Company assumes no respoibility for any errors which may appear in this document, reserves the right to change devices or specificatio detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licees to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel s products are not authorized for use as critical components in life support devices or systems. Atmel Corporation 3. All rights reserved. Atmel and combinatio thereof, are the registered trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be the trademarks of others. Printed on recycled paper. xm

22 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Atmel: AT516N-1SC-.7 AT58N-1SC-.7 AT53N-1SI AT58N-1SI AT516N-1SI-.7 AT564N-1SC-.7 AT564N-1SI-.7

SPI Serial EEPROMs AT25010 AT25020 AT SPI, 1K Serial E 2 PROM

SPI Serial EEPROMs AT25010 AT25020 AT SPI, 1K Serial E 2 PROM Features Serial Peripheral Interface (SPI) Compatible Supports SPI Modes (,) and 3 (1,1) Low-voltage and Standard-voltage Operation 5. (V CC = 4.5V to 5.5V) 2.7 (V CC = 2.7V to 5.5V) 3. MHz Clock Rate