CMOS 8-BIT SINGLE CHIP MICROCOMPUTER S1C Technical Manual. S1C88655 Technical Hardware

Transcription

1 CMOS 8-BIT SINGLE CHIP MICOCOMPUTE SC88655 Technical Manual SC88655 Technical Hardware

2 NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. SEIKO EPSON COPOATION 26, All rights reserved.

3 Configuration of product number Devices S C 884 F A Packing specifications : Besides tape & reel A : TCP BL 2 directions B : Tape & reel BACK C : TCP B 2 directions D : TCP BT 2 directions E : TCP BD 2 directions F : Tape & reel FONT G : TCP BT 4 directions H : TCP BD 4 directions J : TCP SL 2 directions K : TCP S 2 directions L : Tape & reel LEFT M : TCP ST 2 directions N : TCP SD 2 directions P : TCP ST 4 directions Q : TCP SD 4 directions : Tape & reel IGHT 99 : Specs not fixed Specification Package D: die form; F: QFP, B: BGA Model number Model name C: microcomputer, digital products Product classification S: semiconductor Development tools S5U C D Packing specifications : standard packing Version : Version Tool type Hx : ICE Ex : EVA board Px : Peripheral board Wx : Flash OM writer for the microcomputer Xx : OM writer peripheral board Cx : C compiler package Ax : Assembler package Dx : Utility tool by the model Qx : Soft simulator Corresponding model number 88348: for SC88348 Tool classification C: microcomputer use Product classification S5U: development tool for semiconductor products

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5 CONTENTS Contents INTODUCTION.... Features....2 Block Diagram Pad Layout Diagram of pad layout Pad coordinates Pad description Mask Option CPU Core CPU CPU model CC (customized condition flag) MCU Mode and MPU Mode MCU mode MPU mode Mask option MEMOY MAP MCU Single Chip Mode MCU Expansion Mode MPU Expansion Mode Internal Memory Program OM AM Display data AM Font data OM I/O Memory POWE SUPPLY Operating Voltage Internal Power Supply Circuit VD voltage generator Supply voltage booster circuit VC5 voltage generator VC4 voltage generator LCD drive power supply circuit control procedure Details of Control egisters Precautions INITIAL ESET Configuration of Initial eset Circuit ESET terminal eset voltage detector (VD) Watchdog timer overflow signal Initial reset sequence Initial Settings After Initial eset...34 SC88655 TECHNICAL MANUAL EPSON i

6 CONTENTS 6 SYSTEM CONTOLLE AND BUS CONTOL Configuration of External Bus Bus Mode and CPU Mode Bus mode CPU mode Address Decoder (CE) Settings WAIT State Settings Setting Bus Authority elease equest Signal Stack Page Setting Details of Control egisters Precautions INTEUPT AND STANDBY STATUS Interrupt Generation Conditions Interrupt Factor Flag Interrupt Enable egister Interrupt Priority egister and Interrupt Priority Level Exception Processing Vectors Details of Control egisters Precautions OSCILLATION CICUITS Configuration of Oscillation Circuits Mask Option OSC3 Oscillation Circuit OSC Oscillation Circuit Switching the CPU Clock Clock Output (FOUT) Details of Control egisters Precautions OUTPUT POTS ( POTS) Configuration of Output Ports High Impedance Control DC Output Details of Control egisters...62 I/O POTS (P POTS) Configuration of I/O Ports Mask Option Input/Output Mode Pull-up Control Interrupt Function Details of Control egisters Precautions...72 ii EPSON SC88655 TECHNICAL MANUAL

7 CONTENTS SEIAL INTEFACE Configuration of Serial Interface Switching Terminal Functions Transfer Modes Clock Source Transmit/eceive Control Operation of Clock Synchronous Transfer Operation of Asynchronous Transfer Interrupt Function Details of Control egisters Precautions CLOCK TIME Configuration of Clock Timer Interrupt Function Details of Control egisters Precautions POGAMMABLE TIME Configuration of Programmable Timer Operation Mode Setting of Input Clock Operation and Control of Timer Interrupt Function Setting TOUT Outputs Setting Transfer ate of Serial Interface Setting Clock for LCD Driver Display Timing Generator Details of Control egister Precautions WATCHDOG TIME Configuration of Watchdog Timer Mask Option Details of Control egister Precautions LCD DIVE Configuration of LCD Driver LCD Power Supply Display Timing Generator Generating frame signal CL, F signal outputs Display Data AM Display Control Details of Control egisters Precautions...27 SC88655 TECHNICAL MANUAL EPSON iii

8 CONTENTS 6 SUPPLY VOLTAGE DETECTION (SVD) CICUIT Configuration of SVD Circuit SVD Operation Details of Control egister Precautions SUMMAY OF NOTES Notes for Low Current Consumption Precautions on Mounting BASIC EXTENAL WIING DIAGAM ELECTICAL CHAACTEISTICS Absolute Maximum ating ecommended Operating Conditions DC Characteristics Analog Circuit Characteristics Power Current Consumption AC Characteristics Oscillation Characteristics Characteristics Curves (reference value) PACKAGE FO TEST SAMPLES... 5 APPENDIX A PEIPHEAL CICUIT BOAD FO SC88655 (S5UC88P + S5UC88655P2 + S5UC88655T) A. Names and Functions of Each Part...53 A.2 Installation...56 A.2. Installing S5UC88655P2 to S5UC88P A.2.2 Installing into the ICE (S5UC88H5) A.3 Connecting to the Target System...56 A.4 Downloading Circuit Data to the S5UC88P...58 A.5 Precautions...58 A.5. Precaution for operation A.5.2 Differences from actual IC A.6 Product Specifications...6 A.6. S5UC88P specifications... 6 A.6.2 S5UC88655P2 specifications... 6 A.6.3 S5UC88655T specifications... 6 APPENDIX B USING FONT DATA APPENDIX C TCM iv EPSON SC88655 TECHNICAL MANUAL

9 INTODUCTION The SC88655 is an 8-bit microcomputer for portable equipment with an LCD display that has a built-in LCD controller/driver and a font data OM. The LCD controller/driver contains an LCD drive power supply circuit and can drive a maximum of dot LCD panel. The SC88655 has a builtin large-capacity OM that can store various font data*. This microcomputer features low-voltage (.8 V) and high-speed (8.2 MHz) operations as well as low-current consumption, for instance, 2 µa in standby mode (HALT mode with 32-kHz crystal oscillation). INTODUCTION The SC88655 is suitable for display modules such as PDAs and data banks that require a generalpurpose LCD driver in conventional systems as well as portable CD/MD players and solid audio equipment with low-power and a small-footprint. Fonts supported ) 2 2-dot Japanese font (JIS level- and level-2, other characters) 2) 2 2-dot Korean font (KSX) Please contact Seiko Epson for more information on the fonts provided.. Features Table.. lists the features of the SC Table.. Main features Core CPU Main (OSC3) oscillation circuit SC88 (MODEL3) CMOS 8-bit core CPU Crystal oscillation circuit/ceramic oscillation circuit 8.2 MHz (Max.), or C oscillation circuit 2.2 MHz (Max.) Sub (OSC) oscillation circuit Crystal oscillation circuit khz (Typ.), or C oscillation circuit 2 khz (Max.) Instruction set 68 types (usable for multiplication and division instructions) Min. instruction execution time.244 µsec/8.2 MHz (2 clock) Internal OM capacity 48K bytes/program OM 52K bytes/font data OM Can be used for a program and data OM when no font data is stored. Internal AM capacity 8K bytes/am 2K bytes/display data AM (892 bits per screen 2) Bus line Address bus: 2 bits Data bus: 8 bits CE signal: 4 bits (MB addressing range 4) W signal: bit D signal: bit Output port I/O port Serial interface Timer LCD driver Watchdog timer Supply voltage detection (SVD) circuit eset voltage detection (VD) circuit Interrupt Supply voltage Current consumption Supply form These pins can be used as general-purpose ports when not used for the bus. 3 bits (when the external bus is used) 26 bits (when the external bus is not used) 6 bits (when the external bus is used) CMOS or Schmitt inputs 24 bits (when the external bus is not used) With or without pull-up resistors 2 channels Clock synchronous system or asynchronous system is selectable. Programmable timer: 4 channels of 6-bit (8-bit 2) timers (with PWM waveform, SIF and LCD driver clock output functions) Clock timer: channel Dot matrix type, 28 segments 64 commons Built-in LCD power supply circuit that multiplies the source voltage by a factor of 2, 3, 4, or 5 Overflow cycle ( to 4 seconds) and output signal (NMI or reset) are selectable 3 values programmable (.82.7 V) Supply voltage level reset (.6 V, power-on reset function) with enable/disable option External interrupt: Input interrupt (with noise rejector) system (8 types) Internal interrupt: Timer interrupt 5 systems (2 types) Serial interface interrupt 2 systems (6 types).83.6 V (internal voltage VD =.8 V) SLEEP mode:.7 µa (Typ.) HALT mode: 2 µa (Typ.) 32 khz OSC crystal, LCD OFF 7 µa (Typ.) 32 khz OSC C, LCD OFF un mode: 5 µa (Typ.) 32 khz OSC crystal, LCD OFF 35 µa (Typ.) 2 MHz OSC3 C, LCD OFF 8 µa (Typ.) 8 MHz OSC3 ceramic, LCD OFF VD circuit operating current:.5 µa (Typ.) VDD = 3.6 V SVD circuit operating current: 5 µa (Typ.) VDD = 3.6 V LCD driver circuit operating current: 5 µa (Typ.) VDD = 3. V, OSC = 32 khz, triple boosted, VC5 = 8 V, white screen displayed 2 µa (Typ.) VDD = 3. V, OSC = 32 khz, triple boosted, VC5 = 8 V, checker pattern displayed AU-bump chip or TCM 2 Selectable by mask option 2 TCM (Tape Carrier Module): FPC (Flexible Printed Circuit) modules that include peripheral circuit parts as well as the IC main unit SC88655 TECHNICAL MANUAL EPSON

10 INTODUCTION.2 Block Diagram Core CPU SC88 OSC, 2 OSC3, 4 Oscillator Interrupt Controller MCU/MPU BEQ (P24) BACK (P25) ESET TEST VDD VSS VD V VCVC5 CAP, CAM, CA2P, CA2M, CA3P, CA4P System Controller eset/test (Voltage detection & power on reset) Watchdog Timer Clock Timer Supply Voltage Detector Internal & LCD Power Generator I/O Port Serial Interface Programmable Timer External Memory Interface Output Port LCD Driver PP7 (DD7) P (SIN) P (SOUT) P2 (SCLK) P3 (SDY) P4 (SIN) P5 (SOUT) P6 (SCLK) P7 (SDY) P2 (TOUT/TOUT) P2 (TOUT2/TOUT3) P22 (FOUT) P23 (TOUT2/TOUT3) P24 (BEQ/EXCL) P25 (BACK/EXCL) P26 (CL/EXCL2) P27 (F/EXCL3) 7 (AA7) 7 (A8A5) 223 (A6A9) 24, 25 (D, W) 333 (CECE3) SEGSEG27 COMCOM63 OM 48K bytes Display Data AM 892 x 2 bits OM (for Font Data) 52K bytes AM 8K bytes Fig..2. SC88655 block diagram.3 Pad Layout.3. Diagram of pad layout Upper left alignment mark ( ) Die No. CA655Dxxx Y X (, ) mm Lower right alignment mark ( ) mm Chip size) mm Chip thickness) 725 µm Pad size) No. 98: µm, No. 9934: 54 µm, No : 54 µm, No : 54 µm Bump pitch) No. 98: µm (Min.), No. 9932: 8 µm (Min.) Bump height) 22.5 µm Alignment mark coordinates) Upper left corner: (-556, 66), Lower right corner: (5569, -569) Fig..3.. Pad layout N.C. 2 EPSON SC88655 TECHNICAL MANUAL

11 SC88655 TECHNICAL MANUAL EPSON 3 INTODUCTION.3.2 Pad coordinates Table.3.2. Pad coordinates (Unit: µm) No Name (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) VDD OSC2 OSC VSS VD OSC4 OSC3 TEST MCU/MPU ESET VSS P27/F/EXCL3 P26/CL/EXCL2 P25/BACK/EXCL P24/BEQ/EXCL P23/TOUT2/TOUT3 P22/FOUT P2/TOUT2/TOUT3 P2/TOUT/TOUT P7/SDY P6/SCLK P5/SOUT P4/SIN P3/SDY P2/SCLK P/SOUT P/SIN VDD P7/D7 P6/ P5/ P4/D4 P3/D3 P2/ P/D P/D /A /A 2/A2 3/A3 4/A4 5/A5 6/A6 7/A7 /A8 /A9 2/A 3/A 4/A2 5/A3 6/A4 7/A5 2/A6 2/A7 22/A8 23/A9 24/D 25/W 3/CE 3/CE 32/CE2 33/CE3 (N.C.) VDD VSS (N.C.) X -3,886-3,86-3,726-3,646-3,566-3,486-3,46-3,326-3,246-3,66-3,86-3,6-2,926-2,846-2,766-2,686-2,66-2,526-2,446-2,366-2,286-2,26-2,26-2,46 -,966 -,886 -,86 -,726 -,646 -,566 -,486 -,46 -,326 -,246 -,66 -,86 -, ,6,86,66,246,326,46,486,566,646,726,86,886,966 2,46 2,26 2,26 2,286 Y -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 Pad Coordinates No X 2,366 2,446 2,526 2,66 2,686 2,766 2,846 2,926 3,6 3,86 3,66 3,246 3,326 3,46 3,486 3,566 3,646 3,726 3,86 3,886 3,966 4,46 4,26 4,26 4,286 4,366 4,446 4,526 4,66 4,686 4,766 4,846 4,926 5,6 5,86 5,66 5,246 5,326 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 5,689 Y -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,342 -,262 -,82 -,2 -, ,58,38,28,298,378,458 Pad Coordinates No Name SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG2 SEG2 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 (N.C.) (N.C.) (N.C.) (N.C.) COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM4 COM4 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM5 COM5 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM6 COM6 COM62 COM63 (N.C.) (N.C.) X -3,268-3,42-3,535-3,635-3,735-3,869-4,2-4,2-4,22-4,32-4,42-4,52-4,62-4,72-4,82-4,92-5,2-5,2-5,22-5,32-5,42-5,52-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,689-5,326-5,246-5,66-5,86-5,6-4,926-4,846-4,766-4,686-4,66-4,526-4,446-4,366-4,286-4,26-4,26-4,46-3,966 Y,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,458,378,298,28,38, ,22 -,2 -,82 -,262 -,342 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 -,689 Pad Coordinates No Name SEG6 SEG7 SEG8 SEG9 SEG2 SEG2 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG3 SEG3 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG4 SEG4 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG5 SEG5 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG6 SEG6 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG7 SEG7 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG8 SEG8 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG9 SEG9 X 5,52 5,42 5,32 4,32 3,932 3,832 3,732 3,632 3,532 3,432 3,332 3,232 3,32 3,32 2,932 2,832 2,732 2,632 2,532 2,432 2,332 2,232 2,32 2,32,932,832,732,632,532,432,332,232,32, ,68 -,68 -,268 -,368 -,468 -,568 -,668 -,768 -,868 -,968-2,68-2,68-2,268-2,368-2,468-2,568-2,668-2,768-2,868-2,968-3,68-3,68 Y,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72,72 Pad Coordinates Name CA3P CAM CAP V CA4P CA2M CA2P V VSS VC VC2 VC3 VC4 VC5 (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) COM3 COM3 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM2 COM2 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM COM COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM COM (N.C.) (N.C.) (N.C.) (N.C.) SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG SEG SEG2 SEG3 SEG4 SEG5

12 INTODUCTION.3.3 Pad description Table.3.3. Pad description Pad name Pad No. In/Out Init* Function, 38, 74 4, 2, 75, , , 78, 83, 82, 77, 8 3 I I 2 O O 7 I I 6 O O 9 I I (Pull-up) 4754 O O (H) 5562 O O (H) 6366 O O (H) 67 O O (H) 68 O O (H) 6972 O O (H) 4639 I/O I (Pull-up) 37 I/O I (Pull-up) 36 I/O I (Pull-up) 35 I/O I (Pull-up) 34 I/O I (Pull-up) 33 I/O I (Pull-up) 32 I/O I (Pull-up) 3 I/O I (Pull-up) 3 I/O I (Pull-up) 29 I/O I (Pull-up) VDD VSS VD V VCVC5 CAP, CAM, CA2P, CA2M, CA3P, CA4P OSC OSC2 OSC3 OSC4 MCU/MPU 7/AA7 7/A8A5 223/A6A9 24/D 25/W 333/CECE3 PP7/DD7 P/SIN P/SOUT P2/SCLK P3/SDY P4/SIN P5/SOUT P6/SCLK P7/SDY P2/TOUT/TOUT P2/TOUT2/TOUT3 P22/FOUT P23/TOUT2/TOUT3 P24/BEQ/EXCL P25/BACK/EXCL P26/CL/EXCL2 P27/F/EXCL3 COMCOM63 SEGSEG27 ESET TEST , I/O I/O I/O I/O I/O I/O I/O O O I I I (Pull-up) I (Pull-up) I (Pull-up) I (Pull-up) I (Pull-up) I (Pull-up) I (Pull-up) O (L) O (L) I (Pull-up) I (Pull-up) Power supply (+) terminal Power supply (GND) terminal Internal logic and oscillation system voltage regulator output terminal LCD circuit power voltage booster output terminal LCD drive voltage output terminals LCD voltage booster capacitor connection terminals OSC oscillation input terminal (select crystal/c oscillation by mask option) OSC oscillation output terminal OSC3 oscillation input terminal (select crystal/ceramic/c oscillation by mask option) OSC3 oscillation output terminal MCU/MPU mode setup terminal Output terminals (7) or address bus (AA7) Output terminals (7) or address bus (A8A5) Output terminals (223) or address bus (A6A9) Output terminal (24) or read signal output terminal (D) Output terminal (25) or write signal output terminal (W) Output terminals (333) or chip enable signal output terminals (CECE3) I/O terminals (PP7) or data bus (DD7) I/O terminal (P) or serial I/F Ch. data input terminal (SIN) I/O terminal (P) or serial I/F Ch. data output terminal (SOUT) I/O terminal (P2) or serial I/F Ch. clock I/O terminal (SCLK) I/O terminal (P3) or serial I/F Ch. ready signal output terminal (SDY) I/O terminal (P4) or serial I/F Ch. data input terminal (SIN) I/O terminal (P5) or serial I/F Ch. data output terminal (SOUT) I/O terminal (P6) or serial I/F Ch. clock I/O terminal (SCLK) I/O terminal (P7) or serial I/F Ch. ready signal output terminal (SDY) I/O terminal (P2) or programmable timer underflow signal output terminal (TOUT/TOUT) I/O terminal (P2) or programmable timer underflow signal output terminal (TOUT2/TOUT3) I/O terminal (P22) or clock output terminal (FOUT) I/O terminal (P23) or programmable timer underflow inverted signal output terminal (TOUT2/TOUT3) I/O terminal (P24), bus request signal input terminal (BEQ) or programmable timer external clock input terminal (EXCL) I/O terminal (P25), bus acknowledge signal output terminal (BACK) or programmable timer external clock input terminal (EXCL) I/O terminal (P26), LCD clock output terminal (CL) or programmable timer external clock input terminal (EXCL2) I/O terminal (P27), LCD frame signal output terminal (F) or programmable timer external clock input terminal (EXCL3) LCD common output terminals LCD segment output terminals Initial reset input terminal Test input terminal (Pull-up): Pulled up (Hi-Z when Gate Direct is selected by mask option), (H): HIGH level output, (L): LOW level output 4 EPSON SC88655 TECHNICAL MANUAL

13 INTODUCTION.4 Mask Option Mask options shown below are provided for the SC Several hardware specifications are prepared in each mask option, and one of them can be selected according to the application. Multiple specifications are available in each option item as indicated in the Option List. Select the specifications that meet the target system and check the appropriate box. The option selection is done interactively on the screen during function option generator winfog execution, using this option list as reference. Mask pattern of the IC is finally generated based on the data created by the winfog. efer to the "S5UC88C Manual II" for details on the winfog. PEIPHEAL CICUIT BOAD option list The following shows the options for configuring the Peripheral Circuit Board (S5UC88P with S5UC88655P2) installed in the ICE (S5UC88H5). The selections do not affect the IC's mask option. A OSC SYSTEM CLOCK. Internal Clock 2. User Clock B OSC3 SYSTEM CLOCK. Internal Clock 2. User Clock When User Clock is selected, input a clock to the OSC terminal. When Internal Clock is selected, the clock frequency is changed according to the oscillation circuit selected by the IC's mask option. When User Clock is selected, input a clock to the OSC3 terminal. When Internal Clock is selected, the clock frequency is changed according to the oscillation circuit selected by the IC's mask option. SC88655 mask option list The following shows the option list for generating the IC's mask pattern. Note that the Peripheral Circuit Board installed in the ICE does not support some options. OSC SYSTEM CLOCK. Crystal 2. C 2 OSC3 SYSTEM CLOCK. Crystal 2. Ceramic 3. C 3 INPUT POT PULL UP ESISTO MCU/MPU.... With esistor 2. Gate Direct ESET.... With esistor 2. Gate Direct The specification of the OSC oscillation circuit can be selected from among two types: "Crystal oscillation" and "C oscillation". efer to Section 8.4, "OSC Oscillation Circuit", for details. The specification of the OSC3 oscillation circuit can be selected from among three types: "Crystal oscillation", "Ceramic oscillation" and "C oscillation". efer to Section 8.3, "OSC3 Oscillation Circuit", for details. This mask option can select whether the pull-up resistors for the MCU/MPU and ESET terminals are used or not. SC88655 TECHNICAL MANUAL EPSON 5

14 INTODUCTION 4 I/O POT PULL UP ESISTO P.... With esistor 2. Gate Direct P.... With esistor 2. Gate Direct P2.... With esistor 2. Gate Direct P3.... With esistor 2. Gate Direct P4.... With esistor 2. Gate Direct P5.... With esistor 2. Gate Direct P6.... With esistor 2. Gate Direct P7.... With esistor 2. Gate Direct P.... With esistor 2. Gate Direct P.... With esistor 2. Gate Direct P2.... With esistor 2. Gate Direct P3.... With esistor 2. Gate Direct P4.... With esistor 2. Gate Direct P5.... With esistor 2. Gate Direct P6.... With esistor 2. Gate Direct P7.... With esistor 2. Gate Direct P2.... With esistor 2. Gate Direct P2.... With esistor 2. Gate Direct P With esistor 2. Gate Direct P With esistor 2. Gate Direct P With esistor 2. Gate Direct P With esistor 2. Gate Direct P With esistor 2. Gate Direct P With esistor 2. Gate Direct This mask option can select whether the pull-up resistor for the I/O port terminal (it works during input mode) is used or not. It is possible to select for each bit of the I/O ports. efer to Chapter, "I/O Ports (P Ports)", for details. 5 I/O POT INPUT I/F LEVEL P.... CMOS Level P.... CMOS Level P2.... CMOS Level P3.... CMOS Level P4.... CMOS Level P5.... CMOS Level P6.... CMOS Level P7.... CMOS Level P2.... CMOS Level P2.... CMOS Level P CMOS Level P CMOS Level P CMOS Level P CMOS Level P CMOS Level P CMOS Level 2. CMOS Schmitt 2. CMOS Schmitt 2. CMOS Schmitt 2. CMOS Schmitt 2. CMOS Schmitt 2. CMOS Schmitt 2. CMOS Schmitt 2. CMOS Schmitt 2. CMOS Schmitt 2. CMOS Schmitt 2. CMOS Schmitt 2. CMOS Schmitt 2. CMOS Schmitt 2. CMOS Schmitt 2. CMOS Schmitt 2. CMOS Schmitt This mask option can select the interface level of the I/O (P) port from either the CMOS level or CMOS Schmitt level. It is possible to select for each bit of the I/O ports. efer to Chapter, "I/O Ports (P Ports)", for details. 6 ESET VOLTAGE DETECTO. Not Use 2. Use 7 WATCHDOG TIME OVEFLOW CYCLE. Not Use /fOSC (-sec cycle when fosc = 32 khz) /fOSC (2-sec cycle when fosc = 32 khz) /fOSC (4-sec cycle when fosc = 32 khz) 8 WATCHDOG TIME OVEFLOW SIGNAL. Interrupt (NMI) 2. eset This mask option can select whether the built-in reset voltage detection circuit is used or not. efer to Section 5..2, "eset voltage detector", for details. This mask option can select a watchdog timer overflow cycle. efer to Chapter 4, "Watchdog Timer", for details. This mask option can select whether the watchdog timer overflow signal is used to generate NMI or reset. efer to Chapter 4, "Watchdog Timer", for details. 6 EPSON SC88655 TECHNICAL MANUAL

15 2 CPU This chapter explains the CPU and operating mode. 2 CPU 2. Core CPU The SC88655 contains the SC88 8-bit core CPU, so its register configuration, command set and other core features are similar to other family processors incorporating the SC88. See the "SC88 Core CPU Manual" for the SC CPU model The SC88655 employs the Model 3 SC88 CPU which has a maximum address space of M bytes CC (customized condition flag) The SC88655 does not use the customized condition flag (CC) in the core CPU. Accordingly, it cannot be used as a branching condition for the conditional branching instruction (JS, CAS). 2.2 MCU Mode and MPU Mode The chip operating mode can be set to one of two settings using the MCU/MPU terminal MCU mode Setting MCU mode: MCU/MPU terminal = HIGH Set to this mode when using the internal OM. With respect to areas other than internal memory, external memory can even be expanded. See Chapter 3, "Memory Map", for the memory map. In the MCU mode, during initial reset, only systems in internal memory are activated. The internal program OM is normally fixed as the top portion of the common program memory area (logical space H7FFFH). Exception processing vectors are assigned in the internal program OM. Furthermore, the application initialization routines that start with reset exception processing must likewise be written to the internal program OM. Since bus and other settings which correlate with external expanded memory can be executed in software, this processing is executed in the initialization routine written to the internal program OM. Once these bus mode settings are made, external memory can be accessed. See Chapter 6, "System Controller and Bus Control", for setting bus mode. When accessing the internal memory in this mode, the chip enable (CE) and read (D)/write (W) signals are not output to external memory, and the data bus (DD7) goes into high impedance status (or pull-up status). Consequently, in cases where addresses overlap in external and internal memory, the areas in external memory will be unavailable MPU mode Setting MPU mode: MCU/MPU terminal = LOW The internal OM area is released to an external device. The internal OM then becomes unusable and when this area is accessed, chip enable (CE) and read (D)/write (W) signals are output to external memory and the data bus (DD7) become active. These signals are not output to an external device when other areas of internal memory are accessed. In the MPU mode, the system is activated by external memory. When using this mode, the exception processing vectors and initialization routine must be assigned within the common area (H7FFFH) Mask option You can select whether the built-in pull-up resistor for the MCU/MPU terminal is used or not by mask option. Input port pull-up resistor MCU/MPU... With resistor Notes: Gate direct Setting of MCU/MPU terminal is latched at the rising edge of a reset signal input from the ESET terminal. Therefore, if the setting is to be changed, the ESET terminal must be set to LOW level once again. The data bus while the CPU accesses to the internal memory can be select into highimpedance status or pulled up to high using the pull-up control register and mask option. See Chapter, "I/O Ports (P Ports)", for details. SC88655 TECHNICAL MANUAL EPSON 7

16 3 MEMOY MAP 3 MEMOY MAP This chapter explains the memory configuration of the SC MCU Single Chip Mode The SC88655 should be placed in single chip mode when it is used as a single chip microcomputer without an externally expanded memory. Since this mode uses the internal OM, the system can be operated only in MCU mode. The MPU mode does not allow the IC to be placed in single chip mode. This mode does not need an external bus, so the terminals normally set for the external bus can be used as general-purpose output ports or I/O ports. See Chapter 6, "System Controller and Bus Control", for how to set single chip mode. 3.2 MCU Expansion Mode The SC88655 must be placed in expansion mode when it is used with an externally expanded memory up to M bytes 4. The internal OM is enabled in the MCU mode, so external memory can be assigned to the area from H to 4FFFFFH. See Chapter 6, "System Controller and Bus Control", for how to set expansion mode. 3.3 MPU Expansion Mode The internal OM area is released in the MPU mode, so external memory can be assigned to the area from H to 3FFFFFH. However, the area from CH to FFFFH is assigned to the internal memory and cannot be used to access an external device. 4FFFFFH 4H 3FFFFFH 3H 2FFFFFH 2H FFFFFH H FFFFFH 9H 8FFFFH H FFFFH FFH FEFFH ECH EBFFH E8H E7FFH E4H E3FFH EH DFFFH CH BFFFH H Internal font data OM (52KB) I/O memory Unused Display data AM (KB) Unused Display data AM (KB) Internal AM (8KB) Internal OM (48KB) 64KB space External memory CE area External memory CE3 area External memory CE2 area External memory CE area Unused Internal font data OM (52KB) I/O memory Unused Display data AM (KB) Unused Display data AM (KB) Internal AM (8KB) Internal OM (48KB) MB space MB space MB space MB space MB space External memory CE3 area External memory CE2 area External memory CE area External memory CE area I/O memory Unused Display data AM (KB) Unused Display data AM (KB) Internal AM (8KB) External memory CE area MB space MB space MB space MB space MCU single chip mode MCU expansion mode MPU expansion mode Fig. 3.. Memory map 8 EPSON SC88655 TECHNICAL MANUAL

17 3 MEMOY MAP 3.4 Internal Memory The SC88655 is equipped with a OM and AM as shown in Figure 3... Small-scale applications can be implemented in this chip alone Program OM The SC88655 has a built-in 48K-byte program OM. The OM is allocated to HBFFFH. This OM areas can be released to external memory depending on the setting of the MCU/ MPU terminal. (See Section 2.2, "MCU Mode and MPU Mode".) AM The internal AM capacity is 8K bytes and is allocated to CHDFFFH. Even when external memory which overlaps the internal AM area is expanded, the AM area is not released to external memory. Accesses to this area are always aimed at the internal AM. 3.5 I/O Memory A memory mapped I/O method is employed in the SC88655 for interfacing with the internal peripheral circuits. The peripheral circuit control bits and data registers are arranged in the data memory space, so normal memory access operations control the circuits and transfer data. The I/O memory is arranged in the area from FFH to FFFFH. Even when external memory which overlaps the I/O memory area is expanded, the I/O memory area is not released to external memory. Accesses to this area are always aimed at the I/O memory. The following shows the SC88655 I/O memory map Display data AM The SC88655 is equipped with an internal display data AM which stores a display data for LCD driver. The display data AM is allocated to EHEBFFH. See Chapter 5, "LCD Driver", for details of the display data AM. The display data AM area cannot be released to external memory. Accesses to this area are always aimed at the display data AM Font data OM The SC88655 has a built-in OM that can be used to store font data. The OM capacity is 52K bytes and is allocated to H8FFFFH. The entire OM area when any font data is not used or the remaining area unused for font data can be used for a program and data storage area (see "Appendix B" for use of font data). This OM area can be released to external memory depending on the setting of the MCU/MPU terminal. (See Section 2.2, "MCU Mode and MPU Mode".) SC88655 TECHNICAL MANUAL EPSON 9

18 3 MEMOY MAP Table 3.5.(a) I/O Memory map (FFHFF2H) Address Bit Name Function S Comment FF (MCU) D7 BUSMOD Bus mode CPUMOD CPU mode Expansion Maximum Single chip Minimum D4 Constantly "" when being read D3 CE3 CE3 (33) CE3 enable CE3 disable In Single chip mode, CE signal output Enable/Disable CE2 CE2 (32) CE2 enable CE2 disable these setting are fixed Enable: CE signal output D CE CE (3) CE enable CE disable at DC output. Disable: DC (3x) output D CE CE (3) CE enable CE disable FF (MPU) D7 BUSMOD Bus mode CPUMOD CPU mode Expansion Maximum Minimum Expansion mode only D4 Constantly "" when being read D3 CE3 CE3 (33) CE3 enable CE3 disable CE signal output Enable/Disable CE2 CE2 (32) CE2 enable CE2 disable Enable: CE signal output D CE CE (3) CE enable CE disable Disable: DC (3x) output D CE CE (3) CE enable FF D7 D4 SPP7 SPP6 SPP5 SPP4 Stack pointer page address < SP page allocatable address > Single chip mode: only page (MSB) D3 D SPP3 SPP2 SPP Expansion mode: 27H page D SPP (LSB) FF2 D7 EB Bus release enable register P24 BEQ (P24 and P25 terminal specification) P25 BACK WT2 Wait control register Number of state WT D4 WT WT2 WT WT D3 CLKCHG CPU operating clock switch D D SOSC3 SOSC OSC3 oscillation On/Off control OSC oscillation On/Off control No wait OSC3 On On OSC Off Off "" when being read 2 3 CLKCHG cannot be set to "" when SOSC = "" (OSC oscillation is OFF) and cannot be set to "" when SOSC3 = "" (OSC3 oscillation is OFF). 2 Cannot be turned OFF when the CPU is running with the OSC3 clock. 3 Cannot be turned OFF when the CPU is running with the OSC clock or the watchdog timer is enabled. Note: All the interrupts including NMI are disabled, until you write the optional value into both the "FFH" and "FFH" addresses. EPSON SC88655 TECHNICAL MANUAL

19 3 MEMOY MAP Table 3.5.(b) I/O Memory map (FF4HFFAH) Address Bit Name Function S Comment FF4 D7 FOUTON FOUT output control On Off FOUT2 FOUT frequency selection FOUT D4 FOUT FOUT2 FOUT FOUT Frequency fosc3 / 8 fosc3 / 4 fosc3 / 2 fosc3 / fosc / 8 fosc / 4 fosc / 2 fosc / D3 D D WDST Watchdog timer reset FF8 D7 LCLK CL output control LFM F output control SEGEV SEG output assignment control D4 COMEV COM output assignment control D3 DSPA LCD display data AM area selection DSPEV everse display control D DSPC LCD display control DSPC DSPC Display All dots ON D DSPC All dots OFF Normal display Display off FF9 D7 LCDON LCD driver circuit On/Off control LBIAS LCD bias selection D4 VCON VC4 voltage generator On/Off control D3 VC5ON VC5 voltage generator On/Off control LBON Supply voltage booster On/Off control D LCDCS Display timing generator control LCDCS LCDCS Source clock P timer 5 D LCDCS fosc/2 fosc/ Off FFA D7 D4 D3 LSEL2 VC5 voltage generator resistance ratio adjustment D LSEL D LSEL LSEL2 LSEL LSEL esistance ratio Not allowed eset No operation On Off On Off Normal everse Normal everse Display area Display area Normal everse On /9 bias On On On Off /7 bias Off Off Off W Constantly "" when being read "" when being read Constantly "" when being read SC88655 TECHNICAL MANUAL EPSON

20 3 MEMOY MAP Table 3.5.(c) I/O Memory map (FFBHFF5H) Address Bit Name Function S Comment FFB D7 LEV5 VC5 voltage control Constantly "" when being read D4 LEV4 LEV5 LEV4 LEV3 LEV2 LEV LEV Level D3 LEV LEV2 : : : : : : : D D LEV LEV FFC D7 D4 SVDDT SVDON SVD detection data SVD circuit On/Off Low On Normal Off Constantly "" when being read D3 D D SVDS3 SVDS2 SVDS SVDS SVD criteria voltage setting SVDS3 SVDS2 SVDS SVDS Voltage (V) : : : : :.8 FF D7 PSIF Serial interface interrupt priority register PSIF PSIF PSIF PPT PPT PPT Programmable timer interrupt PPT3 PPT2 Priority D4 PPT priority register PP2 PP2 level D3 PPT3 Programmable timer 32 interrupt Level 3 Level 2 PPT2 priority register Level D PP2 P2P27 interrupt priority register Level D PP2 FF D7 PPT5 Programmable timer 54 interrupt PPT5 PPT4 PPT4 priority register PPT7 PPT6 PPT7 Programmable timer 76 interrupt PTM PTM Priority D4 PPT6 priority register PSIF PSIF level D3 PTM Clock timer interrupt priority register Level 3 Level 2 PTM Level D PSIF Serial interface interrupt priority register Level D PSIF FF4 D7 EP27 EP26 EP25 P27 interrupt enable P26 interrupt enable P25 interrupt enable D4 EP24 P24 interrupt enable Interrupt Interrupt D3 EP23 P23 interrupt enable enable disable D D EP22 EP2 EP2 P22 interrupt enable P2 interrupt enable P2 interrupt enable FF5 D7 ETC3 ETU3 ETC2 PTM3 compare match interrupt enable PTM3 underflow interrupt enable PTM2 compare match interrupt enable D4 ETU2 PTM2 underflow interrupt enable Interrupt Interrupt D3 ETC PTM compare match interrupt enable enable disable D D ETU ETU ETC PTM underflow interrupt enable PTM underflow interrupt enable PTM compare match interrupt enable 2 EPSON SC88655 TECHNICAL MANUAL

21 3 MEMOY MAP Table 3.5.(d) I/O Memory map (FF6HFFCH) Address Bit Name Function S FF6 D7 D4 ESE Serial I/F (error) interrupt enable ESEC Serial I/F (receive) interrupt enable D3 ESTA Serial I/F (transmit) interrupt enable ESE Serial I/F (error) interrupt enable Interrupt enable Interrupt disable D D ESEC Serial I/F (receive) interrupt enable ESTA Serial I/F (transmit) interrupt enable FF7 D7 D4 D3 ETM32 Clock timer 32 Hz interrupt enable ETM8 Clock timer 8 Hz interrupt enable Interrupt Interrupt D ETM2 Clock timer 2 Hz interrupt enable enable disable D ETM Clock timer Hz interrupt enable FF8 D7 ETC7 PTM7 compare match interrupt enable ETU7 PTM7 underflow interrupt enable ETC6 PTM6 compare match interrupt enable D4 ETU6 PTM6 underflow interrupt enable Interrupt Interrupt D3 ETC5 PTM5 compare match interrupt enable enable disable ETU5 PTM5 underflow interrupt enable D ETC4 PTM4 compare match interrupt enable D ETU4 PTM4 underflow interrupt enable FFA D7 FP27 P27 interrupt factor flag () () FP26 P26 interrupt factor flag Interrupt No interrupt FP25 P25 interrupt factor flag factor is factor is D4 FP24 P24 interrupt factor flag occurred occurred D3 FP23 P23 interrupt factor flag FP22 P22 interrupt factor flag (W) (W) D FP2 P2 interrupt factor flag eset No operation D FP2 P2 interrupt factor flag FFB D7 FTC3 PTM3 compare match interrupt factor flag () () FTU3 PTM3 underflow interrupt factor flag Interrupt No interrupt FTC2 PTM2 compare match interrupt factor flag factor is factor is D4 FTU2 PTM2 underflow interrupt factor flag occurred occurred D3 FTC PTM compare match interrupt factor flag FTU PTM underflow interrupt factor flag (W) (W) D FTU PTM underflow interrupt factor flag eset No operation D FTC PTM compare match interrupt factor flag FFC D7 FSE Serial I/F (error) interrupt factor flag () () D4 FSEC Serial I/F (receive) interrupt factor flag Interrupt No interrupt factor is factor is D3 FSTA Serial I/F (transmit) interrupt factor flag occurred occurred FSE Serial I/F (error) interrupt factor flag (W) (W) D FSEC Serial I/F (receive) interrupt factor flag eset No operation D FSTA Serial I/F (transmit) interrupt factor flag Comment Constantly "" when being read Constantly "" when being read Constantly "" when being read SC88655 TECHNICAL MANUAL EPSON 3

22 3 MEMOY MAP Table 3.5.(e) I/O Memory map (FFDHFF2H) Address Bit Name Function S Comment FFD D7 D4 Constantly "" when being read D3 FTM32 Clock timer 32 Hz interrupt factor flag () () FTM8 Clock timer 8 Hz interrupt factor flag Occurred Not occurred D FTM2 Clock timer 2 Hz interrupt factor flag (W) (W) D FTM Clock timer Hz interrupt factor flag eset No operation FFE D7 FTC7 FTU7 FTC6 PTM7 compare match interrupt factor flag PTM7 underflow interrupt factor flag PTM6 compare match interrupt factor flag () Interrupt factor is () No interrupt factor is D4 FTU6 PTM6 underflow interrupt factor flag occurred occurred D3 FTC5 PTM5 compare match interrupt factor flag D D FTU5 FTC4 FTU4 PTM5 underflow interrupt factor flag PTM4 compare match interrupt factor flag PTM4 underflow interrupt factor flag (W) eset (W) No operation FF2 D7 PPT Programmable timer clock control PST2 Programmable timer division ratio PST2 PST PST (OSC3) (OSC) fosc3 / 496 fosc / 28 PST fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 D4 PST fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / D3 PPT Programmable timer clock control PST2 Programmable timer division ratio PST2 PST PST (OSC3) (OSC) fosc3 / 496 fosc / 28 D PST fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 D PST fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / FF2 D7 PPT3 Programmable timer 3 clock control PST32 PST3 D4 PST3 Programmable timer 3 division ratio PST32 PST3 PST3 (OSC3) (OSC) fosc3 / 496 fosc / 28 fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / D3 PPT2 Programmable timer 2 clock control PST22 Programmable timer 2 division ratio PST22 PST2 PST2 (OSC3) (OSC) fosc3 / 496 fosc / 28 D PST2 fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 D PST2 fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / On On On On Off Off Off Off 4 EPSON SC88655 TECHNICAL MANUAL

23 3 MEMOY MAP Table 3.5.(f) I/O Memory map (FF23HFF27H) Address Bit Name Function S Comment FF23 D7 D4 D3 D D PTF3 PTF2 PTF PTF register Programmable timer 3 source clock selection Programmable timer 2 source clock selection Programmable timer source clock selection Programmable timer source clock selection fosc fosc fosc fosc fosc3 fosc3 fosc3 fosc3 Constantly "" when being read eserved register FF24 D7 PPT5 Programmable timer 5 clock control On Off PST52 Programmable timer 5 division ratio PST52 PST5 PST5 (OSC3) (OSC) fosc3 / 496 fosc / 28 PST5 fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 D4 PST5 fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / D3 PPT4 Programmable timer 4 clock control PST42 Programmable timer 4 division ratio PST42 PST4 PST4 (OSC3) (OSC) fosc3 / 496 fosc / 28 D PST4 fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 D PST4 fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / FF25 D7 PPT7 Programmable timer 7 clock control PST72 PST7 D4 PST7 Programmable timer 7 division ratio PST72 PST7 PST7 (OSC3) (OSC) fosc3 / 496 fosc / 28 fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / D3 PPT6 Programmable timer 6 clock control PST62 Programmable timer 6 division ratio PST62 PST6 PST6 (OSC3) (OSC) fosc3 / 496 fosc / 28 D PST6 fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 D PST6 fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / FF27 D7 D4 D3 PTF7 Programmable timer 7 source clock selection PTF6 Programmable timer 6 source clock selection D PTF5 Programmable timer 5 source clock selection D PTF4 Programmable timer 4 source clock selection On On On fosc fosc fosc fosc Off Off Off fosc3 fosc3 fosc3 fosc3 Constantly "" when being read SC88655 TECHNICAL MANUAL EPSON 5

24 3 MEMOY MAP Table 3.5.(g) I/O Memory map (FF3HFF35H) Address Bit Name Function S Comment FF3 D7 MODE6_A PTM 8/6-bit mode selection PTNEN_A External clock noise rejector selection 6-bit x Enable 8-bit x 2 Disable D4 register "" when being read eserved register D3 PTOUT PTM clock output control PTUN PTM un/stop control On un Off Stop D PSET PTM preset Preset No operation W "" when being read D CKSEL PTM input clock selection External clock Internal clock FF3 D7 D4 register D3 PTOUT PTM clock output control PTUN PTM un/stop control On un Off Stop D PSET PTM preset Preset No operation D CKSEL PTM input clock selection External clock Internal clock FF32 D7 D7 PTM reload data D7 (MSB) PTM reload data PTM reload data D4 D4 PTM reload data D4 D3 D3 PTM reload data D3 High Low PTM reload data D D PTM reload data D D D PTM reload data D (LSB) FF33 D7 D7 PTM reload data D7 (MSB) PTM reload data PTM reload data D4 D4 PTM reload data D4 D3 D3 PTM reload data D3 High Low D D D D PTM reload data PTM reload data D PTM reload data D (LSB) FF34 D7 CD7 PTM compare data D7 (MSB) C PTM compare data C PTM compare data D4 CD4 PTM compare data D4 D3 CD3 PTM compare data D3 High Low C PTM compare data D CD PTM compare data D D CD PTM compare data D (LSB) FF35 D7 CD7 PTM compare data D7 (MSB) C PTM compare data C PTM compare data D4 CD4 PTM compare data D4 D3 CD3 PTM compare data D3 High Low C PTM compare data D CD PTM compare data D D CD PTM compare data D (LSB) W Constantly "" when being read eserved register "" when being read 6 EPSON SC88655 TECHNICAL MANUAL

25 3 MEMOY MAP Table 3.5.(h) I/O Memory map (FF36HFF3BH) Address Bit Name Function S Comment FF36 D7 PTM7 PTM6 PTM5 PTM data D7 (MSB) PTM data PTM data D4 PTM4 PTM data D4 D3 PTM3 PTM data D3 High Low D D PTM2 PTM PTM PTM data PTM data D PTM data D (LSB) FF37 D7 PTM7 PTM6 PTM5 PTM data D7 (MSB) PTM data PTM data D4 PTM4 PTM data D4 D3 PTM3 PTM data D3 High Low D D PTM2 PTM PTM PTM data PTM data D PTM data D (LSB) FF38 D7 MODE6_B PTM23 8/6-bit mode selection PTNEN_B External clock noise rejector selection 6-bit x Enable 8-bit x 2 Disable "" when being read D4 D3 PTOUT2 PTM2 inverted clock output control PTOUT2 PTM2 clock output control PTUN2 PTM2 un/stop control On On un Off Off Stop D PSET2 PTM2 preset Preset No operation W "" when being read D CKSEL2 PTM2 input clock selection External clock Internal clock FF39 D7 D4 D3 PTOUT3 PTM3 inverted clock output control PTOUT3 PTM3 clock output control PTUN3 PTM3 un/stop control On On un Off Off Stop D PSET3 PTM3 preset Preset No operation D CKSEL3 PTM3 input clock selection External clock Internal clock FF3A D7 7 PTM2 reload data D7 (MSB) 6 PTM2 reload data 5 PTM2 reload data D4 4 PTM2 reload data D4 D3 3 PTM2 reload data D3 High Low 2 PTM2 reload data D PTM2 reload data D D PTM2 reload data D (LSB) FF3B D7 D37 D36 D35 PTM3 reload data D7 (MSB) PTM3 reload data PTM3 reload data D4 D34 PTM3 reload data D4 D3 D33 PTM3 reload data D3 High Low D D D32 D3 D3 PTM3 reload data PTM3 reload data D PTM3 reload data D (LSB) W Constantly "" when being read "" when being read SC88655 TECHNICAL MANUAL EPSON 7

26 3 MEMOY MAP Table 3.5.(i) I/O Memory map (FF3CHFF4H) Address Bit Name Function S Comment FF3C D7 C7 C6 C5 PTM2 compare data D7 (MSB) PTM2 compare data PTM2 compare data D4 C4 PTM2 compare data D4 D3 C3 PTM2 compare data D3 High Low D D C2 C C PTM2 compare data PTM2 compare data D PTM2 compare data D (LSB) FF3D D7 CD37 CD36 CD35 PTM3 compare data D7 (MSB) PTM3 compare data PTM3 compare data D4 CD34 PTM3 compare data D4 D3 CD33 PTM3 compare data D3 High Low D D CD32 CD3 CD3 PTM3 compare data PTM3 compare data D PTM3 compare data D (LSB) FF3E D7 PTM27 PTM26 PTM25 PTM2 data D7 (MSB) PTM2 data PTM2 data D4 PTM24 PTM2 data D4 D3 PTM23 PTM2 data D3 High Low D D PTM22 PTM2 PTM2 PTM2 data PTM2 data D PTM2 data D (LSB) FF3F D7 PTM37 PTM36 PTM35 PTM3 data D7 (MSB) PTM3 data PTM3 data D4 PTM34 PTM3 data D4 D3 PTM33 PTM3 data D3 High Low D D PTM32 PTM3 PTM3 PTM3 data PTM3 data D PTM3 data D (LSB) FF4 D7 D4 D3 D D TMST TMUN Clock timer reset Clock timer un/stop control eset un No operation Stop FF4 D7 TMD7 Clock timer data Hz TM Clock timer data 2 Hz TM Clock timer data 4 Hz D4 TMD4 Clock timer data 8 Hz D3 TMD3 Clock timer data 6 Hz High Low TM Clock timer data 32 Hz D TMD Clock timer data 64 Hz D TMD Clock timer data 28 Hz W Constantly "" when being read 8 EPSON SC88655 TECHNICAL MANUAL

27 3 MEMOY MAP Table 3.5.(j) I/O Memory map (FF48HFF4BH) Address Bit Name Function S Comment FF48 D7 STPB EP PMD D4 SCS D3 SCS SMD D SMD D ESIF SIF stop bit selection 2 bits bit Only for SIF parity enable register SIF parity mode selection SIF clock source selection SCS SCS Clock source Programmable timer fosc3 / 4 fosc3 / 8 fosc3 / 6 SIF mode selection SMD SMD Mode With parity Non parity Odd Even Asynchronous 8-bit Asynchronous 7-bit Clock synchronous slave Clock synchronous master SIF enable register Serial I/F I/O port FF49 D7 SDP FE SIF data input/output permutation selection SIF framing error flag W PE SIF parity error flag W D4 OE SIF overrun error flag W D3 XTG SIF receive trigger/status W XEN SIF receive enable D TXTG SIF transmit trigger/status W D TXEN SIF transmit enable FF4A D7 TXD7 SIF transmit data D7 (MSB) TX SIF transmit data TX SIF transmit data D4 TXD4 SIF transmit data D4 D3 TXD3 SIF transmit data D3 TX SIF transmit data D TXD SIF transmit data D D TXD SIF transmit data D (LSB) FF4B D7 D4 D3 D D XD7 X X XD4 XD3 X XD XD SIF receive data D7 (MSB) SIF receive data SIF receive data SIF receive data D4 SIF receive data D3 SIF receive data SIF receive data D SIF receive data D (LSB) MSB first LSB first Error No error eset () No operation Error No error eset () No operation Error No error eset () No operation un Stop Trigger No operation Enable Disable un Stop Trigger No operation Enable Disable High Low High Low asynchronous mode In the clock synchronous slave mode, external clock is selected. Only for asynchronous mode X X SC88655 TECHNICAL MANUAL EPSON 9

28 3 MEMOY MAP Table 3.5.(k) I/O Memory map (FF4CHFF4FH) Address Bit Name Function S Comment FF4C D7 STPB EP PMD D4 SCS D3 SCS SMD D SMD D ESIF SIF stop bit selection 2 bits bit Only for SIF parity enable register SIF parity mode selection SIF clock source selection SCS SCS Clock source Programmable timer fosc3 / 4 fosc3 / 8 fosc3 / 6 SIF mode selection SMD SMD Mode With parity Non parity Odd Even Asynchronous 8-bit Asynchronous 7-bit Clock synchronous slave Clock synchronous master SIF enable register Serial I/F I/O port FF4D D7 SDP FE SIF data input/output permutation selection SIF framing error flag W PE SIF parity error flag W D4 OE SIF overrun error flag W D3 XTG SIF receive trigger/status W XEN SIF receive enable D TXTG SIF transmit trigger/status W D TXEN SIF transmit enable FF4E D7 TXD7 SIF transmit data D7 (MSB) TX SIF transmit data TX SIF transmit data D4 TXD4 SIF transmit data D4 D3 TXD3 SIF transmit data D3 TX SIF transmit data D TXD SIF transmit data D D TXD SIF transmit data D (LSB) FF4F D7 D4 D3 D D XD7 X X XD4 XD3 X XD XD SIF receive data D7 (MSB) SIF receive data SIF receive data SIF receive data D4 SIF receive data D3 SIF receive data SIF receive data D SIF receive data D (LSB) MSB first LSB first Error No error eset () No operation Error No error eset () No operation Error No error eset () No operation un Stop Trigger No operation Enable Disable un Stop Trigger No operation Enable Disable High Low High Low asynchronous mode In the clock synchronous slave mode, external clock is selected. Only for asynchronous mode X X 2 EPSON SC88655 TECHNICAL MANUAL

29 3 MEMOY MAP Table 3.5.(l) I/O Memory map (FF5HFF55H) Address Bit Name Function S Comment FF5 D7 IOC7 IOC6 IOC5 P7 I/O control register P6 I/O control register P5 I/O control register D4 IOC4 P4 I/O control register D3 IOC3 P3 I/O control register Output Input D D IOC2 IOC IOC P2 I/O control register P I/O control register P I/O control register FF5 D7 IOC7 IOC6 IOC5 P7 I/O control register P6 I/O control register P5 I/O control register D4 IOC4 P4 I/O control register D3 IOC3 P3 I/O control register Output Input D D IOC2 IOC IOC P2 I/O control register P I/O control register P I/O control register FF52 D7 P7D P6D P5D P7 I/O port data P6 I/O port data P5 I/O port data D4 P4D P4 I/O port data D3 P3D P3 I/O port data High Low D D P2D PD PD P2 I/O port data P I/O port data P I/O port data FF53 D7 P7D P6D P5D P7 I/O port data P6 I/O port data P5 I/O port data D4 P4D P4 I/O port data D3 P3D P3 I/O port data High Low D D P2D PD PD P2 I/O port data P I/O port data P I/O port data FF54 D7 PULP7 PULP6 PULP5 P7 pull-up control register P6 pull-up control register P5 pull-up control register D4 PULP4 P4 pull-up control register D3 PULP3 P3 pull-up control register On Off D D PULP2 PULP PULP P2 pull-up control register P pull-up control register P pull-up control register FF55 D7 PULP7 PULP6 PULP5 P7 pull-up control register P6 pull-up control register P5 pull-up control register D4 PULP4 P4 pull-up control register D3 PULP3 P3 pull-up control register On Off D D PULP2 PULP PULP P2 pull-up control register P pull-up control register P pull-up control register SC88655 TECHNICAL MANUAL EPSON 2

30 3 MEMOY MAP Table 3.5.(m) I/O Memory map (FF6HFF68H) Address Bit Name Function S Comment FF6 D7 IOC27 IOC26 IOC25 D4 IOC24 D3 IOC23 IOC22 D IOC2 D IOC2 FF62 D7 P27D P26D P25D D4 P24D D3 P23D P22D D P2D D P2D P27 I/O control register P26 I/O control register P25 I/O control register P24 I/O control register P23 I/O control register P22 I/O control register P2 I/O control register P2 I/O control register P27 I/O port data P26 I/O port data P25 I/O port data P24 I/O port data P23 I/O port data P22 I/O port data P2 I/O port data P2 I/O port data FF64 D7 D4 D3 D D PULP27 PULP26 PULP25 PULP24 PULP23 PULP22 PULP2 PULP2 P27 pull-up control register P26 pull-up control register P25 pull-up control register P24 pull-up control register P23 pull-up control register P22 pull-up control register P2 pull-up control register P2 pull-up control register FF66 D7 PCP27 P27 input comparison register PCP26 P26 input comparison register PCP25 P25 input comparison register D4 PCP24 P24 input comparison register D3 PCP23 P23 input comparison register PCP22 P22 input comparison register D PCP2 P2 input comparison register D PCP2 P2 input comparison register FF68 D7 CTP22H P24P27 port chattering-eliminate setup (Input level check time) Check time CTP22H CTP2H CTP2H [sec] CTP2H 4/fOSC3 2/fOSC3 /fosc3 496/fOSC D4 CTP2H 248/fOSC 52/fOSC 28/fOSC None D3 CTP22L P2P23 port chattering-eliminate setup (Input level check time) Check time CTP22L CTP2L CTP2L [sec] D CTP2L 4/fOSC3 2/fOSC3 /fosc3 496/fOSC D CTP2L 248/fOSC 52/fOSC 28/fOSC None Output High On Interrupt occurred at falling edge Input Low Off Interrupt occurred at rising edge "" when being read "" when being read 22 EPSON SC88655 TECHNICAL MANUAL

31 3 MEMOY MAP Table 3.5.(n) I/O Memory map (FF7HFF75H) Address Bit Name Function S Comment FF7 D7 HZ7 HZ6 HZ5 7 high impedance control 6 high impedance control 5 high impedance control D4 HZ4 4 high impedance control High Complementary D3 HZ3 3 high impedance control impedance D D HZ2 HZ HZ 2 high impedance control high impedance control high impedance control FF7 D7 HZ7 HZ6 HZ5 7 high impedance control 6 high impedance control 5 high impedance control D4 HZ4 4 high impedance control High Complementary D3 HZ3 3 high impedance control impedance D D HZ2 HZ HZ 2 high impedance control high impedance control high impedance control FF72 D7 D4 HZ25 HZ24 25 high impedance control 24 high impedance control Constantly "" when being read D3 HZ23 23 high impedance control High Complementary HZ22 22 high impedance control impedance D D HZ2 HZ2 2 high impedance control 2 high impedance control FF73 D7 D4 D3 HZ33 33 high impedance control Constantly "" when being read HZ32 32 high impedance control High Complementary D HZ3 3 high impedance control impedance D HZ3 3 high impedance control FF74 D7 7D 6D 5D 7 output port data 6 output port data 5 output port data D4 4D 4 output port data D3 3D 3 output port data High Low D D 2D D D 2 output port data output port data output port data FF75 D7 7D 6D 5D 7 output port data 6 output port data 5 output port data D4 4D 4 output port data D3 3D 3 output port data High Low D D 2D D D 2 output port data output port data output port data SC88655 TECHNICAL MANUAL EPSON 23

32 3 MEMOY MAP Table 3.5.(o) I/O Memory map (FF76HFF83H) Address Bit Name Function S Comment FF76 D7 D4 D3 D D 25D 24D 23D 22D 2D 2D register register 25 output port data 24 output port data 23 output port data 22 output port data 2 output port data 2 output port data FF77 D7 D4 D3 D D 33D 32D 3D 3D register register register register 33 output port data 32 output port data 3 output port data 3 output port data FF8 D7 MODE6_C PTM45 8/6-bit mode selection PTNEN_C External clock 2 noise rejector selection D4 register D3 register PTUN4 PTM4 un/stop control D PSET4 PTM4 preset D CKSEL4 PTM4 input clock selection FF8 D7 D4 register D3 register PTUN5 PTM5 un/stop control D PSET5 PTM5 preset D CKSEL5 PTM5 input clock selection FF82 D7 D47 PTM4 reload data D7 (MSB) D46 PTM4 reload data D45 PTM4 reload data D4 D44 PTM4 reload data D4 D3 D43 PTM4 reload data D3 D42 PTM4 reload data D D4 PTM4 reload data D D D4 PTM4 reload data D (LSB) FF83 D7 7 PTM5 reload data D7 (MSB) 6 PTM5 reload data 5 PTM5 reload data D4 4 PTM5 reload data D4 D3 3 PTM5 reload data D3 2 PTM5 reload data D PTM5 reload data D D PTM5 reload data D (LSB) eserved register High Low eserved register High Low 6-bit x 8-bit x 2 Enable Disable un Stop Preset No operation External clock Internal clock un Stop Preset No operation External clock Internal clock High Low High Low "" when being read eserved register W "" when being read Constantly "" when being read eserved register W "" when being read 24 EPSON SC88655 TECHNICAL MANUAL

33 3 MEMOY MAP Table 3.5.(p) I/O Memory map (FF84HFF89H) Address Bit Name Function S Comment FF84 D7 CD47 CD46 CD45 PTM4 compare data D7 (MSB) PTM4 compare data PTM4 compare data D4 CD44 PTM4 compare data D4 D3 CD43 PTM4 compare data D3 High Low D D CD42 CD4 CD4 PTM4 compare data PTM4 compare data D PTM4 compare data D (LSB) FF85 D7 C7 C6 C5 PTM5 compare data D7 (MSB) PTM5 compare data PTM5 compare data D4 C4 PTM5 compare data D4 D3 C3 PTM5 compare data D3 High Low D D C2 C C PTM5 compare data PTM5 compare data D PTM5 compare data D (LSB) FF86 D7 PTM47 PTM46 PTM45 PTM4 data D7 (MSB) PTM4 data PTM4 data D4 PTM44 PTM4 data D4 D3 PTM43 PTM4 data D3 High Low D D PTM42 PTM4 PTM4 PTM4 data PTM4 data D PTM4 data D (LSB) FF87 D7 PTM57 PTM56 PTM55 PTM5 data D7 (MSB) PTM5 data PTM5 data D4 PTM54 PTM5 data D4 D3 PTM53 PTM5 data D3 High Low D D PTM52 PTM5 PTM5 PTM5 data PTM5 data D PTM5 data D (LSB) FF88 D7 MODE6_D PTM67 8/6-bit mode selection PTNEN_D External clock 3 noise rejector selection 6-bit x Enable 8-bit x 2 Disable D4 D3 register register "" when being read eserved register PTUN6 PTM6 un/stop control un Stop D PSET6 PTM6 preset Preset No operation W "" when being read D CKSEL6 PTM6 input clock selection External clock Internal clock FF89 D7 D4 D3 register register Constantly "" when being read eserved register PTUN7 PTM7 un/stop control un Stop D PSET7 PTM7 preset Preset No operation W "" when being read D CKSEL7 PTM7 input clock selection External clock Internal clock SC88655 TECHNICAL MANUAL EPSON 25

34 3 MEMOY MAP Table 3.5.(q) I/O Memory map (FF8AHFF8FH) Address Bit Name Function S Comment FF8A D PTM6 reload data D7 (MSB) PTM6 reload data PTM6 reload data D4 4 PTM6 reload data D4 D3 3 PTM6 reload data D3 High Low D D 2 PTM6 reload data PTM6 reload data D PTM6 reload data D (LSB) FF8B D7 D77 D76 D75 PTM7 reload data D7 (MSB) PTM7 reload data PTM7 reload data D4 D74 PTM7 reload data D4 D3 D73 PTM7 reload data D3 High Low D D D72 D7 D7 PTM7 reload data PTM7 reload data D PTM7 reload data D (LSB) FF8C D7 C7 C6 C5 PTM6 compare data D7 (MSB) PTM6 compare data PTM6 compare data D4 C4 PTM6 compare data D4 D3 C3 PTM6 compare data D3 High Low D D C2 C C PTM6 compare data PTM6 compare data D PTM6 compare data D (LSB) FF8D D7 CD77 CD76 CD75 PTM7 compare data D7 (MSB) PTM7 compare data PTM7 compare data D4 CD74 PTM7 compare data D4 D3 CD73 PTM7 compare data D3 High Low D D CD72 CD7 CD7 PTM7 compare data PTM7 compare data D PTM7 compare data D (LSB) FF8E D7 PTM67 PTM66 PTM65 PTM6 data D7 (MSB) PTM6 data PTM6 data D4 PTM64 PTM6 data D4 D3 PTM63 PTM6 data D3 High Low D D PTM62 PTM6 PTM6 PTM6 data PTM6 data D PTM6 data D (LSB) FF8F D7 PTM77 PTM76 PTM75 PTM7 data D7 (MSB) PTM7 data PTM7 data D4 PTM74 PTM7 data D4 D3 PTM73 PTM7 data D3 High Low D D PTM72 PTM7 PTM7 PTM7 data PTM7 data D PTM7 data D (LSB) 26 EPSON SC88655 TECHNICAL MANUAL

35 4 POWE SUPPLY 4 POWE SUPPLY This chapter explains the operating voltage and the configuration and control of the SC88655 internal power supply circuit. 4. Operating Voltage The SC88655 operating power voltage is as follows:.8 V to 3.6 V Supply a voltage within the above range to between the VDD (+) and VSS (GND) terminals. Note: The SC88655 has three VDD terminals and four VSS terminals. These terminals must be connected to VDD or VSS. Do not leave the terminals open. 4.2 Internal Power Supply Circuit The SC88655 has a built-in power supply circuit as shown in Figure 4.2. that generates all the voltages required for the internal circuits from the supply voltage within the range described above. Notes: Be sure not to use the voltages output from the VD, V, and VCVC5 terminals for driving external circuits. Voltage within the range of 2. to 3.6 V should be supplied to VDD when generating the VC to VC5 voltages. If VDD =.82. V, the VC to VC5 voltages will be generated higher than those described in Chapter 9, "Electrical Characteristics". VDD Internal circuit VD VD voltage generator VD OSC3 oscillation circuit OSC3, OSC4 V CA3P CAM CAP CA4P CA2M CA2P VC5 Supply voltage booster V VC5 voltage generator VC5 LBON Programmable timer 5 underflow signal LEV5 eference voltage generator VC5ON LSEL2 Voltage booster clock OSC oscillation circuit Divider Display timing generator LCD driver circuit OSC, OSC2 COM63 SEG27 VC4 VC3 VC2 VC VC4 voltage generator VC5 VCON LBIAS LCDON VSS Fig Configuration of internal power supply circuit SC88655 TECHNICAL MANUAL EPSON 27

36 4 POWE SUPPLY 4.2. VD voltage generator The VD voltage generator outputs the VD operating voltage for the internal logic and oscillation circuits. The VD voltage value is fixed at.8 V (Typ.) Supply voltage booster circuit The V voltage is used to drive the VC5 voltage generator and VC4 voltage generator that generates the LCD drive voltages. The supply voltage booster circuit generates the V voltage by double, triple, quadruple, or quintuple boosting the supply voltage VDD. The boost ratio can be configured with the external circuit as shown in Figure Select a boost ratio according to the VDD voltage value so that the V voltage level is higher than the desired VC5. CA3P CAM CAP CA4P CA2M CA2P V VSS Quintuple boosting circuit V = 5 VDD CA3P CAM CAP CA4P CA2M CA2P V VSS Triple boosting circuit V = 3 VDD CA3P CAM CAP CA4P CA2M CA2P V VSS Quadruple boosting circuit V = 4 VDD CA3P CAM CAP CA4P CA2M CA2P V VSS Double boosting circuit V = 2 VDD Fig External connection for supply voltage booster circuit Notes: Make sure that the V voltage does not exceed the absolute maximum rating (see Chapter 9, "Electrical Characteristics") when setting the boosting ratio. The capacitances depend on the load of the LCD panel to drive. Select component values so that the LCD drive voltages are stabilized as much as possible. Current consumption varies according to the boosting ratio. See Chapter 9, "Electrical Characteristics". The supply voltage booster circuit is activated by writing "" to the supply voltage booster ON/OFF control register LBON and is deactivated by writing "". However, the LCD display timing generator must be turned ON to supply the voltage booster clock to the supply voltage booster circuit before turning the circuit ON VC5 voltage generator The VC5 voltage generator generates the LCD drive voltage VC5 from the V voltage output by the supply voltage booster circuit. The VC5 voltage generator includes a 64-level programmable voltage control and a software adjustable resistor with 7 different resistances to provide a voltage fine adjustment function. This function is used to adjust the contrast of the LCD panel. LSEL2 b a + eference voltage generator VSS LEV5 VC5 Fig Configuration of VC5 voltage generator The programmable voltage control can be adjusted within level to level 63 using the VC5 voltage control register LEVLEV5. The resistance ratio "(a + b)/a" can be selected as listed in Table using the VC5 voltage generator resistance ratio adjustment register LSELLSEL2. Table Adjusting resistance ratio in VC5 voltage generator LSEL2 LSEL LSEL (a+b)/a Not allowed See Chapter 9, "Electrical Characteristics", for the VC5 voltage adjustment values. The VC5 voltage generator is activated by writing "" to the VC5 voltage generator ON/OFF control register VC5ON and is deactivated by writing "" VC4 voltage generator The VC4 voltage generator generates the LCD drive voltages VC, VC2, VC3, and VC4 by dividing the VC5 voltage output from the VC5 voltage generator with resistors. These voltages are supplied to the LCD driver circuit via a voltage follower circuit. Furthermore, the LCD bias select register LBIAS is provided to select the LCD bias ratio from /7 bias or /9 bias. See Chapter 9, "Electrical Characteristics", for the voltage values. The VC4 voltage generator is activated by writing "" to the VC4 voltage generator ON/OFF control register VCON and is deactivated by writing "". 28 EPSON SC88655 TECHNICAL MANUAL

37 4 POWE SUPPLY LCD drive power supply circuit control procedure The supply voltage booster circuit, VC5 voltage generator, and VC4 voltage generator should be activated in the procedure as shown in Figure Turn OSC oscillation circuit or programmable timer 5 ON LCDCS = "", "", or "" Turn display timing generator ON LBON = "" Display clock is generated. Voltage booster clock is generated. Turn supply voltage booster ON V is generated. LSEL2 = arbitrary, LEV5 = arbitrary, VC5ON = "" Turn VC5 voltage generator ON VC5 is generated. LBIAS = arbitrary, VCON = "" Turn VC4 voltage generator ON VC4 are generated. LCDON = "" Turn LCD driver circuit ON Fig LCD drive power supply circuit control procedure Setting the LCDON register to "" starts supplying the VCVC5 voltages to the LCD driver to enable display controls. Furthermore, the LCD driver generates the CL and F signals. However, the DSPC and DSPC registers must be configured to start the LCD display. While the LCD display is turned OFF, the LCD drive power supply circuit can be deactivated to reduce current consumption. In this case, turn each circuit OFF in the reverse order of Figure except hardware reset. See chapters "8 Oscillation Circuits", "3 Programmable Timer", and "5 LCD Driver" for controlling the OSC oscillation circuit, programmable timer, and display timing generator. SC88655 TECHNICAL MANUAL EPSON 29

38 4 POWE SUPPLY 4.3 Details of Control egisters Table 4.3. shows the control bits of the power supply circuit. Table 4.3. Power supply control bits Address Bit Name Function S Comment FF9 D7 D4 D3 LCDON LBIAS VCON VC5ON LBON LCD driver circuit On/Off control LCD bias selection VC4 voltage generator On/Off control VC5 voltage generator On/Off control Supply voltage booster On/Off control On /9 bias On On On Off /7 bias Off Off Off "" when being read D LCDCS Display timing generator control D LCDCS LCDCS LCDCS Source clock P timer 5 fosc/2 fosc/ Off FFA D7 D4 D3 LSEL2 VC5 voltage generator resistance Constantly "" when being read ratio adjustment D LSEL D LSEL FFB D7 LEV5 D4 LEV4 D3 LEV3 LEV2 D LEV D LEV LSEL2 LSEL VC5 voltage control LEV5 : LEV4 : LEV3 : LSEL LEV2 : esistance ratio Not allowed LEV : LEV : Level : Constantly "" when being read LBON: FF9H Controls the supply voltage booster circuit. When "" is written: ON When "" is written: OFF eading: Valid When "" is written to LBON, the supply voltage booster circuit goes ON and outputs V by boosting the VDD in the boosting ratio set using the CAxx terminals. The V voltage is supplied to the VC5 voltage generator and VC4 voltage generator that generates the LCD drive voltages. When "" is written to LBON, the supply voltage booster circuit goes OFF. At initial reset, LBON is set to "" (OFF). VC5ON: FF9H D3 Controls the VC5 voltage generator. When "" is written: ON When "" is written: OFF eading: Valid When "" is written to VC5ON, the VC5 voltage generator goes ON and outputs the LCD drive voltage VC5. However, a V voltage higher than the desired VC5 voltage level must be supplied from the supply voltage booster circuit before the VC5 voltage can be generated. When "" is written to VC5ON, the VC5 voltage generator goes OFF. At initial reset, VC5ON is set to "" (OFF). 3 EPSON SC88655 TECHNICAL MANUAL

39 4 POWE SUPPLY VCON: FF9H D4 Controls the VC4 voltage generator. When "" is written: ON When "" is written: OFF eading: Valid When "" is written to VCON, the VC4 voltage generator goes ON and outputs the LCD drive voltages VCVC4. However, the VC5 voltage must be supplied from the VC5 voltage generator before these voltages can be generated. When "" is written to VCON, the VC4 voltage generator goes OFF. At initial reset, VCON is set to "" (OFF). Note: While the LCD panel is turned OFF, the LCD drive power supply circuit should be turned OFF to reduce current consumption using LBON, VC5ON, and VCON. LBIAS: FF9H Selects the bias ratio for LCD drive. When "" is written: /9 bias When "" is written: /7 bias eading: Valid When "" is written to LBIAS, /9 bias is selected and when "" is written, /7 bias is selected. This setting controls the VC4 voltage generator outputs. At initial reset LBIAS is set to "" (/9 bias). LSELLSEL2: FFAH D Selects a resistance ratio to adjust the output voltage of the VC5 voltage generator. Table Adjusting resistance ratio in VC5 voltage generator LSEL2 LSEL LSEL (a+b)/a Not allowed Precautions () Be sure not to use the voltages output from the VD and V terminals for driving external circuits. The VCVC5 terminal outputs can only be used to drive a recommended LCD driver. (2) The supply voltage booster circuit must be configured so that the V voltage level is higher than the desired VC5. However, make sure that the V voltage does not exceed the absolute maximum rating (see Chapter 9, "Electrical Characteristics") when setting the boosting ratio. At initial reset, LSEL is set to "". LEVLEV5: FFBH D Adjusts the reference voltage for the VC5 voltage generator in 64 levels ( to 63). The contrast of the LCD panel can be adjusted with both this register and the LSELLSEL2 register. See Chapter 9, "Electrical Characteristics", for relationship between the setting values and the VC5 voltage values. At initial reset, LEV is set to "". SC88655 TECHNICAL MANUAL EPSON 3

40 5 INITIAL ESET 5 INITIAL ESET An initial reset must be applied to the SC88655 to initialize the internal circuits. This chapter describes the internal initial reset circuits and default values of the CPU registers. 5. Configuration of Initial eset Circuit The SC88655 handles two internal reset signals for system reset and CPU reset. System reset The system reset signal initializes all the I/O registers and counters. When a system reset is issued, the CPU reset is issued simultaneously also. The following lists the causes of system reset: () External initial reset via the ESET terminal (2) Internal initial reset by the reset voltage detector (mask option) CPU reset The CPU reset signal resets only the CPU with the I/O register values maintained. The cause of CPU reset is as follows: () Internal initial reset by the watchdog timer overflow signal (mask option) Figure 5.. shows the configuration of the initial reset circuit. The CPU and peripheral circuits enter an reset status when a cause of initial reset occurs. When the cause of the reset is canceled, the CPU starts reset exception processing. (See the "SC88 Core CPU Manual".) When this occurs, the reset exception processing vector, Bank, HH from the program memory is read out and the program (initialization routine) which begins at the readout address is executed. 5.. ESET terminal Initial reset can be done by externally inputting a LOW level to the ESET terminal. Be sure to maintain the ESET terminal at LOW level for the regulation time after the power on to assure the initial reset. (See Chapter 9, "Electrical Characteristics".) In addition, be sure to use the ESET terminal for the first initial reset after the power is turned on. However, it is not necessary to reset the IC using the ESET terminal when the internal reset circuit is enabled by mask option. The ESET terminal is equipped with a pull-up resistor. You can select whether or not to use by mask option. Input port pull-up resistor ESET... With resistor Gate direct OSC OSC2 OSC3 OSC4 OSC oscillation circuit OSC3 oscillation circuit Mask option fosc fosc3 VDD Watchdog timer reset Divider Divider fosc/256 Watchdog timer fosc3/24 Watchdog timer overflow signal Operating clock status Mask option CPU-resetrelease clock S Q NMI CPU reset ESET eset voltage detector VDD Mask option A eset pulse delay circuit System reset Fig. 5.. Configuration of initial reset circuit 32 EPSON SC88655 TECHNICAL MANUAL

41 5 INITIAL ESET 5..2 eset voltage detector (VD) The SC88655 has a built-in reset voltage detector that can be enabled by mask option. This circuit has a power-on reset function that issues a system reset when the power supply is turned OFF or the supply voltage drops as well as when the power supply is turned ON. eset voltage detector Not Use Use When "Use" is selected by mask option, the reset voltage detector asserts the reset signal immediately after power is turned on until the supply voltage VDD reaches the reset release level. Furthermore, when the power is turned OFF or the supply voltage drops, the reset voltage detector asserts the reset signal after the supply voltage VDD drops under the reset level. There is a hysteresis error between the reset release level and the reset level. The reset voltage detector contains a function to hold reset status for a certain time to make sure the IC resets even if there is an instantaneous power interruption or a power surge. Note that current consumption increases when the reset voltage detector is used. See Chapter 9, "Electrical Characteristics", for the reset level, reset release level, hysteresis and current consumption. eset release level VDD eset voltage detector output eset signal negated eset level Fig eset output from reset voltage detector 5..3 Watchdog timer overflow signal The watchdog timer overflow signal can be used as a CPU reset signal by mask option. Watchdog timer overflow signal Interrupt(NMI) eset When "eset" is selected, the watchdog timer overflow signal will reset only the CPU (it does not initialize the register values of the peripheral circuits). The reset signal output from the watchdog timer is negated without waiting for oscillation stabilization time Initial reset sequence Even if the ESET terminal input or internal reset circuit negates the reset signal after power is turned on, the CPU's reset status continues (or the CPU does not starts up) until the oscillation stabilization waiting time (52/fOSC3 sec.) has elapsed. Figure shows the operating sequence following initial reset release. The CPU starts operating in synchronization with the OSC3 clock after reset status is released. Note: The oscillation stabilization time described in this section does not include oscillation start time. Therefore the time interval until the CPU starts executing instructions after power is turned on or SLEEP status is cancelled may be longer than that indicated in the figure below. When the reset voltage detector is used, it is not necessary to perform initial reset using the ESET terminal. However, both the ESET terminal and the reset voltage detector can be used for initial reset. fosc3 eset signal (at A in Figure 5..) System reset eset release clock eset released Delay time CPU reset Internal address bus Internal data bus Internal read signal 52/fOSC3 [sec] CPU reset released PC PC PC - Dummy Dummy VECL Oscillation stable waiting time Dummy cycle eset exception processing eset status is maintained during this period. Fig Initial reset sequence SC88655 TECHNICAL MANUAL EPSON 33

42 5 INITIAL ESET 5.2 Initial Settings After Initial eset The CPU internal registers are initialized as follows during initial reset. Table 5.2. Initial settings egister name Code Bit length Setting value Data register A Data register B Index (data) register L Index (data) register H Index register IX Index register IY Program counter Stack pointer Base register Zero flag Carry flag Overflow flag Negative flag Decimal flag Unpack flag Interrupt flag Interrupt flag New code bank register Code bank register Expand page register Expand page register for IX Expand page register for IY A B L H IX IY PC SP B Z C V N D U I I NB CB EP XP YP Undefined Undefined Undefined Undefined Undefined Undefined Undefined* Undefined Undefined H Undefined* H H H * eset exception processing loads the preset values stored in bank, HH into the PC. At the same time, H of the NB initial value is loaded into CB. Initialize the registers which are not initialized at initial reset using software. Since the internal AM and display data AM are not initialized at initial reset, be sure to initialize using software. The respectively stipulated initializations are done for internal peripheral circuits. If necessary, the initialization should be done using software. For initial values at initial reset, see Section 3.5, "I/ O Memory", and peripheral circuit descriptions in the following chapters. 34 EPSON SC88655 TECHNICAL MANUAL

43 The system controller is a management unit which sets such items as the bus mode in accordance with memory system configuration factors. For the purposes of controlling the system, the following settings can be performed in software: () Bus and CPU mode settings (2) Chip enable (CE) signal output settings (3) WAIT state settings for external memory (4) Page address setting of the stack pointer Below is a description of the how these settings are to be made. 6. Configuration of External Bus The SC88655 has bus terminals that can address a maximum of M 4 bytes and memory (and other) devices can be externally expanded according to the range of each bus mode described in the previous section. SC88655 BEQ BACK D W CE CE CE2 CE3 Address bus (AA9) External device External device 6 SYSTEM CONTOLLE AND BUS CONTOL 6 SYSTEM CONTOLLE AND BUS CONTOL External device Data bus (DD7) Fig. 6.. External bus lines External device Address bus The SC88655 possesses a 2-bit external address bus (AA9). The address bus terminals AA9 are shared with output ports 7 (=AA7), 7 (=A8A5) and 223 (=A6A9), switching between these functions being determined by the bus mode setting. When set as address bus, the data register and high impedance control register of each output port can be used as a general-purpose data register with read/write capabilities. Data bus The SC88655 possesses an 8-bit external data bus (DD7). The data bus terminals DD7 are shared with I/O ports PP7, switching between these functions being determined by the bus mode setting. When set as data bus, the data register and I/O control register of each I/O port can be used as a general-purpose data register with read/write capabilities. The data bus can be pulled up to high during input mode using the built-in pull-up resistor. This pull-up resistor is enabled or disabled using the pull-up control register and mask option. See Chapter, "I/O Ports (P Ports)" for details. ead (D)/write (W) signals The read (D)/write (W) signal output terminals directed to external devices are shared respectively with the output ports 24 and 25, switching between these functions being determined by the bus mode setting. When set as read (D)/write (W) signal output terminals, the data register and high impedance control register for each output port (24, 25) can be used as a general-purpose data register with read/write capabilities. The read (D)/write (W) signals are output only when an external memory is accessed When accessing the internal memory area, these signals are not output outside the IC. Chip enable (CE) signal The SC88655 is equipped with an address decoder which can output four different chip enable (CE) signals. Consequently, four devices equipped with a chip enable (CE) or chip select (CS) terminal can be directly connected without any external address decoder circuit. The four chip enable (CECE3) signal output terminals are shared with the output ports 3 33, either the chip enable (CE) output or general-purpose output can be selected in each bit with software (except for single chip mode). When set for chip enable (CE) output, the data register and high impedance control register for each output port can be used as a generalpurpose data register with read/write capabilities. The chip enable (CE) signals are output only when an external memory is accessed. When accessing the internal memory area, these signals are not output to outside the IC. See Table 6.3. for the address ranges that are assigned to the chip enable (CE) signals. SC88655 TECHNICAL MANUAL EPSON 35

44 6 SYSTEM CONTOLLE AND BUS CONTOL 6.2 Bus Mode and CPU Mode 6.2. Bus mode In order to set bus specifications to match the configuration of external expanded memory, two different bus modes described below are selectable using the bus mode setting register BUSMOD. () Single chip mode (BUSMOD = "") (2) Expansion mode (BUSMOD = "") Single chip mode The single chip mode setting applies when the SC88655 is used as a single chip microcomputer without external expanded memory. Since this mode uses the internal OM, the system can only be operated in the MCU mode. In the MPU mode, the system cannot be set to the single chip mode. Since there is no need for an external bus line in this mode, terminals normally set for bus use can be used as general-purpose output ports or I/O ports. Address space 8FFFFH Internal font data OM H (52KB) FFFFH I/O memory FFH FEFFH Unused ECH EBFFH Display data AM E8H (KB) E7FFH Unused E4H E3FFH Display data AM EH (KB) DFFFH Internal AM CH (8KB) BFFFH Internal OM (48KB) H 64KB space Pin configuration Pin name P P7 P24 P25 Function P P7 P24 P25 Fig Memory map for single chip mode Expansion mode The expansion mode setting applies when the SC88655 is used with up to M bytes 4 of external expanded memory. Because internal OM is being used in the MCU mode, external devices can be assigned to the area from H to 4FFFFFH. Since the internal OM area is released in the MPU mode, external devices can be assigned to the area from H to 3FFFFFH. However, the area from CH to FFFFH is assigned to internal memory and cannot be used to access an external device. 4FFFFFH 4H 3FFFFFH 3H 2FFFFFH 2H FFFFFH H FFFFFH 9H 8FFFFH H FFFFH FFH FEFFH ECH EBFFH E8H E7FFH E4H E3FFH EH DFFFH CH BFFFH H Address space External memory CE area External memory CE3 area External memory CE2 area External memory CE area Unused Internal font data OM (52KB) I/O memory Unused Display data AM (KB) Unused Display data AM (KB) Internal AM (8KB) Internal OM (48KB) MB space MB space MB space MB space MB space Pin configuration Pin name P P7 P24 P25 Function A A7 A8 A5 A6 A9 D W 3/CE 3/CE 32/CE2 33/CE3 D D7 P24/BEQ P25/BACK Fig Memory map for MCU expansion mode 3FFFFFH 3H 2FFFFFH 2H FFFFFH H FFFFFH H FFFFH FFH FEFFH ECH EBFFH E8H E7FFH E4H E3FFH EH DFFFH CH BFFFH H Address space External memory CE3 area External memory CE2 area External memory CE area External memory CE area I/O memory Unused Display data AM (KB) Unused Display data AM (KB) Internal AM (8KB) External memory CE area MB space MB space MB space MB space Pin configuration Pin name P P7 P24 P25 Function A A7 A8 A5 A6 A9 D W CE 3/CE 32/CE2 33/CE3 D D7 P24/BEQ P25/BACK Fig Memory map for MPU expansion mode 36 EPSON SC88655 TECHNICAL MANUAL

45 6 SYSTEM CONTOLLE AND BUS CONTOL CPU mode The CPU allows software to select its operating mode from two types shown below according to the programming area size. Use the CPU mode setting register CPUMOD for selection. () Minimum mode (CPUMOD = "") (2) Maximum mode (CPUMOD = "") Minimum mode The program area is configured within 64K bytes in any one-bank. However, the bank to be used must be specified in the CB register and cannot be changed after an initialization. This mode does not push the CB register contents onto the stack when a subroutine is called. It makes it possible to economize on stack area usage. Maximum mode The program area can be configured exceeding 64K bytes. However the CB register must be setup when the program exceeds a bank boundary every 64K bytes. This mode pushes the CB register contents when a subroutine is called. Table lists the configuration of MCU/MPU mode, bus mode, and CPU mode. Mode set after initial reset At initial reset, the bus mode (CPU mode) is set as explained below. In MCU mode: At initial reset, the SC88655 is set in single chip mode (minimum). Accordingly, in MCU mode, even if a memory has been externally expanded, the system is activated by the program stored in the internal OM. In the system with externally expanded memory, perform the applicable bus mode settings during the initialization routine originating in the internal OM. In MPU mode: At initial reset, the SC88655 is set in expansion mode (minimum). Therefore, the internal OM will be disabled. MCU/MPU terminal (MCU mode) (MPU mode) Table Setting bus mode and CPU mode Setting value BUSMOD CPUMOD Bus mode CPU mode Configuration of external memory Expansion Single chip Expansion Maximum Minimum Maximum Minimum Maximum Minimum Maximum Minimum OM+AM>64K bytes (Program 64K bytes) OM+AM>64K bytes (Program<64K bytes) None (Program 64K bytes) None (Program<64K bytes) OM+AM>64K bytes (Program 64K bytes) OM+AM>64K bytes (Program<64K bytes) OM+AM>64K bytes (Program 64K bytes) OM+AM>64K bytes (Program<64K bytes) SC88655 TECHNICAL MANUAL EPSON 37

46 6 SYSTEM CONTOLLE AND BUS CONTOL 6.3 Address Decoder (CE) Settings The SC88655 is equipped with address decoders that can output a maximum of four chip enable signals (CECE3) to external devices. At initial reset, the CECE3 terminals are set as output port terminals (333). For this reason, when operating in expansion mode, the ports to be used as CE signal output terminals must be configured. This setting is performed through software which writes "" to registers CECE3 correspond- ing the CE signals to be used. However, in the MPU mode the 3 terminal is always configured as the CE output port. Table 6.3. shows the address range assigned to the four chip enable (CE) signals. Table 6.3. Address settings of CECE3 Mode MCU expansion mode MPU expansion mode CE signal CE CE CE2 CE3 CE CE CE2 CE3 Address 4H4FFFFFH HFFFFFH 2H2FFFFFH 3H3FFFFFH HBFFFH HFFFFFH HFFFFFH 2H2FFFFFH 3H3FFFFFH The arrangement of memory space for external devices does not necessarily have to be continuous from a subordinate address and any of the chip enable signals can be used to assign areas in memory. However, in the MPU mode, program memory must be assigned to CE. The CE signals are output only when the appointed external memory area is accessed and are not output when internal memory is accessed. Note: The CE signals will be inactive status when the chip enters the standby mode (HALT mode or SLEEP mode). 6.4 WAIT State Settings In order to insure accessing of external low speed devices during high speed operations, the SC88655 is equipped with a WAIT function which prolongs access time. (See the "SC88 Core CPU Manual" for details of the WAIT function.) The number of wait states inserted can be selected from a choice of eight as shown in Table 6.4. using the WAIT state control register WTWT2. Table 6.4. Setting number of WAIT states WT2 WT WT Number of inserted states No wait * The length of one state is a /2 clock cycle. WAIT states set in software are inserted between bus cycle states T3T4. Note, however, that WAIT states cannot be inserted when an internal register and internal memory are being accessed and when operating with the OSC oscillation circuit. Consequently, WAIT state settings in single chip mode are meaningless. Figures 6.4. and show the memory read/ write timing charts. 38 EPSON SC88655 TECHNICAL MANUAL

47 6 SYSTEM CONTOLLE AND BUS CONTOL CLK T T2 T3 T4 T T2 T3 T4 AA9 Address Address CE CE W D DD7 ead data Write data ead cycle Write cycle Fig Memory read/write cycle (no wait state) WAIT (4 states inserted) WAIT (4 states inserted) CLK T T2 T3 Tw Tw2 Tw Tw2 T4 T T2 T3 Tw Tw2 Tw Tw2 T4 AA9 CE CE W D DD7 Address ead data Address Write data ead cycle Write cycle Fig Memory read/write cycle (with wait state) SC88655 TECHNICAL MANUAL EPSON 39

48 6 SYSTEM CONTOLLE AND BUS CONTOL 6.5 Setting Bus Authority elease equest Signal The SC88655 is equipped with a bus authority release function on request from an external device so that DMA (Direct Memory Access) transfer can be conducted between external devices. The internal memory cannot be accessed by this function. There are two terminals used for this function: the bus authority release request signal (BEQ) input terminal and the bus authority release acknowledge signal (BACK) output terminal. The BEQ input terminal is shared with the P24 port and the BACK output terminal with the P25 port. At initial reset, these terminal facilities are set as I/O port terminals. The terminals can be altered to function as BEQ/BACK terminals by writing "" to register EB. In the single chip mode, or when using a system which does not require bus authority release, EB must be fixed at "". When the bus authority release request (BEQ = LOW) is received from an external device, the SC88655 switches the address bus, data bus, D/ W signal, and CE signal lines to a high impedance state, outputs a LOW level from the BACK terminal and releases bus authority. As soon as a LOW level is output from the BACK terminal, the external device can use the external bus. When DMA is completed, the external device returns the BEQ terminal to HIGH and releases bus authority. Figure 6.5. shows the bus authority release sequence. During bus authority release state, internal memory cannot be accessed from the external device. In cases where external memory has areas which overlap areas in internal memory, the external memory areas can be accessed accordance with the CE signal output by the external device. Note: Be careful with the system, such that an external device does not become the bus master, other than during the bus release status. After setting the BEQ terminal to LOW level, hold the BEQ terminal at LOW level until the BACK terminal becomes LOW level. If the BEQ terminal is returned to HIGH level, before the BACK terminal becomes LOW level, the shift to the bus authorization release status will become indefinite. 6.6 Stack Page Setting Although the stack area used to evacuate registers during subroutine calls can be arbitrarily moved to any area in data AM using the stack pointer SP, its page address is set in registers SPPSPP7 in I/O memory. At initial reset, SPPSPP7 are set to "H" (page ). Since the internal AM is arranged on page (CHDFFFH), the stack area in single chip mode is inevitably located in page. In order to place the stack area at the final address in internal AM, the stack pointer SP is placed at an initial setting of "EH". (SP is pre-decremented.) In the expansion mode, to place the stack in external expanded AM, set a corresponding page to SPPSPP7. The page addresses to which SPP SPP7 can be set are H27H and must be within a AM area. * A page is each recurrent 64K division of data memory beginning at address zero. CLK Tw2 T4 T T2 T3 Tw Tw2 T4 Tz Tz2 Tz Tz2 Tz Tz2 Tz Tz2 T T2 T3 AA9 IX HL PC DD7 (IX) (IX) ANY W D BEQ L L L L H BACK Program execution status Bus authority release status Program execution status LD [HL],[IX] Fig Bus authority release sequence 4 EPSON SC88655 TECHNICAL MANUAL

49 6.7 Details of Control egisters WT D4 WT WT2 WT WT D3 CLKCHG CPU operating clock switch D D SOSC3 SOSC OSC3 oscillation On/Off control OSC oscillation On/Off control 6 SYSTEM CONTOLLE AND BUS CONTOL Table 6.7. shows the control bits for the system controller. Table 6.7. System controller control bits Address Bit Name Function S Comment FF (MCU) D7 BUSMOD Bus mode CPUMOD CPU mode Expansion Maximum Single chip Minimum D4 Constantly "" when being read D3 CE3 CE3 (33) CE3 enable CE3 disable In Single chip mode, CE signal output Enable/Disable CE2 CE2 (32) CE2 enable CE2 disable these setting are fixed Enable: CE signal output D CE CE (3) CE enable CE disable at DC output. Disable: DC (3x) output D CE CE (3) CE enable CE disable FF (MPU) D7 BUSMOD Bus mode CPUMOD CPU mode Expansion Maximum Minimum Expansion mode only D4 Constantly "" when being read D3 CE3 CE3 (33) CE3 enable CE3 disable CE signal output Enable/Disable CE2 CE2 (32) CE2 enable CE2 disable Enable: CE signal output D CE CE (3) CE enable CE disable Disable: DC (3x) output D CE CE (3) CE enable FF D7 D4 SPP7 SPP6 SPP5 SPP4 Stack pointer page address < SP page allocatable address > Single chip mode: only page (MSB) D3 D SPP3 SPP2 SPP Expansion mode: 27H page D SPP (LSB) FF2 D7 EB Bus release enable register P24 BEQ (P24 and P25 terminal specification) P25 BACK WT2 Wait control register Number of state No wait OSC3 On On OSC Off Off "" when being read 2 3 CLKCHG cannot be set to "" when SOSC = "" (OSC oscillation is OFF) and cannot be set to "" when SOSC3 = "" (OSC3 oscillation is OFF). 2 Cannot be turned OFF when the CPU is running with the OSC3 clock. 3 Cannot be turned OFF when the CPU is running with the OSC clock or the watchdog timer is enabled. Note: All the interrupts including NMI are disabled, until you write the optional value into both the "FFH" and "FFH" addresses. SC88655 TECHNICAL MANUAL EPSON 4

50 6 SYSTEM CONTOLLE AND BUS CONTOL BUSMOD, CPUMOD: FFH D7, Bus mode and CPU mode are set as shown in Table Table Bus mode and CPU mode settings MCU/MPU Setting value Bus mode CPU mode terminal BUSMOD CPUMOD (MCU mode) (MPU mode) Expansion Maximum Minimum Single Maximum chip Minimum Expansion Maximum Minimum Maximum Minimum The single chip mode configuration is only possible when this IC is used in the MCU mode. The single chip mode setting is incompatible with the MPU mode, since this mode does not utilize internal OM. At initial reset, in the MCU mode the unit is set to single chip (minimum) mode and in the MPU mode the expansion (minimum) mode is used to select the applicable mode. CECE3: FFH DD3 Sets the CE output terminals being used. When "" is written: CE output enable When "" is written: CE output disable eading: Valid CE output is enabled when a "" is written to registers CECE3 which correspond to the CE output being used. A "" written to any of the registers disables CE signal output from that terminal and it reverts to its alternate function as an output port terminal (333). In the MPU mode, CE is fixed at "" as a read-only register. At initial reset, register CE is set to "" in the MCU mode and in the MPU mode, "" is set in the register. egisters CECE3 are set to "" regardless of the MCU/MPU mode setting. Note: To avoid a malfunction from an interrupt generated before the bus configuration is initialized, all interrupts including NMI are masked until you write an optional value into address "FFH". SPPSPP7: FFH Sets the page address of stack area. In single chip mode, set page address to "H". In expansion mode, it can be set to any value within the range "H""27H". Since a carry and borrow from/to the stack pointer SP is not reflected in register SPP, the upper limit on continuous use of the stack area is 64K bytes. At initial reset, this register is set to "H" (page ). Note: To avoid a malfunction from an interrupt generated before the bus configuration is initialized, all interrupts including NMI are disabled, until you write an optional value into "FFH" address. Furthermore, to avoid generating an interrupt while the stack area is being set, all interrupts including NMI are disabled in one instruction execution period after writing to address "FFH". WTWT2: FF2H D4 How WAIT state settings are performed. The number of WAIT states to be inserted based on register settings is as shown in Table Table Setting WAIT states WT2 WT WT Number of inserted states No wait * The length of one state is a /2 clock cycle. At initial reset, this register is set to "" (no wait). EB: FF2H D7 Sets the BEQ/BACK terminals function. When "" is written: BEQ/BACK enabled When "" is written: BEQ/BACK disabled eading: Valid How BEQ and BACK terminal functions are set. Writing "" to EB enables BEQ/BACK input/ output. Writing "" sets the BEQ terminal as the P24 port terminal and the BACK terminal as the P25 port terminal. At initial reset, EB is set to "" (BEQ/BACK disabled). 42 EPSON SC88655 TECHNICAL MANUAL

51 6 SYSTEM CONTOLLE AND BUS CONTOL 6.8 Precautions () All the interrupts including NMI are masked, until you write the optional value into both the "FFH" and "FFH" addresses. Consequently, even if you do not change the content of this address (You use the initial value, as is.), you should still be sure to perform the writing operation using the initialization routine. (2) When setting stack fields, including page addresses as well, you should write them in the order of the register SPP ("FFH") and the stack pointer SP. Example: When setting the "78H" address LD EP, #H LD HL, #FFH LD [HL], #7H LD SP, #8H During this period the interrupts (including NMI) are masked. SC88655 TECHNICAL MANUAL EPSON 43

52 7 INTEUPT AND STANDBY STATUS 7 INTEUPT AND STANDBY STATUS Types of interrupts 4 systems and 34 types of interrupts have been provided for the SC External interrupt P2P27 input interrupt (8 types) Internal interrupt Clock timer interrupt (4 types) Programmable timer interrupt (6 types) Serial interface interrupt (6 types) Each interrupt source provides an interrupt factor flag that indicates occurrence of an interrupt factor and an interrupt enable register that enables/disables interrupt requests for controlling interrupt generation. In addition, an interrupt priority register has been provided for each interrupt system allowing interrupt handler routines to set the priority of each interrupt system to 3 levels. Figure 7. shows the configuration of the interrupt circuit. efer to the explanations of the respective peripheral circuits for details on each interrupt. HALT mode When the program executes the HALT instruction, the SC88655 enters HALT mode. Since the CPU stops operating in HALT mode, power consumption can be reduced with only peripheral circuit operation. The HALT mode is cancelled by initial reset or an interrupt request, and the CPU restarts program execution from an exception handler routine. See the "SC88 Core CPU Manual" for the HALT mode and reactivation sequence. SLEEP mode When the program executes the SLP instruction, the SC88655 enters SLEEP mode. Since the CPU and peripheral circuits stop operating completely in SLEEP mode, power consumption can be reduced even more than in HALT mode. The SLEEP mode is cancelled by initial reset or an input interrupt from the port. The CPU reactivates after waiting 28/fOSC or 52/fOSC3 seconds of oscillation stabilization time (the oscillation stabilization time varies depending on the operating clock being used when the SLP instruction is executed). At this time, the CPU restarts program execution from an exception handler routine (input interrupt routine). Note: The oscillation becomes unstable for a while after SLEEP status is cancelled, the wait time for restarting the CPU may be longer than 28/fOSC or 52/fOSC3 seconds. 7. Interrupt Generation Conditions The interrupt factor flags that indicate occurrence of their respective interrupt factors are provided for the previously indicated 4 systems and 34 types of interrupts. They will be set to "" when the corresponding interrupt factor occurs. In addition, interrupt enable registers with a to correspondence to each of the interrupt factor flags are provided. An interrupt is enabled when "" is written and interrupt is disabled when "" is written. The CPU manages the enable/disable of interrupt requests at the interrupt priority level. An interrupt priority register that sets the priority level is provided for each of the interrupts of the 4 systems and the CPU accepts only interrupts above the level that has been indicated with the interrupt flags (I and I). Consequently, the following three conditions are necessary for the CPU to accept the interrupt. () The interrupt factor flag has been set to "" by generation of an interrupt factor. (2) The interrupt enable register corresponding to the above has been set to "". (3) The interrupt priority register corresponding to the above has been set to a priority level higher than the interrupt flag (I and I) setting. The CPU initially samples the interrupt for the first op-code fetch cycle of each instruction. Thereupon, the CPU shifts to the exception processing when the above mentioned conditions have been established. See the "SC88 Core CPU Manual" for the exception processing sequence. 44 EPSON SC88655 TECHNICAL MANUAL

53 7 INTEUPT AND STANDBY STATUS Interrupt factor flag Interrupt enable register Interrupt priority register Port P27 P26 P25 P24 P23 P22 P2 P2 FP27 EP27 FP26 EP26 FP25 EP25 FP24 EP24 FP23 EP23 FP22 EP22 FP2 EP2 FP2 EP2 Interrupt vector address generation circuit PP2 PP2 Vector address Data bus Programmable timer Programmable timer Programmable timer 2 Programmable timer 3 Programmable timer 4 Programmable timer 5 Programmable timer 6 Programmable timer 7 Underflow Compare match Underflow Compare match Underflow Compare match Underflow Compare match Underflow Compare match Underflow Compare match Underflow Compare match Underflow Compare match FTU ETU FTC ETC FTU ETU FTC ETC FTU2 ETU2 FTC2 ETC2 FTU3 ETU3 FTC3 ETC3 FTU4 ETU4 FTC4 ETC4 FTU5 ETU5 FTC5 ETC5 FTU6 ETU6 FTC6 ETC6 FTU7 ETU7 FTC7 ETC7 PPT PPT PPT2 PPT3 PPT4 PPT5 PPT6 PPT7 Interrupt priority level judgment circuit IQ3 IQ2 IQ Serial interface Error eceive Transmit FSE ESE FSEC ESEC FSTA ESTA PSIF PSIF Serial interface Error eceive Transmit FSE ESE FSEC ESEC FSTA ESTA PSIF PSIF 32 Hz FTM32 ETM32 Clock timer 8 Hz 2 Hz Hz FTM8 ETM8 FTM2 ETM2 FTM ETM PTM PTM Fig. 7. Configuration of interrupt circuit SC88655 TECHNICAL MANUAL EPSON 45

54 7 INTEUPT AND STANDBY STATUS 7.2 Interrupt Factor Flag Table 7.2. shows the correspondence between the factors generating an interrupt and the interrupt factor flags. The corresponding interrupt factor flags are set to "" by generation of the respective interrupt factors. The corresponding interrupt factor can be confirmed by reading the flags through software. Interrupt factor flag that has been set to "" is reset to "" by writing "". At initial reset, the interrupt factor flags are reset to "". Note: Table 7.2. Interrupt factors Interrupt factor P27 input (falling edge or rising edge specified with PCP27) P26 input (falling edge or rising edge specified with PCP26) P25 input (falling edge or rising edge specified with PCP25) P24 input (falling edge or rising edge specified with PCP24) P23 input (falling edge or rising edge specified with PCP23) P22 input (falling edge or rising edge specified with PCP22) P2 input (falling edge or rising edge specified with PCP2) P2 input (falling edge or rising edge specified with PCP2) Programmable timer compare match Programmable timer underflow Programmable timer underflow Programmable timer compare match Programmable timer 2 underflow Programmable timer 2 compare match Programmable timer 3 underflow Programmable timer 3 compare match Programmable timer 4 underflow Programmable timer 4 compare match Programmable timer 5 underflow Programmable timer 5 compare match Programmable timer 6 underflow Programmable timer 6 compare match Programmable timer 7 underflow Programmable timer 7 compare match Serial interface receiving error (in asynchronous mode) Serial interface receiving completion Serial interface transmitting completion Serial interface receiving error (in asynchronous mode) Serial interface receiving completion Serial interface transmitting completion Clock timer 32 Hz signal (falling edge) Clock timer 8 Hz signal (falling edge) Clock timer 2 Hz signal (falling edge) Clock timer Hz signal (falling edge) When executing the ETE instruction without resetting the interrupt factor flag after an interrupt has been generated, the same interrupt will be generated. Consequently, the interrupt factor flag corresponding to that routine must be reset (writing "") in the interrupt processing routine. Interrupt factor flag FP27 FP26 FP25 FP24 FP23 FP22 FP2 FP2 FTC FTU FTU FTC FTU2 FTC2 FTU3 FTC3 FTU4 FTC4 FTU5 FTC5 FTU6 FTC6 FTU7 FTC7 FSE FSEC FSTA FSE FSEC FSTA FTM32 FTM8 FTM2 FTM FFAH D7 FFAH FFAH FFAH D4 FFAH D3 FFAH FFAH D FFAH D FFBH D FFBH D FFBH FFBH D3 FFBH D4 FFBH FFBH FFBH D7 FFEH D FFEH D FFEH FFEH D3 FFEH D4 FFEH FFEH FFEH D7 FFCH FFCH D FFCH D FFCH FFCH D4 FFCH D3 FFDH D3 FFDH FFDH D FFDH D 46 EPSON SC88655 TECHNICAL MANUAL

55 7.3 Interrupt Enable egister The interrupt enable register has a to correspondence with each interrupt factor flag and enable/ disable of interrupt requests can be set. When "" is written to the interrupt enable register, an interrupt request is enabled, and is disabled when "" is written. 7 INTEUPT AND STANDBY STATUS This register also permits reading, thus making it possible to confirm that a status has been set. At initial reset, the interrupt enable registers are set to "" and shifts to the interrupt disable status. Table 7.3. shows the correspondence between the interrupt enable registers and the interrupt factor flags. Table 7.3. Interrupt enable registers and interrupt factor flags Interrupt Interrupt factor flag Interrupt enable register P27 input P26 input P25 input P24 input P23 input P22 input P2 input P2 input Timer compare match Timer underflow Timer underflow Timer compare match Timer 2 underflow Timer 2 compare match Timer 3 underflow Timer 3 compare match Timer 4 underflow Timer 4 compare match Timer 5 underflow Timer 5 compare match Timer 6 underflow Timer 6 compare match Timer 7 underflow Timer 7 compare match Serial interface receiving error Serial interface receiving completion Serial interface transmitting completion Serial interface receiving error Serial interface receiving completion Serial interface transmitting completion Clock timer 32 Hz Clock timer 8 Hz Clock timer 2 Hz Clock timer Hz FP27 FP26 FP25 FP24 FP23 FP22 FP2 FP2 FTC FTU FTU FTC FTU2 FTC2 FTU3 FTC3 FTU4 FTC4 FTU5 FTC5 FTU6 FTC6 FTU7 FTC7 FSE FSEC FSTA FSE FSEC FSTA FTM32 FTM8 FTM2 FTM FFAH D7 FFAH FFAH FFAH D4 FFAH D3 FFAH FFAH D FFAH D FFBH D FFBH D FFBH FFBH D3 FFBH D4 FFBH FFBH FFBH D7 FFEH D FFEH D FFEH FFEH D3 FFEH D4 FFEH FFEH FFEH D7 FFCH FFCH D FFCH D FFCH FFCH D4 FFCH D3 FFDH D3 FFDH FFDH D FFDH D EP27 EP26 EP25 EP24 EP23 EP22 EP2 EP2 ETC ETU ETU ETC ETU2 ETC2 ETU3 ETC3 ETU4 ETC4 ETU5 ETC5 ETU6 ETC6 ETU7 ETC7 ESE ESEC ESTA ESE ESEC ESTA ETM32 ETM8 ETM2 ETM FF4H D7 FF4H FF4H FF4H D4 FF4H D3 FF4H FF4H D FF4H D FF5H D FF5H D FF5H FF5H D3 FF5H D4 FF5H FF5H FF5H D7 FF8H D FF8H D FF8H FF8H D3 FF8H D4 FF8H FF8H FF8H D7 FF6H FF6H D FF6H D FF6H FF6H D4 FF6H D3 FF7H D3 FF7H FF7H D FF7H D SC88655 TECHNICAL MANUAL EPSON 47

56 7 INTEUPT AND STANDBY STATUS 7.4 Interrupt Priority egister and Interrupt Priority Level Interrupt P2P27 input interrupt Programmable timer interrupt Programmable timer interrupt 32 Programmable timer interrupt 54 Programmable timer interrupt 76 Serial interface interrupt Serial interface interrupt Clock timer interrupt Table 7.4. Interrupt priority register Interrupt priority register PP2, PP2 PPT, PPT PPT2, PPT3 PPT4, PPT5 PPT6, PPT7 PSIF, PSIF PSIF, PSIF PTM, PTM FF D, D FF D4, FF, D3 FF, D7 FF D4, FF, D7 FF D, D FF, D3 The interrupt priority registers shown in Table 7.4. are provided for each system of interrupts and the interrupt priority levels for the CPU can be set to the optional priority level (3). As a result, it is possible to have multiple interrupts that match the system's interrupt processing priority levels. The interrupt priority level between each system can optionally be set to three levels by the interrupt priority register. However, when more than one system is set to the same priority level, they are processed according to the default priority level. Table Setting of interrupt priority level P* P* Interrupt priority level Level 3 (IQ3) Level 2 (IQ2) Level (IQ) Level (None) At initial reset, the interrupt priority registers are all set to "" and each interrupt is set to level. Furthermore, the priority levels in each system have been previously decided and they cannot be changed. The CPU can mask each interrupt by setting the interrupt flags (I and I). The relation between the interrupt priority level of each system and interrupt flags is shown in Table 7.4.3, and the CPU accepts only interrupts above the level indicated by the interrupt flags. The NMI (watchdog timer) that has level 4 priority, is always accepted regardless of the setting of the interrupt flags. Table Interrupt mask setting of CPU I I Acceptable interrupt Level 4 (NMI) Level 4, Level 3 (IQ3) Level 4, Level 3, Level 2 (IQ2) Level 4, Level 3, Level 2, Level (IQ) After an interrupt has been accepted, the interrupt flags are written to the level of that interrupt. However, interrupt flags after an NMI has been accepted are written to level 3 (I = I = ""). Table Interrupt flags after acceptance of interrupt Accepted interrupt priority level I I Level 4 (NMI) Level 3 (IQ3) Level 2 (IQ2) Level (IQ) The set interrupt flags are reset to their original value on return from the interrupt processing routine. Consequently, multiple interrupts up to 3 levels can be controlled by the initial settings of the interrupt priority registers alone. Additional multiplexing can be realized by rewriting the interrupt flags and interrupt enable register in the interrupt processing routine. Note: Beware. If the interrupt flags have been rewritten (set to lower priority) prior to resetting an interrupt factor flag after an interrupt has been generated, the same interrupt will be generated again. 48 EPSON SC88655 TECHNICAL MANUAL

57 7 INTEUPT AND STANDBY STATUS 7.5 Exception Processing Vectors When the CPU accepts an interrupt request, it starts exception processing following completion of the instruction being executed. In exception processing, the following operations branch the program. () In the minimum mode, the program counter (PC) and system condition flag (SC) are moved to stack and in the maximum mode, the code bank register (CB), PC and SC are moved. (2) The branch destination address is read from the exception processing vector corresponding to each exception processing (interrupt) factor and is placed in the PC. An exception vector is 2 bytes of data in which the top address of each exception (interrupt) processing routine has been stored and the vector addresses correspond to the exception processing factors as shown in Table Note: An exception processing vector is fixed at 2 bytes, so it cannot specify a branch destination bank address. Consequently, to branch from multiple banks to a common exception processing routine, the top portion of an exception processing routine must be described within the common area (H7FFFH). Table 7.5. Vector address and exception processing correspondence Vector Exception processing factor address H 2H 4H 6H 8H AH CH EH H 2H 4H 6H 8H AH CH EH 2H 22H 24H 26H 28H 2AH 2CH 2EH 3H 32H 34H 36H 38H 3AH 3CH 3EH 4H 42H 44H 46H 48H 4AH 4CH : FEH eset Zero division Watchdog timer (NMI) P27 input interrupt P26 input interrupt P25 input interrupt P24 input interrupt P23 input interrupt P22 input interrupt P2 input interrupt P2 input interrupt PTM 3 compare match interrupt PTM 3 underflow interrupt PTM 2 compare match interrupt PTM 2 underflow interrupt PTM compare match interrupt PTM underflow interrupt PTM underflow interrupt PTM compare match interrupt Serial I/F error interrupt Serial I/F receiving complete interrupt Serial I/F transmitting complete interrupt Serial I/F error interrupt Serial I/F receiving complete interrupt Serial I/F transmitting complete interrupt Clock timer 32 Hz interrupt Clock timer 8 Hz interrupt Clock timer 2 Hz interrupt Clock timer Hz interrupt PTM 7 compare match interrupt PTM 7 underflow interrupt PTM 6 compare match interrupt PTM 6 underflow interrupt PTM 5 compare match interrupt PTM 5 underflow interrupt PTM 4 compare match interrupt PTM 4 underflow interrupt System reserved (cannot be used) Software interrupt Priority High Low No priority rating SC88655 TECHNICAL MANUAL EPSON 49

58 7 INTEUPT AND STANDBY STATUS 7.6 Details of Control egisters Table 7.6. shows the interrupt control bits. Table 7.6.(a) Interrupt control bits Address Bit Name Function S Comment FF D7 PSIF Serial interface interrupt priority register PSIF PSIF PSIF PPT PPT PPT Programmable timer interrupt PPT3 PPT2 Priority D4 PPT priority register PP2 PP2 level D3 PPT3 Programmable timer 32 interrupt Level 3 Level 2 PPT2 priority register Level D PP2 P2P27 interrupt priority register Level D PP2 FF D7 PPT5 Programmable timer 54 interrupt PPT5 PPT4 PPT4 PPT7 priority register Programmable timer 76 interrupt PPT7 PTM PPT6 PTM Priority D4 PPT6 priority register PSIF PSIF level D3 PTM Clock timer interrupt priority register Level 3 Level 2 PTM Level D PSIF Serial interface interrupt priority register Level D PSIF FF4 D7 EP27 EP26 EP25 P27 interrupt enable P26 interrupt enable P25 interrupt enable D4 EP24 P24 interrupt enable Interrupt Interrupt D3 EP23 P23 interrupt enable enable disable D D EP22 EP2 EP2 P22 interrupt enable P2 interrupt enable P2 interrupt enable FF5 D7 ETC3 ETU3 ETC2 PTM3 compare match interrupt enable PTM3 underflow interrupt enable PTM2 compare match interrupt enable D4 ETU2 PTM2 underflow interrupt enable Interrupt Interrupt D3 ETC PTM compare match interrupt enable enable disable D D ETU ETU ETC PTM underflow interrupt enable PTM underflow interrupt enable PTM compare match interrupt enable FF6 D7 Constantly "" when being read D4 ESE Serial I/F (error) interrupt enable ESEC Serial I/F (receive) interrupt enable D3 ESTA Serial I/F (transmit) interrupt enable ESE Serial I/F (error) interrupt enable Interrupt enable Interrupt disable D D ESEC Serial I/F (receive) interrupt enable ESTA Serial I/F (transmit) interrupt enable FF7 D7 D4 D3 ETM32 Clock timer 32 Hz interrupt enable Constantly "" when being read ETM8 Clock timer 8 Hz interrupt enable Interrupt Interrupt D ETM2 Clock timer 2 Hz interrupt enable enable disable D ETM Clock timer Hz interrupt enable 5 EPSON SC88655 TECHNICAL MANUAL

59 7 INTEUPT AND STANDBY STATUS Table 7.6.(b) Interrupt control bits Address Bit Name Function S FF8 D7 ETC7 ETU7 ETC6 PTM7 compare match interrupt enable PTM7 underflow interrupt enable PTM6 compare match interrupt enable D4 ETU6 PTM6 underflow interrupt enable Interrupt Interrupt D3 ETC5 PTM5 compare match interrupt enable enable disable D D ETU5 ETC4 ETU4 PTM5 underflow interrupt enable PTM4 compare match interrupt enable PTM4 underflow interrupt enable FFA D7 FP27 FP26 FP25 P27 interrupt factor flag P26 interrupt factor flag P25 interrupt factor flag () Interrupt factor is () No interrupt factor is D4 FP24 P24 interrupt factor flag occurred occurred D3 FP23 P23 interrupt factor flag D D FP22 FP2 FP2 P22 interrupt factor flag P2 interrupt factor flag P2 interrupt factor flag (W) eset (W) No operation FFB D7 FTC3 FTU3 FTC2 PTM3 compare match interrupt factor flag PTM3 underflow interrupt factor flag PTM2 compare match interrupt factor flag () Interrupt factor is () No interrupt factor is D4 FTU2 PTM2 underflow interrupt factor flag occurred occurred D3 FTC PTM compare match interrupt factor flag D D FTU FTU FTC PTM underflow interrupt factor flag PTM underflow interrupt factor flag PTM compare match interrupt factor flag (W) eset (W) No operation FFC D7 FSE Serial I/F (error) interrupt factor flag () () D4 FSEC Serial I/F (receive) interrupt factor flag Interrupt No interrupt factor is factor is D3 FSTA Serial I/F (transmit) interrupt factor flag occurred occurred FSE Serial I/F (error) interrupt factor flag (W) (W) D FSEC Serial I/F (receive) interrupt factor flag eset No operation D FSTA Serial I/F (transmit) interrupt factor flag FFD D7 D4 D3 FTM32 Clock timer 32 Hz interrupt factor flag () () FTM8 Clock timer 8 Hz interrupt factor flag Occurred Not occurred D FTM2 Clock timer 2 Hz interrupt factor flag (W) (W) D FTM Clock timer Hz interrupt factor flag eset No operation FFE D7 FTC7 PTM7 compare match interrupt factor flag () () FTU7 PTM7 underflow interrupt factor flag Interrupt No interrupt FTC6 PTM6 compare match interrupt factor flag factor is factor is D4 FTU6 PTM6 underflow interrupt factor flag occurred occurred D3 FTC5 PTM5 compare match interrupt factor flag FTU5 PTM5 underflow interrupt factor flag (W) (W) D FTC4 PTM4 compare match interrupt factor flag eset No operation D FTU4 PTM4 underflow interrupt factor flag Comment Constantly "" when being read Constantly "" when being read SC88655 TECHNICAL MANUAL EPSON 5

60 7 INTEUPT AND STANDBY STATUS P, P : FFHFFH These are the interrupt priority registers used to set the priority level of each interrupt system. Table shows the correspondence between the register and interrupt system. Table Interrupt priority registers egister PP2, PP2 (FF D, D) PPT, PPT (FF D4, ) PPT2, PPT3 (FF, D3) PPT4, PPT5 (FF, D7) PPT6, PPT7 (FF D4, ) PSIF, PSIF(FF, D7) PSIF, PSIF(FF D, D) PTM, PTM (FF, D3) Interrupt system P2P27 input Programmable timers Programmable timers 32 Programmable timers 54 Programmable timers 76 Serial interface Serial interface Clock timer Table shows the interrupt priority level that can be set by these registers. Table Setting interrupt priority level P* P* Interrupt priority level Level 3 (IQ3) Level 2 (IQ2) Level (IQ) Level (None) To generate an interrupt, the priority level of the interrupt system must be set higher than the level set with the CPU's interrupt flag (I, I) using the interrupt priority register. Furthermore, when two or more interrupts occur at the same time, the interrupt that has the highest priority set using this register is processed first. If they have the same priority level, the priority order set to the interrupt vectors (see Table 7.5.) are applied. At initial reset, the interrupt priority registers are set to "" (level ). E : FF4HFF8H These are the interrupt enable registers that enable or disable to generate an interrupt to the CPU. Table shows the correspondence between the register and interrupt factor. EP27 EP26 EP25 EP24 EP23 EP22 EP2 EP2 ETC ETU ETU ETC ETU2 ETC2 ETU3 ETC3 ETU4 ETC4 ETU5 ETC5 ETU6 ETC6 ETU7 ETC7 ESE Table Interrupt enable registers egister (FF4H D7) (FF4H ) (FF4H ) (FF4H D4) (FF4H D3) (FF4H ) (FF4H D) (FF4H D) (FF5H D) (FF5H D) (FF5H ) (FF5H D3) (FF5H D4) (FF5H ) (FF5H ) (FF5H D7) (FF8H D) (FF8H D) (FF8H ) (FF8H D3) (FF8H D4) (FF8H ) (FF8H ) (FF8H D7) (FF6H ) ESEC (FF6H D) ESTA (FF6H D) ESE (FF6H ) ESEC (FF6H D4) ESTA (FF6H D3) ETM32 (FF7H D3) ETM8 (FF7H ) ETM2 (FF7H D) ETM (FF7H D) Interrupt factor P27 input P26 input P25 input P24 input P23 input P22 input P2 input P2 input PTM compare match PTM underflow PTM underflow PTM compare match PTM 2 underflow PTM 2 compare match PTM 3 underflow PTM 3 compare match PTM 4 underflow PTM 4 compare match PTM 5 underflow PTM 5 compare match PTM 6 underflow PTM 6 compare match PTM 7 underflow PTM 7 compare match Serial I/F receiving error Serial I/F receiving completion Serial I/F transmitting completion Serial I/F receiving error Serial I/F receiving completion Serial I/F transmitting completion Clock timer 32 Hz Clock timer 8 Hz Clock timer 2 Hz Clock timer Hz When "" is written: Interrupt enabled When "" is written: Interrupt disabled eading: Valid When the interrupt enable register is set to "", the corresponding interrupt is enabled. When the interrupt enable register is set to "", the interrupt is disabled. At initial reset, the interrupt enable register is set to "" (interrupt disabled). 52 EPSON SC88655 TECHNICAL MANUAL

61 7 INTEUPT AND STANDBY STATUS F : FFAHFFEH These are the interrupt factor flags that indicate occurrence of interrupt factors. Table shows the correspondence between the flag and interrupt factor. Table Interrupt factor flags Flag Interrupt factor FP27 (FFAH D7) P27 input FP26 (FFAH ) P26 input FP25 (FFAH ) P25 input FP24 (FFAH D4) P24 input FP23 (FFAH D3) P23 input FP22 (FFAH ) P22 input FP2 (FFAH D) P2 input FP2 (FFAH D) P2 input FTC (FFBH D) PTM compare match FTU (FFBH D) PTM underflow FTU (FFBH ) PTM underflow FTC (FFBH D3) PTM compare match FTU2 (FFBH D4) PTM 2 underflow FTC2 (FFBH ) PTM 2 compare match FTU3 (FFBH ) PTM 3 underflow FTC3 (FFBH D7) PTM 3 compare match FTU4 (FFEH D) PTM 4 underflow FTC4 (FFEH D) PTM 4 compare match FTU5 (FFEH ) PTM 5 underflow FTC5 (FFEH D3) PTM 5 compare match FTU6 (FFEH D4) PTM 6 underflow FTC6 (FFEH ) PTM 6 compare match FTU7 (FFEH ) PTM 7 underflow FTC7 (FFEH D7) PTM 7 compare match FSE (FFCH ) Serial I/F receiving error FSEC (FFCH D) Serial I/F receiving completion FSTA (FFCH D) Serial I/F transmitting completion FSE (FFCH ) Serial I/F receiving error FSEC (FFCH D4) Serial I/F receiving completion FSTA (FFCH D3) Serial I/F transmitting completion FTM32 (FFDH D3) Clock timer 32 Hz FTM8 (FFDH ) Clock timer 8 Hz FTM2 (FFDH D) Clock timer 2 Hz FTM (FFDH D) Clock timer Hz To accept the subsequent interrupt after an interrupt has generated, resetting of the interrupt flags (set interrupt flag to lower level than the level indicated by the interrupt priority registers, or execute the ETE instruction) and interrupt factor flag must be reset. The interrupt factor flag is reset to "" by writing "". At initial reset, this flag is reset to "". efer to the explanations on the respective peripheral circuits for details of the interrupt factor. When "" is read: Occurred When "" is read: Not occurred When "" is written: esets factor flag When "" is written: Invalid The interrupt factor flag is set to "" when the interrupt generation condition is met. When set in this manner, if the corresponding interrupt enable register is set to "" and the corresponding interrupt priority register is set to a higher level than the setting of interrupt flags (I and I), an interrupt will be generated to the CPU. egardless of the interrupt enable register and interrupt priority register settings, the interrupt factor flag will be set to "" by the occurrence of an interrupt factor. SC88655 TECHNICAL MANUAL EPSON 53

62 7 INTEUPT AND STANDBY STATUS 7.7 Precautions () When executing the ETE instruction without resetting the interrupt factor flag after an interrupt has been generated, the same interrupt will be generated. Consequently, the interrupt factor flag corresponding to that routine must be reset (writing "") in the interrupt processing routine. (2) Beware. If the interrupt flags (I and I) have been rewritten (set to lower priority) prior to resetting an interrupt factor flag after an interrupt has been generated, the same interrupt will be generated again. (3) An exception processing vector is fixed at 2 bytes, so it cannot specify a branch destination bank address. Consequently, to branch from multiple banks to a common exception processing routine, the front portion of an exception processing routine must be described within the common area (H7FFFH). (4) Do not execute the SLP instruction for 2 msec after a NMI interrupt has occurred (when fosc is khz). 54 EPSON SC88655 TECHNICAL MANUAL

63 8 OSCILLATION CICUITS 8 OSCILLATION CICUITS 8. Configuration of Oscillation Circuits The SC88655 is twin clock system with two internal oscillation circuits (OSC and OSC3). The OSC3 oscillation circuit generates the mainclock to run the CPU and some peripheral circuits in high speed, and the OSC oscillation circuit generates the sub-clock for low-power operation. Figure 8.. shows the configuration of the oscillation circuit. SOSC WDT enable CLKCHG SLEEP status SOSC3 OSC oscillation circuit OSCON OSCON control OSC3ON control fosc OSC3ON OSC3 oscillation circuit fosc3 Divider OSCON status Clock switching control OSC3ON status Divider To peripheral circuit To CPU To peripheral circuit Fig. 8.. Configuration of oscillation circuits 8.2 Mask Option OSC oscillation circuit Crystal oscillation circuit C oscillation circuit OSC3 oscillation circuit Crystal oscillation circuit Ceramic oscillation circuit C oscillation circuit The OSC oscillator types can be selected from crystal and C by mask option. The OSC3 oscillator types can be selected from crystal, ceramic, and C by mask option. At initial reset, the OSC3 oscillation circuit is selected for the CPU operating clock source. Turning the OSC3 oscillation circuit ON/OFF and switching of the system clock between OSC3 and OSC are controlled in software. The OSC3 oscillation circuit is utilized when the CPU and some peripheral circuits must be operated in high speed. Otherwise, OSC should be used to generate the operating clock with the OSC3 oscillation circuit stopped in order to reduce current consumption. SC88655 TECHNICAL MANUAL EPSON 55

64 8 OSCILLATION CICUITS 8.3 OSC3 Oscillation Circuit The OSC3 oscillation circuit generates the system clock to operate the CPU and some peripheral circuits in high speed. The OSC3 oscillator types can be selected from crystal, ceramic, and C by mask option. Figure 8.3. shows the configuration of the OSC3 oscillation circuit. CG3 OSC3 X'tal 3 or Ceramic fosc3 8.4 OSC Oscillation Circuit The OSC oscillation circuit generates the system clock which is utilized during low speed operation (low power mode) of the CPU and peripheral circuits. Furthermore, even when OSC3 is utilized as the system clock, OSC continues to generate the source clock for the clock timer and watchdog timer. The OSC oscillator types can be selected from crystal and C by mask option. Figure 8.4. shows the configuration of the OSC oscillation circuit. CD3 OSC4 OSC3ON VSS () Crystal/ceramic oscillation circuit CG OSC f X'tal fosc C3 OSC3 fosc3 VSS OSC2 OSCON () Crystal oscillation circuit VSS OSC4 OSC3ON OSC fosc (2) C oscillation circuit Fig OSC3 oscillation circuit When crystal or ceramic is selected, the crystal or ceramic oscillation circuit are configured by connecting a crystal oscillator (X'tal 3)/ceramic oscillator (Ceramic) between the OSC3 and OSC4 terminals, and connecting two capacitors (CG3, CD3) between the OSC3 terminal and VSS and between the OSC4 terminal and VSS, respectively. When C is selected, the C oscillation circuit is configured simply by connecting a resistor (C3) between OSC3 and OSC4 terminals. The OSC3 oscillation circuit can be turned ON or OFF using the OSC3 oscillation ON/OFF control register SOSC3. When the system does not need to run at high speed, current consumption can be reduced by turning the OSC3 oscillation OFF after switching the CPU clock to OSC. While the OSC3 clock is used as the system clock, the OSC3 oscillation circuit cannot be stopped. Also the OSC3 oscillation circuit stops when the SLP instruction is executed. C OSC2 OSCON (2) C oscillation circuit Fig OSC oscillation circuit When crystal is selected, a crystal oscillation circuit can be easily configured by connecting a crystal oscillator (X'tal ) between the OSC and OSC2 terminals along with a trimmer capacitor (CG) between the OSC terminal and VSS. When C is selected, the C oscillation circuit is configured simply by connecting a resistor (C) between OSC and OSC2 terminals. The OSC oscillation circuit can be turned ON or OFF using the OSC oscillation ON/OFF control register SOSC. If the system does not need the OSC clock when it is running with OSC3 clock, current consumption can be reduced by turning the OSC oscillation OFF. When the watchdog timer that uses the OSC clock is enabled, the OSC oscillation circuit cannot be stopped. Also the OSC oscillation circuit stops when the SLP instruction is executed. 56 EPSON SC88655 TECHNICAL MANUAL

65 8 OSCILLATION CICUITS 8.5 Switching the CPU Clock Either OSC or OSC3 can be selected as the system clock for running the CPU with software. The system can save power by turning the OSC3 oscillation circuit OFF while the CPU is running with the OSC clock. When the system needs high speed operation, turn the OSC3 oscillation circuit ON and switch the system clock from OSC to OSC3. In this case, since several msec to several tens of msec are necessary for the oscillation to stabilize after turning the OSC3 oscillation circuit ON, you should switch over the clock after stabilization time has elapsed. When switching over from the OSC3 to the OSC, turn the OSC3 oscillation circuit OFF immediately following the clock changeover. When switching the system clock from OSC3 to OSC immediately after the power is turned ON, it is necessary to wait for the OSC oscillation to stabilize before the clock can be switched. The OSC3 oscillation may take several tens of msec to several seconds until it has completely stabilized. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. efer to the oscillation start time example indicated in Chapter 9, "Electrical Characteristics".) Figure 8.5. indicates the status transition diagram for the clock changeover. Note: Be sure to wait long enough that the OSC oscillation has stabilized completely before switching the operating clock to OSC or starting the timer that uses the OSC clock after the OSC oscillation circuit is turned ON. The CPU may start operating before the OSC oscillation has stabilized when both the OSC and OSC3 oscillation circuits are turned ON since the OSC3 oscillation circuit is able to stabilize in a shorter time than the OSC oscillation circuit. Program Execution Status High speed operation 2 OSC OFF OSC3 ON CPU clock OSC3 SOSC= SOSC= ESET High speed operation CLKCHG= OSC ON OSC3 ON CPU clock OSC3 CLKCHG= Low speed operation OSC OSC3 CPU clock ON ON OSC SOSC3= SOSC3= Low speed and low power operation OSC ON OSC3 OFF CPU clock OSC * Interrupt HALT instruction * Interrupt (Input interrupt) SLP instruction HALT status OSC ON or OFF OSC3 ON or OFF CPU clock STOP SLEEP status OSC OFF OSC3 OFF CPU clock STOP Standby Status * The return destination from the standby status becomes the program execution status prior to shifting to the standby status. Fig Status transition diagram for the clock changeover SC88655 TECHNICAL MANUAL EPSON 57

66 8 OSCILLATION CICUITS 8.6 Clock Output (FOUT) In order for the SC88655 to provide a clock to an external device, a FOUT signal (oscillation clock fosc or fosc3 dividing clock) can be output from the P22 port terminal. The FOUT signal output is controlled by the register FOUTON. When FOUTON is set to "", the FOUT signal is output from the P22 port terminal, when "" is set, the port is set to the status according to the P22 port registers. While the FOUT signal is output (FOUTON is ""), settings of the I/O control register IOC22 and data register P22D become invalid. The frequency of the FOUT signal can be selected from among eight settings as shown in Table 8.6. using the registers FOUTFOUT2. Table 8.6. FOUT frequency setting FOUT2 FOUT FOUT FOUT frequency fosc3 / 8 fosc3 / 4 fosc3 / 2 fosc3 / fosc / 8 fosc / 4 fosc / 2 fosc / fosc: OSC oscillation frequency fosc3: OSC3 oscillation frequency When the selected clock source is not activated, the oscillation circuit must be turned ON before starting the FOUT output. An oscillation stabilization waiting time is required after the OSC3 or OSC oscillation circuit is turned ON. Consequently, if an abnormality occurs as the result of an unstable FOUT signal being output externally, you should allow an adequate waiting time after turning ON of the oscillation, before outputting FOUT. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. efer to the oscillation start time example indicated in Chapter 9, "Electrical Characteristics".) Since the FOUT signal is generated asynchronously from the register FOUTON, when the signal is turned ON or OFF by the register settings, a hazard of a /2 cycle or less is generated. Figure 8.6. shows the output waveform of the FOUT signal. FOUTON FOUT output (P22) Fig Output waveform of FOUT signal See Chapter, "I/O Ports (P Ports)", for the P22 port registers. 58 EPSON SC88655 TECHNICAL MANUAL

67 8.7 Details of Control egisters WT D4 WT WT2 WT WT D3 CLKCHG CPU operating clock switch D D SOSC3 SOSC OSC3 oscillation On/Off control OSC oscillation On/Off control OSC3 On On On 8 OSCILLATION CICUITS Table 8.7. shows the control bits for the oscillation circuits. Table 8.7. Oscillation circuit control bits Address Bit Name Function S Comment FF2 D7 EB Bus release enable register P24 BEQ (P24 and P25 terminal specification) P25 BACK WT2 Wait control register Number of state FF4 D7 FOUTON FOUT output control FOUT2 FOUT frequency selection FOUT D4 FOUT FOUT2 FOUT D3 D D WDST Watchdog timer reset FOUT No wait Frequency fosc3 / 8 fosc3 / 4 fosc3 / 2 fosc3 / fosc / 8 fosc / 4 fosc / 2 fosc / OSC Off Off Off "" when being read 2 3 Constantly "" when being read CLKCHG cannot be set to "" when SOSC = "" (OSC oscillation is OFF) and cannot be set to "" when SOSC3 = "" (OSC3 oscillation is OFF). 2 Cannot be turned OFF when the CPU is running with the OSC3 clock. 3 Cannot be turned OFF when the CPU is running with the OSC clock or the watchdog timer is enabled. eset No operation W SOSC: FF2H D Turns the OSC oscillation circuit ON or OFF. When "" is written: OSC oscillation ON When "" is written: OSC oscillation OFF eading: Valid If the system does not need the OSC clock when it is running with OSC3 clock, set SOSC to "" to reduce current consumption. When the system is running with the OSC clock or the watchdog timer that uses the OSC clock is enabled, the OSC oscillation circuit cannot be stopped. Also the OSC oscillation circuit stops when the SLP instruction is executed. At initial reset, SOSC is set to "" (OSC oscillation ON). SOSC3: FF2H D Turns the OSC3 oscillation circuit ON or OFF. When "" is written: OSC3 oscillation ON When "" is written: OSC3 oscillation OFF eading: Valid When the CPU and some peripheral circuits are to be operated at high speed, set SOSC3 to "". Otherwise, it should be set to "" in order to reduce current consumption. When the system is running with the OSC3 clock, the OSC3 oscillation circuit cannot be stopped. Also the OSC3 oscillation circuit stops when the SLP instruction is executed. At initial reset, SOSC3 is set to "" (OSC3 oscillation ON). SC88655 TECHNICAL MANUAL EPSON 59

68 8 OSCILLATION CICUITS CLKCHG: FF2H Selects the operating clock for the CPU. When "" is written: OSC3 clock When "" is written: OSC clock eading: Valid The CPU runs with the OSC3 clock when CLKCHG is set to "" or with the OSC clock when it is set to "". However, CLKCHG cannot be set to "" when SOSC = "" (OSC oscillation is OFF) and cannot be set to "" when SOSC3 = "" (OSC3 oscillation is OFF). At initial reset, CLKCHG is set to "" (OSC3 clock). FOUTON: FF4H D7 Controls the FOUT (fosc/fosc3 dividing clock) signal output. When "" is written: FOUT signal output When "" is written: P22 port eading: Valid FOUTON is the output control register for FOUT signal. When "" is set, the FOUT signal is output from the P22 port terminal and when "" is set, the port is set to the status according to the P22 port registers. While the FOUT signal is output (FOUTON is ""), settings of the I/O control register IOC22 and data register P22D become invalid. At initial reset, FOUTON is set to "" (P22 port). FOUTFOUT2: FF4H D4 FOUT signal frequency is set as shown in Table Table FOUT frequency settings FOUT2 FOUT FOUT FOUT frequency fosc3 / 8 fosc3 / 4 fosc3 / 2 fosc3 / fosc / 8 fosc / 4 fosc / 2 fosc / fosc: OSC oscillation frequency fosc3: OSC3 oscillation frequency At initial reset, this register is set to "" (fosc/). 8.8 Precautions () When the high speed CPU operation is not necessary, you should operate the peripheral circuits according to the setting outline indicate below. CPU operating clock OSC OSC3 oscillation circuit OFF (When the OSC3 clock is not necessary for some peripheral circuits.) (2) An oscillation stabilization time is required when the oscillation circuit starts oscillating. Therefore, be sure to wait long enough before switching the CPU clock or outputting the FOUT clock after the oscillation circuit is turned ON. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. efer to the oscillation start time example indicated in Chapter 9, "Electrical Characteristics".) (3) When switching the clock from OSC3 to OSC, be sure to turn OSC3 oscillation OFF with separate instructions. The same applies when switching the clock from OSC to OSC3 and turning OSC OFF. Using a single instruction to process simultaneously may cause a malfunction of the CPU. (4) Since the FOUT output signal is generated asynchronously from the output control register (FOUTON), when the signals is turned ON or OFF by the output control register settings, a hazard of a /2 cycle or less is generated. (5) If the SLP instruction is executed when the FOUT signal is being output, an unstable clock will be output when the system wakes up from SLEEP status. Therefore, stop the FOUT output before executing the SLP instruction. 6 EPSON SC88655 TECHNICAL MANUAL

69 9 OUTPUT POTS 9 OUTPUT POTS ( POTS) 9. Configuration of Output Ports The SC88655 is equipped with 26 bits of output ports (7, 7, 225, 333). Depending on the bus mode setting, the configuration of the output ports may vary as shown in the table below. Table 9.. Configuration of output ports Terminal Single chip Output port Output port Output port 2 Output port 3 Output port 4 Output port 5 Output port 6 Output port 7 Output port Output port Output port 2 Output port 3 Output port 4 Output port 5 Output port 6 Output port 7 Output port 2 Output port 2 Output port 22 Output port 23 Output port 24 Output port 25 Output port 3 Output port 3 Output port 32 Output port 33 Bus mode Expansion Address A Address A Address A2 Address A3 Address A4 Address A5 Address A6 Address A7 Address A8 Address A9 Address A Address A Address A2 Address A3 Address A4 Address A5 Address A6 Address A7 Address A8 Address A9 D signal W signal Output port 3/CE signal Output port 3/CE signal Output port 32/CE2 signal Output port 33/CE3 signal Only the configuration of the output ports in single chip mode will be discussed here. With respect to bus control, see Chapter 6, "System Controller and Bus Control". Figure 9.. shows the basic structure of the output ports. Data bus Address High impedance control register Data register Address Fig. 9.. Structure of output ports VDD VSS xx In expansion mode, the data registers and high impedance control registers of the output ports used for bus function can be used as generalpurpose registers with read/write capabilities. This will not in any way affect bus signal output. The output specification of each output port is as complementary output with high impedance control in software possible. 9.2 High Impedance Control The output port can be set into high impedance with software. This makes it possible to share output signal lines with an other external device. A high impedance control register HZxx is provided to control each port status. When a high impedance control register HZxx is set to "", the corresponding output port terminal becomes high impedance state and when set to "", it becomes complementary output. 9.3 DC Output As Figure 9.. shows, when "" is written to the output port data register, the output terminal goes HIGH (VDD) and when "" is written it goes LOW (VSS). When the port is in high impedance state, the data written to the data register is output from the terminal at the instant when output is switched to complementary. SC88655 TECHNICAL MANUAL EPSON 6

70 9 OUTPUT POTS 9.4 Details of Control egisters Table 9.4. shows the output port control bits. Table 9.4.(a) Output port control bits Address Bit Name Function S Comment FF7 D7 HZ7 HZ6 HZ5 7 high impedance control 6 high impedance control 5 high impedance control D4 HZ4 4 high impedance control High Complementary D3 HZ3 3 high impedance control impedance D D HZ2 HZ HZ 2 high impedance control high impedance control high impedance control FF7 D7 HZ7 HZ6 HZ5 7 high impedance control 6 high impedance control 5 high impedance control D4 HZ4 4 high impedance control High Complementary D3 HZ3 3 high impedance control impedance D D HZ2 HZ HZ 2 high impedance control high impedance control high impedance control FF72 D7 D4 HZ25 HZ24 25 high impedance control 24 high impedance control Constantly "" when being read D3 HZ23 23 high impedance control High Complementary HZ22 22 high impedance control impedance D D HZ2 HZ2 2 high impedance control 2 high impedance control FF73 D7 D4 D3 HZ33 33 high impedance control Constantly "" when being read HZ32 32 high impedance control High Complementary D HZ3 3 high impedance control impedance D HZ3 3 high impedance control FF74 D7 7D 6D 5D 7 output port data 6 output port data 5 output port data D4 4D 4 output port data D3 3D 3 output port data High Low D D 2D D D 2 output port data output port data output port data FF75 D7 7D 6D 5D 7 output port data 6 output port data 5 output port data D4 4D 4 output port data D3 3D 3 output port data High Low D D 2D D D 2 output port data output port data output port data 62 EPSON SC88655 TECHNICAL MANUAL

71 9 OUTPUT POTS Table 9.4.(b) Output port control bits Address Bit Name Function S Comment FF76 D7 register eserved register register 25D 25 output port data D4 24D 24 output port data D3 23D 23 output port data 22D 22 output port data High Low D 2D 2 output port data D 2D 2 output port data FF77 D7 register eserved register register register D4 register D3 33D 33 output port data 32D 32 output port data D 3D 3 output port data High Low D 3D 3 output port data HZHZ7: FF7H HZHZ7: FF7H HZ2HZ25: FF72H D HZ3HZ33: FF73H DD3 Sets the output terminals to a high impedance state. When "" is written: High impedance When "" is written: Complementary eading: Valid HZxx is the high impedance control register that corresponds to each output port terminal. When "" is set to the HZxx register, the corresponding output port terminal becomes high impedance state and when "" is set, it becomes complementary output. At initial reset, this register is set to "" (complementary). The high impedance control registers set for bus signal output can be used as general-purpose registers with read/write capabilities which do not affect the output terminals. D7D: FF74H D7D: FF75H 25D: FF76H D 3D33D: FF77H DD3 Sets the data output from the output port terminal xx. When "" is written: HIGH level output When "" is written: LOW level output eading: Valid xxd is the data register for each output port. When "" is set, the corresponding output port terminal goes HIGH (VDD), and when "" is set, it goes LOW (VSS). At initial reset, this register is set to "" (HIGH level output). The output data registers set for bus signal output can be used as general-purpose registers with read/write capabilities which do not affect the output terminals. SC88655 TECHNICAL MANUAL EPSON 63

72 I/O POTS I/O POTS (P POTS). Configuration of I/O Ports The SC88655 is equipped with 24 bits of I/O ports (PP7, PP7, P2P27). Figure.. shows the structure of an I/O port. Data bus Pull-up control register I/O control register Data register * Input *2 control VSS *3 *: During output mode *2: During input mode *3: Schmitt input can be selected for PP7 and P2P27 by mask option. Fig... Structure of I/O port VDD Mask option An I/O control register is provided for each I/O port to set the port into input or output mode. The I/O port terminals are shared with other functions shown below and are software configurable. Table.. Terminal shared function Port P P P2 P3 P4 P5 P6 P7 P P P2 P3 P4 P5 P6 P7 P2 P2 P22 P23 P24 P25 P26 P27 Shared functions Data bus (D) I/O Data bus (D) I/O Data bus () I/O Data bus (D3) I/O Data bus (D4) I/O Data bus () I/O Data bus () I/O Data bus (D7) I/O Serial I/F data input (SIN) I Serial I/F data output (SOUT) O Serial I/F clock input/output (SCLK) I or O Serial I/F ready signal output (SDY) O Serial I/F data input (SIN) I Serial I/F data output (SOUT) O Serial I/F clock input/output (SCLK) I or O Serial I/F ready signal output (SDY) O PTM / output (TOUT/TOUT) O PTM 2/3 output (TOUT2/TOUT3) O Clock output (FOUT) O PTM 2/3 inverted output (TOUT2/TOUT3) O ) Bus release request signal input (BEQ) I 2) PTM external clock input (EXCL) I ) Bus release ACK signal output (BACK) O 2) PTM external clock input (EXCL) I ) LCD clock output (CL) O 2) PTM 2 external clock input (EXCL2) I ) LCD frame signal output (F) O 2) PTM 3 external clock input (EXCL3) I Pxx PP7: DD7 The PP7 terminals are shared with the data bus DD7. When the bus mode is set to expansion mode, they function as the data bus terminals and cannot be used for generalpurpose inputs/outputs. In single chip mode, they can be used as the PP7 I/O ports. See Chapter 6, "System Controller and Bus Control", for the bus mode and the data bus. When these terminals are used as the data bus, the data registers and I/O control registers of the I/O ports can be used as general-purpose registers that do not affect the terminal status. The pull-up control registers are effective for the data bus. PP3: SIN, SOUT, SCLK, SDY P4P7: SIN, SOUT, SCLK, SDY The PP3 and P4P7 terminals are shared with the inputs/outputs of the serial interface. Some terminals may be used as the I/O ports depending on the transfer mode to be set even if the serial interface is used. See Chapter, "Serial Interface", for details. The data registers and I/O control registers of the ports used for serial input/output can be used as general-purpose registers that do not affect the terminal status. The pull-up control registers are effective for the input terminals. P2: TOUT/TOUT P2: TOUT2/TOUT3 P23: TOUT2/TOUT3 The P2, P2, and P23 terminals are shared with the programmable timer (PWM) outputs. See Section 3.6, "Setting TOUT Outputs", for details. When using the terminal for a timer output, set the port to output mode and set the output level when the timer output is disabled to the data register. The data register, I/O control register, and pullup control register of the port while the timer output is enabled do not affect the terminal status. P22: FOUT The P22 terminal is shared with the clock output. See Section 8.6, "Clock Output (FOUT)", for the clock output function. When using the terminal for the clock output, set the P22 port to output mode and set the output level when the clock output is disabled to the data register. The data register, I/O control register, and pullup control register of the port while the clock output is enabled do not affect the terminal status. 64 EPSON SC88655 TECHNICAL MANUAL

73 I/O POTS P24, P25: BEQ, BACK The P24 and P25 terminals are shared with the BEQ signal input and BACK signal output, respectively. See Section 6.5, "Setting Bus Authority elease equest Signal", for the BEQ and BACK signals. The data registers and I/O control registers of the ports can be used as general-purpose registers that do not affect the terminal status. The P24 pull-up control register is effective when used for the BEQ signal input. P26, P27: CL, F The P26 and P27 terminals are shared with the CL and F signal outputs, respectively. See Chapter 5, "LCD Driver", for the CL and F signals. When using the terminals for CL/F outputs, set the ports to output mode and set the output level when the CL/F outputs are disabled to the data registers. The data register, I/O control register, and pullup control register of the ports while the CL/F outputs are enabled do not affect the terminal status. P24P27: EXCLEXCL3 The P24P27 terminals can also be used for external clock inputs for the programmable timers. See Chapter 3, "Programmable Timer", for the EXCL input. When using the terminal for EXCL input, set the port to input mode. In this case, the terminal (P24P27) functions as an I/O port. Therefore, the pull-up control register is effective. This chapter explains the functions when the terminals are used as general-purpose I/O ports..2 Mask Option I/O port pull-up resistors P... With resistor Gate direct P... With resistor Gate direct P2... With resistor Gate direct P3... With resistor Gate direct P4... With resistor Gate direct P5... With resistor Gate direct P6... With resistor Gate direct P7... With resistor Gate direct P... With resistor Gate direct P... With resistor Gate direct P2... With resistor Gate direct P3... With resistor Gate direct P4... With resistor Gate direct P5... With resistor Gate direct P6... With resistor Gate direct P7... With resistor Gate direct P2... With resistor Gate direct P2... With resistor Gate direct P22... With resistor Gate direct P23... With resistor Gate direct P24... With resistor Gate direct P25... With resistor Gate direct P26... With resistor Gate direct P27... With resistor Gate direct I/O port input interface level P... CMOS level CMOS Schmitt P... CMOS level CMOS Schmitt P2... CMOS level CMOS Schmitt P3... CMOS level CMOS Schmitt P4... CMOS level CMOS Schmitt P5... CMOS level CMOS Schmitt P6... CMOS level CMOS Schmitt P7... CMOS level CMOS Schmitt P2... CMOS level CMOS Schmitt P2... CMOS level CMOS Schmitt P22... CMOS level CMOS Schmitt P23... CMOS level CMOS Schmitt P24... CMOS level CMOS Schmitt P25... CMOS level CMOS Schmitt P26... CMOS level CMOS Schmitt P27... CMOS level CMOS Schmitt I/O ports PP7, PP7, and P2P27 are equipped with a pull-up resistor which goes ON in the input mode. Whether this resistor is used or not can be selected for each port (one bit unit). Furthermore, the interface level for each port in PP7 and P2P27 can be selected from CMOS level and CMOS Schmitt level. SC88655 TECHNICAL MANUAL EPSON 65

74 I/O POTS.3 Input/Output Mode The I/O port Pxx is set either to input or output modes by writing data to the I/O control register IOCxx which corresponds to each bit. To set an I/O port to input mode, write "" to the I/O control register. The I/O port, which is set to input mode, will go to a high impedance state and functions as an input port. eadout in input mode consists simply of a direct readout of the input terminal state: the data being "" when the input terminal is at HIGH (VDD) level and "" when it is at LOW (VSS) level. When the built-in pull-up resistor is enabled with the software, the port terminal will be pulled-up to high during input mode. Even in input mode, data can be written to the data registers without affecting the terminal state. To set an I/O port to output mode, write "" to the I/O control register. The I/O port, which is set to output mode, functions as an output port. When port output data is "", a HIGH (VDD) level is output and when it is "", a LOW (VSS) level is output. eadout in output mode consists of the contents of the data register. At initial reset, I/O control registers are set to "" (I/O ports are set to input mode)..4 Pull-up Control When "With resistor" is selected by mask option, the software can enable and disable the pull-up resistor for each port (-bit units). The pull-up resistor becomes effective by writing "" to the pull-up control register PULPxx that corresponds to each port, and the Pxx terminal is pulled up during the input mode. When "" has been written, no pull-up is done. When "Gate direct" is selected by mask option, the corresponding pull-up control register is disconnected from the input line, so it can be used as a general-purpose register. When the port is set in the output mode, the setting of the pull-up control register becomes invalid (no pull-up is done during output). At initial reset, the pull-up control registers are set to "" (pulled up). When changing the port terminal from LOW level to HIGH with the built-in pull-up resistor, a delay in the waveform rise time will occur depending on the time constant of the pull-up resistor and the load capacitance of the terminal. It is necessary to set an appropriate wait time for introduction of an I/O port. Make this wait time the amount of time or more calculated by the following expression. Wait time = IN x (CIN + load capacitance on the board) x.6 [sec] IN: Pull up resistance Max. value CIN: Terminal capacitance Max. value For unused ports, select "With resistor" and enable pull-up using the pull-up control registers. 66 EPSON SC88655 TECHNICAL MANUAL

75 I/O POTS.5 Interrupt Function The P2P27 ports provide the input interrupt function. The condition for issuing an interrupt can be set for each terminal in software. When the interrupt generation condition set for a terminal is met, the interrupt factor flag FP2FP27 corresponding to the terminal is set at "" and an interrupt is generated. Interrupt can be prohibited by setting the interrupt enable registers EP2EP27 for the corresponding interrupt factor flags. Furthermore, the priority level for input interrupt can be set at the desired level (3) using the interrupt priority registers PP2PP2. For details on the interrupt control registers for the above and on operations subsequent to interrupt generation, see Chapter 7, "Interrupt and Standby Status". The exception processing vectors for each interrupt factor are set as follows: P27 input interrupt: 6H P26 input interrupt: 8H P25 input interrupt: AH P24 input interrupt: CH P23 input interrupt: EH P22 input interrupt: H P2 input interrupt: 2H P2 input interrupt: 4H Figure.5. shows the configuration of the input interrupt circuit. Note: When a port is placed in output mode or configured for the shared port function other than general-purpose DC input, disable interrupts from the port. P2 Check time setup register CTP2LCTP22L Address Input port P2D Input comparison register PCP2 Chattering-eliminate circuit Interrupt factor flag FP2 Divider Divider fosc fosc3 OSC oscillation circuit OSC3 oscillation circuit Address Address Interrupt enable register EP2 Address Data bus P2 P22 P23 P24 Check time setup register CTP2HCTP22H Address Interrupt priority level judgment circuit Interrupt request Input port P24D Chattering-eliminate circuit Input comparison register PCP24 Address P25 P26 P27 Interrupt factor flag FP24 Address Interrupt enable register EP24 Address Interrupt priority register PP2, PP2 Address Fig..5. Configuration of input interrupt circuit SC88655 TECHNICAL MANUAL EPSON 67

76 I/O POTS The input comparison register PCP selects whether the interrupt for each input port will be generated on the rising edge or the falling edge of input. When the P2x input signal changes to the status set by the input comparison register PCP2x, the interrupt factor flag FP2x is set to "" and an interrupt occurs. The input port has a chattering-eliminate circuit that checks input level to avoid unnecessary interrupt generation due to chattering. There are two separate chattering-eliminate circuits for P2 P23 and P24P27 and they can be set up individually. The CTP2xCTP22x registers allow selection of signal level check time as shown in Table.5.. Table.5. Setting the input level check time CTP22x CTP2x CTP2x Check time ( ) 4/fOSC3 (2 µs) 2/fOSC3 ( µs) /fosc3 (.5 µs) 496/fOSC (28 ms) 248/fOSC (64 ms) 52/fOSC (6 ms) 28/fOSC (4 ms) None : When OSC = 32 khz, OSC3 = 2 MHz Notes: Input interrupts cannot be accepted in SLEEP mode if the CPU enters SLEEP mode when the chattering-eliminate circuit is active. The chattering-eliminate circuit should be turned OFF (CTP2x = "") before executing the SLP instruction. Be sure to disable interrupts before changing the contents of the CTP2x register. Unnecessary interrupts may occur if the register is changed when the corresponding input port interrupts have been enabled by the interrupt enable register EP2x. The chattering-eliminate check time means the maximum pulse width that can be eliminated. The valid interrupt input needs a pulse width of the set check time (minimum) to twice that of the check time (maximum). The internal signal may oscillate if the rise / fall time of the input signal is too long because the input signal level transition to the threshold level duration of time is too long. This causes the input interrupt to malfunction, therefore setup the input signal so that the rise/fall time is 25 nsec or less. 68 EPSON SC88655 TECHNICAL MANUAL

77 I/O POTS.6 Details of Control egisters Table.6. shows the I/O port control bits. Table.6.(a) I/O port control bits Address Bit Name Function S Comment FF5 D7 IOC7 IOC6 IOC5 P7 I/O control register P6 I/O control register P5 I/O control register D4 IOC4 P4 I/O control register D3 IOC3 P3 I/O control register Output Input D D IOC2 IOC IOC P2 I/O control register P I/O control register P I/O control register FF5 D7 IOC7 IOC6 IOC5 P7 I/O control register P6 I/O control register P5 I/O control register D4 IOC4 P4 I/O control register D3 IOC3 P3 I/O control register Output Input D D IOC2 IOC IOC P2 I/O control register P I/O control register P I/O control register FF52 D7 P7D P6D P5D P7 I/O port data P6 I/O port data P5 I/O port data D4 P4D P4 I/O port data D3 P3D P3 I/O port data High Low D D P2D PD PD P2 I/O port data P I/O port data P I/O port data FF53 D7 P7D P6D P5D P7 I/O port data P6 I/O port data P5 I/O port data D4 P4D P4 I/O port data D3 P3D P3 I/O port data High Low D D P2D PD PD P2 I/O port data P I/O port data P I/O port data FF54 D7 PULP7 PULP6 PULP5 P7 pull-up control register P6 pull-up control register P5 pull-up control register D4 PULP4 P4 pull-up control register D3 PULP3 P3 pull-up control register On Off D D PULP2 PULP PULP P2 pull-up control register P pull-up control register P pull-up control register FF55 D7 PULP7 PULP6 PULP5 P7 pull-up control register P6 pull-up control register P5 pull-up control register D4 PULP4 P4 pull-up control register D3 PULP3 P3 pull-up control register On Off D D PULP2 PULP PULP P2 pull-up control register P pull-up control register P pull-up control register SC88655 TECHNICAL MANUAL EPSON 69

78 I/O POTS Table.6.(b) I/O port control bits Address Bit Name Function S Comment FF6 D7 IOC27 IOC26 IOC25 D4 IOC24 D3 IOC23 IOC22 D IOC2 D IOC2 FF62 D7 P27D P26D P25D D4 P24D D3 P23D P22D D P2D D P2D P27 I/O control register P26 I/O control register P25 I/O control register P24 I/O control register P23 I/O control register P22 I/O control register P2 I/O control register P2 I/O control register P27 I/O port data P26 I/O port data P25 I/O port data P24 I/O port data P23 I/O port data P22 I/O port data P2 I/O port data P2 I/O port data FF64 D7 D4 D3 D D PULP27 PULP26 PULP25 PULP24 PULP23 PULP22 PULP2 PULP2 P27 pull-up control register P26 pull-up control register P25 pull-up control register P24 pull-up control register P23 pull-up control register P22 pull-up control register P2 pull-up control register P2 pull-up control register FF66 D7 PCP27 P27 input comparison register PCP26 P26 input comparison register PCP25 P25 input comparison register D4 PCP24 P24 input comparison register D3 PCP23 P23 input comparison register PCP22 P22 input comparison register D PCP2 P2 input comparison register D PCP2 P2 input comparison register FF68 D7 CTP22H P24P27 port chattering-eliminate setup (Input level check time) Check time CTP22H CTP2H CTP2H [sec] CTP2H 4/fOSC3 2/fOSC3 /fosc3 496/fOSC D4 CTP2H 248/fOSC 52/fOSC 28/fOSC None D3 CTP22L P2P23 port chattering-eliminate setup (Input level check time) Check time CTP22L CTP2L CTP2L [sec] D CTP2L 4/fOSC3 2/fOSC3 /fosc3 496/fOSC D CTP2L 248/fOSC 52/fOSC 28/fOSC None Output High On Interrupt occurred at falling edge Input Low Off Interrupt occurred at rising edge "" when being read "" when being read 7 EPSON SC88655 TECHNICAL MANUAL

79 I/O POTS PDP7D: FF52H PDP7D: FF53H P2DP27D: FF62H These registers are used to read Pxx I/O port terminal data and to set output data. When writing data: When "" is written: HIGH level When "" is written: LOW level When the I/O port is set to output mode, the data written is output as is to the I/O port terminal. In terms of port data, when "" is written, the port terminal goes to HIGH (VDD) level and when "" is written to a LOW (VSS) level. Even when the port is in input mode, data can still be written in. When reading out data: When "" is read: HIGH level ("") When "" is read: LOW level ("") When an I/O port is in input mode, the voltage level being input to the port terminal is read out. When terminal voltage is HIGH (VDD), it is read as a "", and when it is LOW (VSS), it is read as a "". Furthermore, in output mode, the contents of the data register are read out. At initial reset, this register is set to "" (HIGH level). Note: The data registers of the ports that are configured to the data bus and serial interface outputs can be used as generalpurpose registers that do not affect the terminal input/output status. IOCIOC7: FF5H IOCIOC7: FF5H IOC2IOC27: FF6H Sets the I/O ports to input or output mode. When "" is written: Output mode When "" is written: Input mode eading: Valid IOCxx is the I/O control register which corresponds to each I/O port (in bit units). Writing "" to the IOCxx register will set the corresponding I/O port Pxx to output mode, and writing "" will set it to input mode. When the special output is used, "" must always be set for the I/O control registers of I/O ports which will become output terminals. At initial reset, this register is set to "" (input mode). Note: The I/O control registers of the ports that are configured to the data bus and serial interface inputs/outputs can be used as general-purpose registers that do not affect the terminal input/output status. PULPPULP7: FF54H PULPPULP7: FF55H PULP2PULP27: FF64H Enables pull-up during input mode. When "" is written: Pull-up ON When "" is written: Pull-up OFF eading: Valid PULPxx is the pull-up control register corresponding to each I/O port (in bit units). When "Gate direct" is selected by mask option, the corresponding pull-up control register is disconnected from the input line, so it can be used as a general-purpose register. By writing "" to the PULPxx register, the corresponding I/O ports are pulled up (during input mode), while writing "" turns the pull-up function OFF. At initial reset, these registers are all set to "", so the pull-up function is enabled. Note: The pull-up control registers of the ports that are configured to the serial interface outputs can be used as general-purpose registers that do not affect the pull-up control. The pull-up control registers of the port that are configured to the data bus and serial interface inputs function the same as the I/O port. PCP2PCP27: FF66H Sets the interrupt generation condition (interrupt generation timing) for input port terminals P2 P27. When "" is written: Falling edge When "" is written: ising edge eading: Valid PCP2x is the input comparison register which corresponds to the input port P2x. When PCP2x is set to "", interrupts from the P2x port are generated at the falling edge of the input signal. When PCP2x is set to "", interrupts are generated at the rising edge. At initial reset, this register is set to "" (falling edge). SC88655 TECHNICAL MANUAL EPSON 7

80 I/O POTS CTP2LCTP22L: FF68H D Sets the input level check time of the chatteringeliminate circuit for the P2P23 port interrupts as shown in Table.6.2. Table.6.2 Setting the input level check time CTP22L CTP2L CTP2L Input level check time [sec] 4/fOSC3 2/fOSC3 /fosc3 496/fOSC 248/fOSC 52/fOSC 28/fOSC None Be sure to disable interrupts before changing the contents of this register. Unnecessary interrupts may occur if the register is changed when the corresponding input port interrupts have been enabled by the interrupt enable register EP2x. At initial reset, this register is set to "" (None). CTP2HCTP22H: FF58H D4 Sets the input level check time of the chatteringeliminate circuit for the P24P27 input port interrupts as shown in Table.6.3. Table.6.3 Setting the input level check time CTP22H CTP2H CTP2H Input level check time [sec] 4/fOSC3 2/fOSC3 /fosc3 496/fOSC 248/fOSC 52/fOSC 28/fOSC None.7 Precautions () When changing the port terminal in which the pull-up resistor is enabled from LOW level to HIGH, a delay in the waveform rise time will occur depending on the time constant of the pull-up resistor and the load capacitance of the terminal. It is necessary to set an appropriate wait time for introduction of an I/O port. Make this wait time the amount of time or more calculated by the following expression. Wait time = IN x (CIN + load capacitance on the board) x.6 [sec] IN: Pull up resistance Max. value CIN: Terminal capacitance Max. value (2) Be sure to disable interrupts before changing the contents of the CTP2x register. Unnecessary interrupts may occur if the register is changed when the corresponding input port interrupts have been enabled by the interrupt enable register EP2x. Be sure to disable interrupts before changing the contents of this register. Unnecessary interrupt may occur if the register is changed when the corresponding input port interrupts have been enabled by the interrupt enable register EP2x. At initial reset, this register is set to "" (None). 72 EPSON SC88655 TECHNICAL MANUAL

81 SEIAL INTEFACE SEIAL INTEFACE. Configuration of Serial Interface The SC88655 incorporates a full duplex serial interface (when asynchronous system is selected) that allows the user to select either clock synchronous system or asynchronous system. The data transfer method can be selected in software. When the clock synchronous system is selected, 8-bit data transfer is possible. When the asynchronous system is selected, either 7-bit or 8- bit data transfer is possible, and a parity check of received data and the addition of a parity bit for transmitting data can automatically be done by selecting in software. Figure.. shows the configuration of the serial interface. Note: Ch. and Ch. have the same circuit configuration and functions. The signal and control bit names are suffixed by a or to indicate the channel number, enabling discrimination between channels and. In this manual, however, channel numbers and are replaced with "x" unless discrimination is necessary, because explanations are common to both channels..2 Switching Terminal Functions The serial interface Ch. input/output terminals, SIN, SOUT, SCLK, and SDY are shared with the I/O ports PP3. Also Ch. input/output terminals, SIN, SOUT, SCLK, and SDY are shared with the I/O ports P4P7. In order to utilize these terminals for the serial interface input/ output terminals, "" must be written to the ESIFx register. At initial reset, these terminals are set as I/ O port terminals. The direction of I/O port terminals set for serial interface input/output terminals are determined by the signal and transfer mode for each terminal. Furthermore, the settings for the corresponding I/ O control registers for the I/O ports become invalid. Table.2. Configuration of input/output terminals Terminal When serial interface is selected P SIN P SOUT P2 SCLK P3 SDY P4 SIN P5 SOUT P6 SCLK P7 SDY * The terminals used may vary depending on the transfer mode. The serial interface terminals are configured according to the transfer mode set using the registers SMDx and SMDx. SINx and SOUTx are serial data input and output terminals which function identically in clock synchronous system and asynchronous system. SCLKx is exclusively for use with clock synchronous system and functions as a synchronous clock input/output terminal. SDYx is exclusively for use in clock synchronous slave mode and functions as a send-receive ready signal output terminal. When asynchronous system is selected, since SCLKx and SDYx are superfluous, the I/O port terminals P2 (P6) and P3 (P7) can be used as I/O ports. In the same way, when clock synchronous master mode is selected, since SDYx is superfluous, the I/O port terminal P3 (P7) can be used as an I/O port. Data bus Serial I/O control & status register eceive data buffer Error detection circuit Transmit data buffer Interrupt control circuit Interrupt request SIN(P) or SIN(P4) Serial input control circuit eceive data shift register Transmit data shift register Serial output control circuit SOUT(P) or SOUT(P5) SCLK(P2) or SCLK(P6) Start bit detection circuit Clock control circuit EADY output control circuit Programmable timer underflow signal (Ch. ) Programmable timer 7 underflow signal (Ch. ) Fig... Configuration of serial interface SDY(P3) or SDY(P7) SC88655 TECHNICAL MANUAL EPSON 73

82 SEIAL INTEFACE.3 Transfer Modes There are four transfer modes for the serial interface and mode selection is made by setting the two bits of the mode selection registers SMDx and SMDx as shown in the table below. Table.3. Transfer modes SMDx SMDx Mode Asynchronous 8-bit Asynchronous 7-bit Clock synchronous slave Clock synchronous master Table.3.2 Terminal settings corresponding to each transfer mode Mode SINx SOUTx SCLKx SDYx Asynchronous 8-bit Asynchronous 7-bit Input Input Output P2/P6 P3/P7 Output P2/P6 P3/P7 Clock synchronous slave Clock synchronous master Input Input Output Output Input Output Output P3/P7 At initial reset, transfer mode is set to clock synchronous master mode. Clock synchronous master mode In this mode, the internal clock is utilized as a synchronous clock for the built-in shift registers, and clock synchronous 8-bit serial transfers can be performed with this serial interface as the master. The synchronous clock is also output from the SCLKx terminal which enables control of the external (slave side) serial I/O device. Since the SDYx terminal is not utilized in this mode, it can be used as an I/O port. Figure.3.(a) shows the connection example of input/output terminals in the clock synchronous master mode. Clock synchronous slave mode In this mode, a synchronous clock from the external (master side) serial input/output device is utilized and clock synchronous 8-bit serial transfers can be performed with this serial interface as the slave. The synchronous clock is input to the SCLKx terminal and is utilized by this interface as the synchronous clock. Furthermore, the SDYx signal indicating the transmit-receive ready status is output from the SDYx terminal in accordance with the serial interface operating status. In the slave mode, the settings for registers SCSx and SCSx used to select the clock source are invalid. Figure.3.(b) shows the connection example of input/output terminals in the clock synchronous slave mode. Asynchronous 7-bit mode In this mode, asynchronous 7-bit transfer can be performed. Parity check during data reception and addition of parity bit (odd/even/none) during transmitting can be specified and data processed in 7 bits with or without parity. Since this mode employs the internal clock, the SCLKx terminal is not used. Furthermore, since the SDYx terminal is not utilized either, both of these terminals can be used as I/O ports. Figure.3.(c) shows the connection example of input/output terminals in the asynchronous mode. Asynchronous 8-bit mode In this mode, asynchronous 8-bit transfer can be performed. Parity check during data reception and addition of parity bit (odd/even/none) during transmitting can be specified and data processed in 8 bits with or without parity. Since this mode employs the internal clock, the SCLKx terminal is not used. Furthermore, since the SDYx terminal is not utilized either, both of these terminals can be used as I/O ports. Figure.3.(c) shows the connection example of input/output terminals in the asynchronous mode. SC88655 SINx(P/P4) SOUTx(P/P5) SCLKx(P2/P6) Pxx port (input) External serial device Data input Data output CLOCK input (a) Clock synchronous master mode SC88655 SINx(P/P4) SOUTx(P/P5) SCLKx(P2/P6) SDYx(P3/P7) EADY output External serial device Data input Data output (b) Clock synchronous slave mode SC88655 SINx(P/P4) SOUTx(P/P5) CLOCK output EADY input Data input (c) Asynchronous 7-bit/8-bit mode External serial device Data output Fig..3. Connection examples of serial interface I/O terminals 74 EPSON SC88655 TECHNICAL MANUAL

83 SEIAL INTEFACE.4 Clock Source There are four clock sources and selection is made by setting the two bits of the clock source selection register SCSx and SCSx as shown in table below. Table.4. Clock source SCSx SCSx Clock source Programmable timer (Ch. ) Programmable timer 7 (Ch. ) fosc3 / 4 fosc3 / 8 fosc3 / 6 This register setting is invalid in clock synchronous slave mode and the external clock input from the SCLKx terminal is used. When the "programmable timer " is selected, the underflow signal of the programmable timer for Ch. or timer 7 for Ch. is divided by 2 and the divided signal is used as the clock source. With respect to the transfer rate setting, see Chapter 3, "Programmable Timer". At initial reset, the synchronous clock is set to "fosc3/6". Whichever clock is selected, the signal is further divided by 6 and then used as the synchronous clock. Furthermore, external clock input is used as is for SCLKx in clock synchronous slave mode. When the divided signal of the OSC3 oscillation circuit is made the clock source, it is necessary to turn the OSC3 oscillation ON, prior to using the serial interface. A time interval of several msec to several msec, from the turning ON of the OSC3 oscillation circuit to until the oscillation stabilizes, is necessary, due to the oscillation element that is used. Consequently, you should allow an adequate waiting time after turning ON of the OSC3 oscillation, before starting transmitting/receiving of serial interface. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. efer to the oscillation start time example indicated in Chapter 9, "Electrical Characteristics".) At initial reset, the OSC3 oscillation circuit is set to ON status. OSC3 oscillation circuit fosc3 /4 /8 Divider /6 Selector /6 Selector Synchronous clock Programmable timer underflow signal /2 (Ch. : timer, Ch. : timer 7) (Clock synchronous slave mode) SCLKx Fig..4. Division of the synchronous clock SC88655 TECHNICAL MANUAL EPSON 75

84 SEIAL INTEFACE.5 Transmit/eceive Control Below is a description of the registers which handle transmit/receive control. With respect to transmit/ receive control procedures and operations, please refer to the following sections in which these are discussed on a mode by mode basis. In addition, TXTGx can be read as the status. When set to "", it indicates transmitting operation, and "" indicates transmitting stop. For details on timing, see the timing chart which gives the timing for each mode. When not transmitting, set TXENx to "" to disable transmitting status. Shift register and transmit/received data buffer Exclusive shift registers for transmitting and receiving are installed in this serial interface. Consequently, duplex communication simultaneous transmit and receive is possible when the asynchronous system is selected. In the transmit section, a transmit data buffer is installed separate from the shift register. When data transmission is started, the data in the transmit data buffer is converted to serial through the shift register and output from the SOUTx terminal. Data can be written to the transmit data buffer asynchronously with the serial output, this allows highly efficient continuous data transfer. In the reception section, a received data buffer is installed separate from the shift register. Data being received are input to the SINx terminal and is converted to parallel through the shift register and written to the received data buffer. Since the received data buffer can be read even during serial input operation, the continuous data is received efficiently. However, since buffer functions are not used in clock synchronous mode, be sure to read out data before the next data reception begins. Transmit enable register and transmit control bit For transmitting control, use the transmit enable register TXENx and transmit control bit TXTGx. The transmit enable register TXENx is used to set the transmitting enable/disable status. When "" is written to this register to set the transmitting enable status, clock input to the shift register is enabled and the system is ready to transmit data. In the clock synchronous mode, synchronous clock input/output from the SCLKx terminal is also enabled. The transmit control bit TXTGx is used as the trigger to start transmitting data. Prepare data transmission by writing data to the transmit data buffer and write "" to TXTGx. Then the data in the transmit data buffer is loaded to the transmit data shift register and data transmission begins. When interrupt has been enabled, an interrupt is generated when the transmission is completed. If there is subsequent data to be transmitted it can be sent using this interrupt. eceive enable register and receive control bit For receiving control, use the receive enable register XENx and receive control bit XTGx. eceive enable register XENx is used to set receiving enable/disable status. When "" is written into this register to set the receiving enable status, clock input to the shift register is enabled and the system is ready to receive data. In the clock synchronous mode, synchronous clock input/output from the SCLKx terminal is also enabled. With the above setting, receiving begins and serial data input from the SINx terminal goes to the shift register. The operation of the receive control bit XTGx is slightly different depending on whether a clock synchronous system or an asynchronous system is being used. In the clock synchronous system, the receive control bit XTGx is used as the trigger to start receiving data. When received data has been read and the preparation for next data receiving is completed, write "" into XTGx to start receiving. (When "" is written to XTGx in slave mode, SDYx switches to "".) In an asynchronous system, XTGx is used to prepare for next data receiving. After reading the received data from the received data buffer, write "" into XTGx to signify that the received data buffer is empty. If "" is not written into XTGx, the overrun error flag OEx will be set to "" when the next receiving operation is completed. (An overrun error will be generated when receiving is completed between reading the received data and the writing of "" to XTGx.) In addition, XTGx can be read as the status. In either clock synchronous mode or asynchronous mode, when XTGx is set to "", it indicates receiving operation and when set to "", it indicates that receiving has stopped. For details on timing, see the timing chart which gives the timing for each mode. When you do not receive, set XENx to "" to disable receiving status. 76 EPSON SC88655 TECHNICAL MANUAL

85 SEIAL INTEFACE.6 Operation of Clock Synchronous Transfer Clock synchronous transfer involves the transfer of 8-bit data by synchronizing it to eight clocks. The same synchronous clock is used by both the transmitting and receiving sides. When the serial interface is used in the master mode, the clock signal selected using SCSx and SCSx is further divided by /6 and employed as the synchronous clock. This signal is then sent via the SCLKx terminal to the slave side (external serial I/O device). When used in the slave mode, the clock input to the SCLKx terminal from the master side (external serial input/output device) is used as the synchronous clock. In the clock synchronous mode, since one clock line (SCLKx) is shared for both transmitting and receiving, transmitting and receiving cannot be performed simultaneously. (Half duplex only is possible in clock synchronous mode.) The transfer data length is fixed at 8 bits. Data can be switched using a register whether it is transmitted/received from LSB (bit ) or MSB (bit 7). LSB first SCLKx Data MSB first SCLKx Data LSB MSB D D D3 D4 D7 MSB LSB D7 D4 D3 D D Fig..6. Transfer data configuration using clock synchronous mode Below is a description of initialization when performing clock synchronous transfer, transmitreceive control procedures and operations. With respect to serial interface interrupt, see ".8 Interrupt Function". Initialization of serial interface When performing clock synchronous transfer, the following initial settings must be made. () Setting of transmitting/receiving disable To set the serial interface into a status in which both transmitting and receiving are disabled, "" must be written to both the transmit enable register TXENx and the receive enable register XENx. Fix these two registers to a disable status until data transfer actually begins. (2) Port selection Because serial interface input/output ports SINx, SOUTx, SCLKx and SDYx are set as I/O port terminals PP3 (P4P7) at initial reset, "" must be written to the serial interface enable register ESIFx in order to set these terminals for serial interface use. (3) Setting of transfer mode Select the clock synchronous mode by writing the data as indicated below to the two bits of the mode selection registers SMDx and SMDx. Master mode: SMDx = "", SMDx = "" Slave mode: SMDx = "", SMDx = "" (4) Clock source selection In the master mode, select the synchronous clock source by writing data to the two bits of the clock source selection registers SCSx and SCSx. (See Table.4..) This selection is not necessary in the slave mode. Since all the registers mentioned in (2)(4) are assigned to the same address, it's possible to set them all with one instruction. The parity enable register EPx is also assigned to this address, however, since parity is not necessary in the clock synchronous mode, parity check will not take place regardless of how they are set. (5) Clock source control When the master mode is selected and programmable timer for the clock source is selected, set transfer rate on the programmable timer side. (See Chapter 3, "Programmable Timer".) When the divided signal of OSC3 oscillation circuit is selected for the clock source, be sure that the OSC3 oscillation circuit is turned ON prior to commencing data transfer. (See Chapter 8, "Oscillation Circuits".) (6) Serial data input/output permutation The SC88655 provides the data input/output permutation select register SDPx to select whether the serial data bits are transferred from the LSB or MSB. The SDPx register should be set before writing data to TXDxTXDx7. SC88655 TECHNICAL MANUAL EPSON 77

86 SEIAL INTEFACE Data transmit procedure Data transmitting TXENx, XENx TXENx Set transmitting data to TXDxTXDx7 No eceiver ready? In case of master mode Yes TXTGx The transmitting complete interrupt factor flag FSTAx is set to "" at the point where the data transmitting of the shift register is completed. When interrupt has been enabled, a transmitting complete interrupt is generated at this point. Set the following transmitting data using this interrupt. (6) epeat steps (3) to (5) for the number of bytes of transmitting data, and then set the transmit disable status by writing "" to the transmit enable register TXENx, when the transmitting is completed. Data receive procedure No FSTAx =? Yes Transmit complete? No Data receiving XENx, TXENx End Yes TXENx Fig..6.2 Transmit procedure in clock synchronous mode The control procedure and operation during transmitting is as follows. () Write "" in the transmit enable register TXENx and the receive enable register XENx to reset the serial interface. (2) Write "" in the transmit enable register TXENx to set into the transmitting enable status. (3) Write the transmitting data into TXDxTXDx7. (4) In case of the master mode, confirm the receive ready status on the slave side (external serial input/output device), if necessary. Wait until it reaches the receive ready status. (5) Write "" in the transmit control bit TXTGx and start transmitting. In the master mode, this control causes the synchronous clock to change to enable and to be provided to the shift register for transmitting and output from the SCLKx terminal. In the slave mode, it waits for the synchronous clock to be input from the SCLKx terminal. The transmitting data of the shift register shifts one bit at a time at each falling edge of the synchronous clock and is output from the SOUTx terminal. When the final bit (MSB when "LSB first" is selected, or LSB when "MSB first" is selected) is output, the SOUTx terminal is maintained at that level, until the next transmitting begins. No XENx No Transmitter ready? In case of master mode Yes XTGx FSECx =? Yes eceived data reading from XDxXDx7 eceiving complete? Yes XENx End Fig..6.3 eceiving procedure in clock synchronous mode The control procedure and operation during receiving is as follows. () Write "" in the receive enable register XENx and transmit enable register TXENx to reset the serial interface. (2) Write "" in the receive enable register XENx to set into the receiving enable status. (3) In case of the master mode, confirm the transmit ready status on the slave side (external serial input/output device), if necessary. Wait until it reaches the transmit ready status. No 78 EPSON SC88655 TECHNICAL MANUAL

87 SEIAL INTEFACE (4) Write "" in the receive control bit XTGx and start receiving. In the master mode, this control causes the synchronous clock to change to enable and is provided to the shift register for receiving and output from the SCLKx terminal. In the slave mode, it waits for the synchronous clock to be input from the SCLKx terminal. The received data input from the SINx terminal is successively incorporated into the shift register in synchronization with the rising edge of the synchronous clock. At the point where the data of the 8th bit has been incorporated at the final (8th) rising edge of the synchronous clock, the content of the shift register is sent to the received data buffer and the receiving complete interrupt factor flag FSECx is set to "". When interrupt has been enabled, a receiving complete interrupt is generated at this point. (5) ead the received data from XDxXDx7 using receiving complete interrupt. (6) epeat steps (3) to (5) for the number of bytes of receiving data, and then set the receive disable status by writing "" to the receive enable register XENx, when the receiving is completed. Transmit/receive ready (SDYx) signal When this serial interface is used in the clock synchronous slave mode (external clock input), an SDYx signal is output to indicate whether or not this serial interface can transmit/receive to the master side (external serial input/output device). This signal is output from the SDYx terminal and when this interface enters the transmit or receive enable (EADY) status, it becomes "" (LOW level) and becomes "" (HIGH level) when there is a BUSY status, such as during transmit/receive operation. The SDYx signal changes the "" to "," immediately after writing "" into the transmit control bit TXTGx or the receive control bit XTGx and returns from "" to "", at the point where the first synchronous clock has been input (falling edge). When you have set in the master mode, control the transfer by inputting the same signal from the slave side using the input port or I/O port. At this time, since the SDYx terminal is not set and instead P3 (P7) functions as the I/O port, you can apply this port for said control. Timing chart The timing chart for the clock synchronous system transmission is shown in Figure.6.4. TXENx TXTGx (D) TXTGx (W) SCLKx SOUTx Interrupt TXENx TXTGx (D) TXTGx (W) SCLKx SOUT SDYx Interrupt XENx XTGx (D) XTGx (W) SCLKx SINx Interrupt D D D3 D4 D7 (a) Transmit timing for master mode D D D3 D4 D7 (b) Transmit timing for slave mode D D D3 D4 D7 XDx 7F st data XENx XTGx (D) XTGx (W) SCLKx SINx Interrupt (c) eceive timing for master mode D D D3 D4 D7 XDx 7F st data SDYx (d) eceive timing for slave mode Fig..6.4 Timing chart (clock synchronous system transmission, LSB first) 7F SC88655 TECHNICAL MANUAL EPSON 79

88 SEIAL INTEFACE.7 Operation of Asynchronous Transfer Asynchronous transfer is a mode that transfers by adding a start bit and a stop bit to the front and the back of each piece of serial converted data. In this mode, there is no need to use a clock that is fully synchronized clock on the transmit side and the receive side, but rather transmission is done while adopting the synchronization at the start/stop bits that have attached before and after each piece of data. The S-232C interface functions can be easily realized by selecting this transfer mode. This interface has separate transmit and receive shift registers and is designed to permit full duplex transmission to be done simultaneously for transmitting and receiving. For transfer data in the asynchronous 7-bit mode, either 7 bits data (no parity) or 7 bits data + parity bit can be selected. In the asynchronous 8-bit mode, either 8 bits data (no parity) or 8 bits data + parity bit can be selected. Parity can be even or odd, and parity checking of received data and adding a party bit to transmitting data will be done automatically. Thereafter, it is not necessary to be conscious of parity itself in the program. The start bit length is fixed at bit. For the stop bit length, either bit or 2 bits can be selected using the stop bit select register STPBx. Whether data is transmitted/received from LSB (bit ) or MSB (bit 7) it can be switched using the data input/output permutation select register SDPx. LSB first Sampling clock 7bit data 7bit data +parity 8bit data 8bit data +parity MSB first Sampling clock 7bit data 7bit data +parity 8bit data 8bit data +parity s s s s s s D D D3 D4 D D D3 D4 D D D3 D4 D7 D4 D3 D D D4 D3 D D D7 D4 D3 D D p s2 s2 s D7 D4 D3 D D p s2 s : Start bit (Low level, bit) s2 : Stop bit (High level, bit or 2 bits) p : Parity bit p s2 s2 s2 s D D D3 D4 D7 p s2 Fig..7. Transfer data configuration for asynchronous system Here following, we will explain the control sequence and operation for initialization and transmitting /receiving in case of asynchronous data transfer. See ".8 Interrupt Function" for the serial interface interrupts. s2 Initialization of serial interface The below initialization must be done in cases of asynchronous system transfer. () Setting of transmitting/receiving disable To set the serial interface into a status in which both transmitting and receiving are disabled, "" must be written to both the transmit enable register TXENx and the receive enable register XENx. Fix these two registers to a disable status until data transfer actually begins. (2) Port selection Because serial interface input/output terminals SINx and SOUTx are set as I/O port terminals P (P4) and P (P5) at initial reset, "" must be written to the serial interface enable register ESIFx in order to set these terminals for serial interface use. SCLKx and SDYx terminals set in the clock synchronous mode are not used in the asynchronous mode. These terminals function as I/O port terminals P2 (P6) and P3 (P7). (3) Setting of transfer mode Select the asynchronous mode by writing the data as indicated below to the two bits of the mode selection registers SMDx and SMDx. 7-bit mode: SMDx = "", SMDx = "" 8-bit mode: SMDx = "", SMDx = "" (4) Parity bit selection When checking and adding parity bits, write "" into the parity enable register EPx to set to "with parity check". As a result of this setting, in the asynchronous 7-bit mode, it has a 7 bits data + parity bit configuration and in the asynchronous 8-bit mode it has an 8 bits data + parity bit configuration. In this case, parity checking for receiving and adding a party bit for transmitting is done automatically in hardware. Moreover, when "with parity check" has been selected, "odd" or "even" parity must be further selected in the parity mode selection register PMDx. When "" is written to the EPx register to select "without parity check" in the asynchronous 7-bit mode, data configuration is set to 7 bits data (no parity) and in the asynchronous 8-bit mode (no parity) it is set to 8 bits data (no parity) and parity checking and parity bit adding will not be done. (5) Clock source selection Select the clock source by writing data to the two bits of the clock source selection registers SCSx and SCSx. (See Table.4..) Since all the registers mentioned in (2)(5) are assigned to the same address, it's possible to set them all with one instruction. 8 EPSON SC88655 TECHNICAL MANUAL

89 SEIAL INTEFACE (6) Clock source control When the programmable timer is selected for the clock source, set transfer rate on the programmable timer side. (See Chapter 3, "Programmable Timer".) When the divided signal of OSC3 oscillation circuit is selected for the clock source, be sure that the OSC3 oscillation circuit is turned ON prior to commencing data transfer. (See Chapter 8, "Oscillation Circuits".) (7) Stop bit length selection The stop bit length can be configured to bit or 2 bits using the stop bit select register STPBx. Table.7. Stop bit and parity bit settings STPBx EPx PMDx Settings Stop bit Parity bit 2 bits 2 bits 2 bits bit bit bit Odd Even Non parity Odd Even Non parity (8) Serial data input/output permutation The SC88655 provides the data input/output permutation select register SDPx to select whether the serial data bits are transferred from the LSB or MSB. The SDPx register should be set before writing data to TXDxTXDx7. Data transmit procedure No Data transmitting TXENx TXENx Set transmitting data to TXDxTXDx7 TXTGx FSTAx =? Yes Transmit complete? Yes TXENx End Fig..7.2 Transmit procedure in asynchronous mode The control procedure and operation during transmitting is as follows. () Write "" in the transmit enable register TXENx to reset the serial interface. (2) Write "" in the transmit enable register TXENx to set into the transmitting enable status. (3) Write the transmitting data into TXDxTXDx7. Also, when 7-bit data is selected, the TXDx7 data becomes invalid. (4) Write "" in the transmit control bit TXTGx and start transmitting. This control causes the shift clock to change to enable and a start bit (LOW) is output to the SOUTx terminal in synchronize to its falling edge. The transmitting data set to the shift register is shifted one bit at a time at each falling edge of the clock thereafter and is output from the SOUTx terminal. After the data output, it outputs a stop bit (HIGH) and HIGH level is maintained until the next start bit is output. The transmitting complete interrupt factor flag FSTAx is set to "" at the point where the data transmitting is completed. When interrupt has been enabled, a transmitting complete interrupt is generated at this point. Set the following transmitting data using this interrupt. (5) epeat steps (3) to (4) for the number of bytes of transmitting data, and then set the transmit disable status by writing "" to the transmit enable register TXENx, when the transmitting is completed. No SC88655 TECHNICAL MANUAL EPSON 8

90 SEIAL INTEFACE Data receive procedure Data receiving XENx esets error flags PEx, OEx and FEx XENx Yes Error generated? No No eceiving interrupt? Yes eceived data reading from XDxXDx7 XTGx No eceiving complete? Yes Error processing If "with parity check" has been selected, a parity check is executed when data is transferred into the received data buffer from the shift register and if a parity error is detected, the error interrupt factor flag is set to "". When the interrupt has been enabled, an error interrupt is generated at this point just as in the framing error mentioned above. (4) ead the received data from XDxXDx7 using receiving complete interrupt. (5) Write "" to the receive control bit XTGx to inform that the receive data has been read out. When the following data is received prior to writing "" to XTGx, it is recognized as an overrun error and the error interrupt factor flag is set to "". When the interrupt has been enabled, an error interrupt is generated at this point just as in the framing error and parity error mentioned above. (6) epeat steps (3) to (5) for the number of bytes of receiving data, and then set the receive disable status by writing "" to the receive enable register XENx, when the receiving is completed. XENx End Fig..7.3 eceiving procedure in asynchronous mode The control procedure and operation during receiving is as follows. () Write "" in the receive enable register XENx to set the receiving disable status and to reset the respective PEx, OEx, FEx flags that indicate parity, overrun and framing errors. (2) Write "" in the receive enable register XENx to set into the receiving enable status. (3) The shift clock will change to enable from the point where the start bit (LOW) has been input from the SINx terminal and the receive data will be synchronized to the rising edge following the second clock, and will thus be successively incorporated into the shift register. After data bits have been incorporated, the stop bit is checked and, if it is not HIGH, it becomes a framing error and the error interrupt factor flag FSEx is set to "". When interrupt has been enabled, an error interrupt is generated at this point. When receiving is completed, data in the shift register is transferred to the received data buffer and the receiving complete interrupt flag FSECx is set to "". When interrupt has been enabled, a receiving complete interrupt is generated at this point. (When an overrun error is generated, the interrupt factor flag FSECx is not set to "" and a receiving complete interrupt is not generated.) eceive error During receiving the following three types of errors can be detected by an interrupt. () Parity error When writing "" to the EPx register to select "with parity check", a parity check (vertical parity check) is executed during receiving. After each data bit is sent a parity check bit is sent. The parity check bit is a "" or a "". Even parity checking will cause the sum of the parity bit and the other bits to be even. Odd parity causes the sum to be odd. This is checked on the receiving side. The parity check is performed when data received in the shift register is transferred to the received data buffer. It checks whether the parity check bit is a "" or a "" (the sum of the bits including the parity bit) and the parity set in the PMDx register match. When it does not match, it is recognized as an parity error and the parity error flag PEx and the error interrupt factor flag FSEx are set to "". When interrupt has been enabled, an error interrupt is generated at this point. The PEx flag is reset to "" by writing "". Even when this error has been generated, the received data corresponding to the error is transferred in the received data buffer and the receive operation also continues. The received data at this point cannot assured because of the parity error. 82 EPSON SC88655 TECHNICAL MANUAL

91 SEIAL INTEFACE (2) Framing error In asynchronous transfer, synchronization is adopted for each character at the start bit ("") and the stop bit (""). When receiving has been done with the stop bit set at "", the serial interface judges the synchronization to be off and a framing error is generated. When this error is generated, the framing error flag FEx and the error interrupt factor flag FSEx are set to "". When interrupt has been enabled, an error interrupt is generated at this point. The FEx flag is reset to "" by writing "". Even when this error has been generated, the received data corresponding to the error is transferred in the received data buffer and the receive operation also continues. However, even when it does not become a framing error with the following data receiving, such data cannot be assured. (3) Overrun error When the next data is received before "" is written to XTGx, an overrun error will be generated, because the previous receive data will be overwritten. When this error is generated, the overrun error flag OEx and the error interrupt factor flag FSEx are set to "". When interrupt has been enabled, an error interrupt is generated at this point. The OEx flag is reset to "" by writing "" into it. Even when this error has been generated, the received data corresponding to the error is transferred in the received data buffer and the receive operation also continues. Furthermore, when the timing for writing "" to XTGx and the timing for the received data transfer to the received data buffer overlap, it will be recognized as an overrun error. Timing chart Figure.7.4 show the asynchronous transfer timing chart. TXENx TXTGx (D) TXTGx (W) Sampling clock SOUTx D D D3 D4 D7 (In 8-bit mode/non parity) Interrupt (a) Transmit timing XENx XTGx (D) XTGx (W) Sampling clock SINx (In 8-bit mode/non parity) XDx OEx control signal OEx D D D3 D4 D7 D D D3 D4 D7 D D D3 D4 D7 st data 2nd data Interrupt (b) eceive timing Fig..7.4 Timing chart (asynchronous transfer, LSB first, stop bit = bit) SC88655 TECHNICAL MANUAL EPSON 83

92 SEIAL INTEFACE.8 Interrupt Function This serial interface includes a function that generates the below indicated three types of interrupts. Transmitting complete interrupt eceiving complete interrupt Error interrupt The interrupt factor flag FSxxx and the interrupt enable register ESxxx for the respective interrupt factors are provided and then the interrupt enable/ disable can be selected by the software. In addition, a priority level of the serial interface interrupt for the CPU can be optionally set at levels to 3 by the interrupt priority registers PSIFx and PSIFx. For details on the above mentioned interrupt control register and the operation following generation of an interrupt, see Chapter 7, "Interrupt and Standby Status". Figure.8. shows the configuration of the serial interface interrupt circuit. Transmitting complete interrupt This interrupt factor is generated at the point where the sending of the data written into the shift register has been completed and sets the interrupt factor flag FSTAx to "". When set in this manner, if the corresponding interrupt enable register ESTAx is set to "" and the corresponding interrupt priority registers PSIFx and PSIFx are set to a higher level than the setting of interrupt flags (I and I), an interrupt will be generated to the CPU. When "" has been written into the interrupt enable register ESTAx and interrupt has been disabled, an interrupt is not generated to the CPU. Even in this case, the interrupt factor flag FSTAx is set to "". The interrupt factor flag FSTAx is reset to "" by writing "". The following transmitting data can be set and the transmitting start (writing "" to TXTGx) can be controlled by generation of this interrupt factor. The exception processing vector address is set as follows: Ch. transmitting complete interrupt: 2AH Ch. transmitting complete interrupt: 3H Address Interrupt priority register PSIFx, PSIFx Error generation Address Interrupt factor flag FSEx Address Interrupt enable register ESEx Data bus eceive completion Address Address Interrupt factor flag FSECx Interrupt enable register ESECx Interrupt priority level judgment circuit Interrupt request Transmit completion Address Interrupt factor flag FSTAx Address Interrupt enable register ESTAx Fig..8. Configuration of serial interface interrupt circuit 84 EPSON SC88655 TECHNICAL MANUAL

93 SEIAL INTEFACE eceiving complete interrupt This interrupt factor is generated at the point where receiving has been completed and the receive data incorporated into the shift register has been transferred into the received data buffer and it sets the interrupt factor flag FSECx to "". When set in this manner, if the corresponding interrupt enable register ESECx is set to "" and the corresponding interrupt priority registers PSIFx and PSIFx are set to a higher level than the setting of interrupt flags (I and I), an interrupt will be generated to the CPU. When "" has been written into the interrupt enable register ESECx and interrupt has been disabled, an interrupt is not generated to the CPU. Even in this case, the interrupt factor flag FSECx is set to "". The interrupt factor flag FSECx is reset to "" by writing "". The generation of this interrupt factor permits the received data to be read. Also, the interrupt factor flag is set to "" when a parity error or framing error is generated. The exception processing vector address is set as follows: Ch. receiving complete interrupt: 28H Ch. receiving complete interrupt: 2EH Error interrupt This interrupt factor is generated at the point where a parity error, framing error or overrun error is detected during receiving and it sets the interrupt factor flag FSEx to "". When set in this manner, if the corresponding interrupt enable register ESEx is set to "" and the corresponding interrupt priority registers PSIFx and PSIFx are set to a higher level than the setting of interrupt flags (I and I), an interrupt will be generated to the CPU. When "" has been written in the interrupt enable register ESEx and interrupt has been disabled, an interrupt is not generated to the CPU. Even in this case, the interrupt factor flag FSEx is set to "". The interrupt factor flag FSEx is reset to "" by writing "". Since all three types of errors result in the same interrupt factor, you should identify the error that has been generated by the error flags PEx (parity error), OEx (overrun error) and FEx (framing error). The exception processing vector address is set as follows: Ch. receive error interrupt: 26H Ch. receive error interrupt: 2CH SC88655 TECHNICAL MANUAL EPSON 85

94 SEIAL INTEFACE.9 Details of Control egisters Table.9. show the serial interface control bits. Table.9.(a) Serial interface control bits Address Bit Name Function S Comment FF48 D7 STPB EP PMD D4 SCS D3 SCS SMD D SMD D ESIF SIF stop bit selection 2 bits bit Only for SIF parity enable register SIF parity mode selection SIF clock source selection SCS SCS Clock source Programmable timer fosc3 / 4 fosc3 / 8 fosc3 / 6 SIF mode selection SMD SMD Mode With parity Non parity Odd Even Asynchronous 8-bit Asynchronous 7-bit Clock synchronous slave Clock synchronous master SIF enable register Serial I/F I/O port FF49 D7 SDP FE SIF data input/output permutation selection SIF framing error flag W PE SIF parity error flag W D4 OE SIF overrun error flag W D3 XTG SIF receive trigger/status W XEN SIF receive enable D TXTG SIF transmit trigger/status W D TXEN SIF transmit enable FF4A D7 TXD7 SIF transmit data D7 (MSB) TX SIF transmit data TX SIF transmit data D4 TXD4 SIF transmit data D4 D3 TXD3 SIF transmit data D3 TX SIF transmit data D TXD SIF transmit data D D TXD SIF transmit data D (LSB) FF4B D7 D4 D3 D D XD7 X X XD4 XD3 X XD XD SIF receive data D7 (MSB) SIF receive data SIF receive data SIF receive data D4 SIF receive data D3 SIF receive data SIF receive data D SIF receive data D (LSB) MSB first LSB first Error No error eset () No operation Error No error eset () No operation Error No error eset () No operation un Stop Trigger No operation Enable Disable un Stop Trigger No operation Enable Disable High Low High Low asynchronous mode In the clock synchronous slave mode, external clock is selected. Only for asynchronous mode X X 86 EPSON SC88655 TECHNICAL MANUAL

95 SEIAL INTEFACE Table.9.(b) Serial interface control bits Address Bit Name Function S Comment FF4C D7 STPB EP PMD D4 SCS D3 SCS SMD D SMD D ESIF SIF stop bit selection 2 bits bit Only for SIF parity enable register SIF parity mode selection SIF clock source selection SCS SCS Clock source Programmable timer fosc3 / 4 fosc3 / 8 fosc3 / 6 SIF mode selection SMD SMD Mode With parity Non parity Odd Even Asynchronous 8-bit Asynchronous 7-bit Clock synchronous slave Clock synchronous master SIF enable register Serial I/F I/O port FF4D D7 SDP FE SIF data input/output permutation selection SIF framing error flag W PE SIF parity error flag W D4 OE SIF overrun error flag W D3 XTG SIF receive trigger/status W XEN SIF receive enable D TXTG SIF transmit trigger/status W D TXEN SIF transmit enable FF4E D7 TXD7 SIF transmit data D7 (MSB) TX SIF transmit data TX SIF transmit data D4 TXD4 SIF transmit data D4 D3 TXD3 SIF transmit data D3 TX SIF transmit data D TXD SIF transmit data D D TXD SIF transmit data D (LSB) FF4F D7 D4 D3 D D XD7 X X XD4 XD3 X XD XD SIF receive data D7 (MSB) SIF receive data SIF receive data SIF receive data D4 SIF receive data D3 SIF receive data SIF receive data D SIF receive data D (LSB) MSB first LSB first Error No error eset () No operation Error No error eset () No operation Error No error eset () No operation un Stop Trigger No operation Enable Disable un Stop Trigger No operation Enable Disable High Low High Low asynchronous mode In the clock synchronous slave mode, external clock is selected. Only for asynchronous mode X X SC88655 TECHNICAL MANUAL EPSON 87

96 SEIAL INTEFACE ESIF: FF48H D ESIF: FF4CH D Configures the serial interface terminals. When "" is written: Serial input/output terminal When "" is written: I/O port terminal eading: Valid The ESIFx is the serial interface enable register and PP3 (P4P7) terminals become serial input/ output terminals (SINx, SOUTx, SCLKx, SDYx) when "" is written, and they become I/O port terminals when "" is written. Also, see Table.3.2 for the terminal settings according to the transfer modes. At initial reset, ESIFx is set to "" (I/O port). SMD, SMD: FF48H D, SMD, SMD: FF4CH D, Set the transfer modes according to Table.9.2. Table.9.2 Transfer mode settings SMDx SMDx Mode Asynchronous 8-bit Asynchronous 7-bit Clock synchronous slave Clock synchronous master SMDx and SMDx can also read out. At initial reset, this register is set to "" (clock synchronous master mode). SCS, SCS: FF48H D3, D4 SCS, SCS: FF4CH D3, D4 Select the clock source according to Table.9.3. Table.9.3 Clock source selection SCSx SCSx Clock source Programmable timer (Ch. ) Programmable timer 7 (Ch. ) fosc3 / 4 fosc3 / 8 fosc3 / 6 SCSx and SCSx can also be read out. In the clock synchronous slave mode, setting of this register is invalid. At initial reset, this register is set to "" (fosc3/6). PMD: FF48H PMD: FF4CH Selects odd parity/even parity. When "" is written: Odd parity When "" is written: Even parity eading: Valid When "" is written to PMDx, odd parity is selected and even parity is selected when "" is written. The parity check and addition of a parity bit is only valid when "" has been written to EPx. When "" has been written to EPx, the parity setting by PMDx becomes invalid. At initial reset, PMDx is set to "" (even parity). EP: FF48H EP: FF4CH Selects the parity function. When "" is written: With parity When "" is written: Non parity eading: Valid Selects whether or not to check parity of the received data and to add a parity bit to the transmitting data. When "" is written to EPx, the most significant bit of the received data is considered to be the parity bit and a parity check is executed. A parity bit is added to the transmitting data. When "" is written, neither checking is done nor is a parity bit added. Parity is valid only in asynchronous mode and the EPx setting becomes invalid in the clock synchronous mode. At initial reset, EPx is set to "" (non parity). STPB: FF48H D7 STPB: FF4CH D7 Selects the stop bit length for asynchronous data transfer. When "" is written: 2 bits When "" is written: bit eading: Valid STPBx is the stop bit select register that is effective in asynchronous mode. When "" is written to STPBx, the stop bit length is set to 2 bits, and when "" is written, it is set to bit. In clock synchronous mode, no start/stop bits can be added to transfer data. Therefore, setting STPBx becomes invalid. At initial reset, STPBx is set to "" ( bit). 88 EPSON SC88655 TECHNICAL MANUAL

97 SEIAL INTEFACE TXEN: FF49H D TXEN: FF4DH D Sets the serial interface to the transmitting enable status. When "" is written: Transmitting enable When "" is written: Transmitting disable eading: Valid When "" is written to TXENx, the serial interface shifts to the transmitting enable status and shifts to the transmitting disable status when "" is written. Set TXENx to "" when making the initial settings of the serial interface and similar operations. At initial reset, TXENx is set to "" (transmitting disable). TXTG: FF49H D TXTG: FF4DH D Functions as the transmitting start trigger and the operation status indicator (transmitting/stop status). When "" is read: During transmitting When "" is read: During stop When "" is written: Transmitting start When "" is written: Invalid Starts the transmitting when "" is written to TXTGx after writing the transmitting data. TXTGx can be read as the status. When set to "", it indicates transmitting operation, and "" indicates transmitting stop. At initial reset, TXTGx is set to "" (during stop). XEN: FF49H XEN: FF4DH Sets the serial interface to the receiving enable status. When "" is written: eceiving enable When "" is written: eceiving disable eading: Valid When "" is written to XENx, the serial interface shifts to the receiving enable status and shifts to the receiving disable status when "" is written. Set XENx to "" when making the initial settings of the serial interface and similar operations. At initial reset, XENx is set to "" (receiving disable). XTG: FF49H D3 XTG: FF4DH D3 Functions as the receiving start trigger or preparation for the following data receiving and the operation status indicator (during receiving/during stop). When "" is read: During receiving When "" is read: During stop When "" is written: eceiving start/following data receiving preparation When "" is written: Invalid XTGx has a slightly different operation in the clock synchronous system and the asynchronous system. The XTGx in the clock synchronous system, is used as the trigger for the receiving start. Writes "" into XTGx to start receiving at the point where the receive data has been read and the following receive preparation has been done. (In the slave mode, SDYx becomes "" at the point where "" has been written into the XTGx.) XTGx is used in the asynchronous system for preparation of the following data receiving. eads the received data located in the received data buffer and writes "" into XTGx to inform that the received data buffer has shifted to empty. When "" has not been written to XTGx, the overrun error flag OEx is set to "" at the point where the following receiving has been completed. (When the receiving has been completed between the operation to read the received data and the operation to write "" into XTGx, an overrun error occurs.) In addition, XTGx can be read as the status. In either clock synchronous mode or asynchronous mode, when XTGx is set to "", it indicates receiving operation and when set to "", it indicates that receiving has stopped. At initial reset, XTGx is set to "" (during stop). OE: FF49H D4 OE: FF4DH D4 Indicates the generation of an overrun error. When "" is read: Error When "" is read: No error When "" is written: eset to "" When "" is written: Invalid OEx is an error flag that indicates the generation of an overrun error and becomes "" when an error has been generated. An overrun error is generated when the receiving of data has been completed prior to the writing of "" to XTGx in the asynchronous mode. OEx is reset to "" by writing "". At initial reset and when XENx is "", OEx is set to "" (no error). SC88655 TECHNICAL MANUAL EPSON 89

98 SEIAL INTEFACE PE: FF49H PE: FF4DH Indicates the generation of a parity error. When "" is read: Error When "" is read: No error When "" is written: eset to "" When "" is written: Invalid PEx is an error flag that indicates the generation of a parity error and becomes "" when an error has been generated. When a parity check is performed in the asynchronous mode, if data that does not match the parity is received, a parity error is generated. PEx is reset to "" by writing "". At initial reset and when XENx is "", PEx is set to "" (no error). FE: FF49H FE: FF4DH Indicates the generation of a framing error. When "" is read: Error When "" is read: No error When "" is written: eset to "" When "" is written: Invalid FEx is an error flag that indicates the generation of a framing error and becomes "" when an error has been generated. When the stop bit for the receiving of the asynchronous mode has become "", a framing error is generated. FEx is reset to "" by writing "". At initial reset and when XENx is "", FEx is set to "" (no error). SDP: FF49H D7 SDP: FF4DH D7 Selects the serial data input/output permutation. When "" is written: MSB first When "" is written: LSB first eading: Valid Select whether the data input/output permutation will be MSB first or LSB first. At initial reset, SDPx is set to "" (LSB first). TXDTXD7: FF4AH TXDTXD7: FF4EH Write the transmitting data into the transmit shift register. When "" is written: HIGH level When "" is written: LOW level Write the transmitting data prior to starting transmitting. In the case of continuous transmitting, wait for the transmitting complete interrupt, then write the data. The TXDx7 becomes invalid for the asynchronous 7-bit mode. Converted serial data for which the bits set at "" as HIGH (VDD) level and for which the bits set at "" as LOW (VSS) level are output from the SOUTx terminal. At initial reset, transmitting data is undefined. XDXD7: FF4BH XDXD7: FF4FH The received data can be read out. When "" is read: HIGH level When "" is read: LOW level The data from the received data buffer can be read out. Since the sift register is provided separately from this buffer, reading can be done during the receive operation in the asynchronous mode. (The buffer function is not used in the clock synchronous mode.) ead the data after waiting for the receiving complete interrupt. When performing parity check in the asynchronous 7-bit mode, "" is loaded into the 8th bit (XDx7) that corresponds to the parity bit. The serial data input from the SINx terminal is level converted, making the HIGH (VDD) level bit "" and the LOW (VSS) level bit "" and is then loaded into this buffer. At initial reset, the buffer content is undefined. 9 EPSON SC88655 TECHNICAL MANUAL

99 SEIAL INTEFACE. Precautions () Be sure to initialize the serial interface mode in the transmitting/receiving disable status (TXENx = XENx = ""). (2) Do not perform double trigger (writing "") to TXTGx (XTGx) when the serial interface is in the transmitting (receiving) operation. Furthermore, do not execute the SLP instruction. (When executing the SLP instruction, set TXENx = XENx = "".) (3) In the clock synchronous mode, since one clock line (SCLKx) is shared for both transmitting and receiving, transmitting and receiving cannot be performed simultaneously. (Half duplex only is possible in clock synchronous mode.) Consequently, be sure not to write "" to XTGx (TXTGx) when TXTGx (XTGx) is "". (4) When a parity error or framing error is generated during receiving in the asynchronous mode, the receiving error interrupt factor flag FSEx is set to "" prior to the receiving complete interrupt factor flag FSECx for the time indicated in Table... Consequently, when an error is generated, you should reset the receiving complete interrupt factor flag FSECx to "" by providing a wait time in error processing routines and similar routines. When an overrun error is generated, the receiving complete interrupt factor flag FSECx is not set to "" and a receiving complete interrupt is not generated. Table.. Time difference between FSEx and FSECx on error generation Clock source Time difference fosc3 / n /2 cycles of fosc3 / n Programmable timer cycle of timer underflow (5) When the demultiplied signal of the OSC3 oscillation circuit is made the clock source, it is necessary to turn the OSC3 oscillation ON, prior to using the serial interface. A time interval of several msec to several msec, from the turning ON of the OSC3 oscillation circuit to until the oscillation stabilizes, is necessary, due to the oscillation element that is used. Consequently, you should allow an adequate waiting time after turning ON of the OSC3 oscillation, before starting transmitting/receiving of serial interface. (The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts. efer to the oscillation start time example indicated in Chapter 9, "Electrical Characteristics".) At initial reset, the OSC3 oscillation circuit is set to ON status. SC88655 TECHNICAL MANUAL EPSON 9

100 2 CLOCK TIME 2 CLOCK TIME 2. Configuration of Clock Timer The SC88655 has built in a clock timer that uses the OSC oscillation circuit as clock source. The clock timer is composed of an 8-bit binary counter that uses the 256 Hz signal (when fosc = khz) dividing fosc as its input clock and can read the data of each bit (28 Hz) by software. Normally, this clock timer is used for various timing functions such as clocks. The configuration of the clock timer is shown in Figure 2... Note: The frequency values described in this chapter assumes that the OSC oscillation frequency (fosc) is khz. If fosc is not khz, this timer cannot be used for clocking. 2.2 Interrupt Function The clock timer can generate an interrupt by each of the 32 Hz, 8 Hz, 2 Hz and Hz signals. The configuration of the clock timer interrupt circuit is shown in Figure Interrupts are generated by respectively setting the corresponding interrupt factor flags FTM32, FTM8, FTM2 and FTM at the falling edge of the 32 Hz, 8 Hz, 2 Hz and Hz signals to "". Interrupt can be prohibited by the setting the interrupt enable registers ETM32, ETM8, ETM2 and ETM corresponding to each interrupt factor flag. In addition, a priority level of the clock timer interrupt for the CPU can be optionally set at levels to 3 by the interrupt priority registers PTM and PTM. For details on the above mentioned interrupt control register and the operation following generation of an interrupt, see Chapter 7, "Interrupt and Standby Status". The exception processing vector addresses for each interrupt factor are respectively set as shown below. 32 Hz interrupt: 32H 8 Hz interrupt: 34H 2 Hz interrupt: 36H Hz interrupt: 38H Figure shows the timing chart for the clock timer. Data bus OSC oscillation circuit fosc Divider 256 Hz Clock timer 28 Hz 64 Hz 32 Hz 6 Hz 8 Hz TMDTMD7 4 Hz 2 Hz Hz TMST TMUN Clock timer reset Clock timer un/stop Interrupt control circuit Fig. 2.. Configuration of clock timer Interrupt request 92 EPSON SC88655 TECHNICAL MANUAL

101 2 CLOCK TIME Address Interrupt priority register PTM, PTM 32 Hz falling edge Address Interrupt factor flag FTM32 Address Interrupt enable register ETM32 8 Hz falling edge Address Interrupt factor flag FTM8 Data bus Address 2 Hz falling edge Address Interrupt enable register ETM8 Interrupt factor flag FTM2 Interrupt priority level judgment circuit Interrupt request Address Interrupt enable register ETM2 Hz falling edge Address Interrupt factor flag FTM Address Interrupt enable register ETM Fig Configuration of clock timer interrupt circuit OSC/ Hz TMD 28 Hz TMD 64 Hz TM 32 Hz TMD3 6 Hz TMD4 8 Hz TM 4 Hz TM 2 Hz TMD7 Hz 32 Hz interrupt 8 Hz interrupt 2 Hz interrupt Hz interrupt Fig Timing chart of clock timer SC88655 TECHNICAL MANUAL EPSON 93

102 2 CLOCK TIME 2.3 Details of Control egisters Table 2.3. shows the clock timer control bits. Table 2.3. Clock timer control bits Address Bit Name Function S Comment FF4 D7 D4 D3 D D TMST TMUN Clock timer reset Clock timer un/stop control eset un No operation Stop FF4 D7 TMD7 Clock timer data Hz TM Clock timer data 2 Hz TM Clock timer data 4 Hz D4 TMD4 Clock timer data 8 Hz D3 TMD3 Clock timer data 6 Hz High Low TM Clock timer data 32 Hz D TMD Clock timer data 64 Hz D TMD Clock timer data 28 Hz W Constantly "" when being read TMDTMD7: FF4H The clock timer data can be read out. Each bit of TMDTMD7 and frequency correspondence are as follows: TMD: 28 Hz TMD4: 8 Hz TMD: 64 Hz TM: 4 Hz TM: 32 Hz TM: 2 Hz TMD3: 6 Hz TMD7: Hz Since the TMDTMD7 is exclusively for reading, the write operation is invalid. At initial reset, the timer data is set to "H". TMST: FF4H D esets the clock timer. When "" is written: Clock timer reset When "" is written: No operation eading: Always "" The clock timer is reset by writing "" to the TMST. When the clock timer is reset in the UN status, it restarts immediately after resetting. In the case of the STOP status, the reset data "H" is maintained. No operation results when "" is written to the TMST. Since the TMST is exclusively for writing, it always becomes "" during reading. TMUN: FF4H D Controls UN/STOP of the clock timer. When "" is written: UN When "" is written: STOP eading: Valid The clock timer starts up-counting by writing "" to the TMUN and stops by writing "". In the STOP status, the count data is maintained until it is reset or set in the next UN status. Also, when the STOP status changes to the UN status, the data that was maintained can be used for resuming the count. At initial reset, the TMUN is set to "" (STOP). 94 EPSON SC88655 TECHNICAL MANUAL

103 2 CLOCK TIME 2.4 Precautions () The clock timer is actually made to UN/STOP in synchronization with the falling edge of the 256 Hz signal after writing to the TMUN register. Consequently, when "" is written to the TMUN, the timer shifts to STOP status when the counter is incremented "". The TMUN maintains "" for reading until the timer actually shifts to STOP status. Figure 2.4. shows the timing chart of the UN/STOP control. 256 Hz TMUN(D) TMUN(W) TMDx 57H 58H 59H 5AH 5BH 5CH Fig Timing chart of UN/STOP control (2) The SLP instruction is executed when the clock timer is in the UN status (TMUN = ""). The clock timer operation will become unstable when returning from SLEEP status. Therefore, when shifting to SLEEP status, set the clock timer to STOP status (TMUN = "") prior to executing the SLP instruction. SC88655 TECHNICAL MANUAL EPSON 95

104 3 POGAMMABLE TIME 3 POGAMMABLE TIME 3. Configuration of Programmable Timer The SC88655 has four built-in 6-bit programmable timer systems. Each system timer consists of a 6-bit presettable down counter, and can be used as 6-bit channel or 8-bit 2 channels of programmable timer. Furthermore, they function as event counters using the input port terminal. Figures 3.. and 3..2 show the configuration of the 6-bit programmable timers. Two 8-bit down counters, the reload data register and compare data register corresponding to each down counter are arranged in the 6-bit programmable timer. fosc3/fosc Input port (P24) Clock output Underflow interrupt Compare match interrupt Prescaler/clock control circuit Clock output circuit Interrupt circuit INCL EXCL TOUT Clock selection circuit Control circuit Underflow signal The reload data register is used to set an initial value to the down counter. The compare data register stores data for comparison with the content of the down counter. By setting these registers, a PWM waveform is generated and it can be output to external devices as the TOUT,, 2 or 3 signal. Furthermore, the serial interface clock is generated from the underflow signal of Timer for serial interface Ch. or Timer 7 for Ch.. The Timer 5 underflow signal can be used to set the source clock for the display timing generator. Underflow Compare match Timer 8-bit reload data register (D) 8-bit down counter (PTM) Comparator 8-bit compare data register (CD) Timer control registers fosc3/fosc Input port (P24) Prescaler/clock control circuit INCL EXCL Clock selection circuit Timer 8-bit reload data register (D) Clock output To serial I/F (Ch. ) Underflow interrupt Compare match interrupt fosc3/fosc Input port (P25) Clock output circuit Interrupt circuit Prescaler/clock control circuit TOUT INCL2 EXCL Control circuit Clock selection circuit Underflow Compare match 8-bit down counter (PTM) Comparator 8-bit compare data register (CD) Timer control registers Timer 2 8-bit reload data register () Data bus Clock output Underflow interrupt Compare match interrupt Clock output circuit Interrupt circuit TOUT2 TOUT2 Control circuit Underflow signal Underflow Compare match 8-bit down counter (PTM2) Comparator 8-bit compare data register (C) Timer 2 control registers fosc3/fosc Input port (P25) Clock output Underflow interrupt Compare match interrupt Prescaler/clock control circuit Clock output circuit Interrupt circuit INCL3 EXCL TOUT3 TOUT3 Clock selection circuit Control circuit Underflow Compare match Timer 3 8-bit reload data register (D3) 8-bit down counter (PTM3) Comparator 8-bit compare data register (CD3) Timer 3 control registers Fig. 3.. Configuration of 6-bit programmable timer (Timers 3) 96 EPSON SC88655 TECHNICAL MANUAL

105 3 POGAMMABLE TIME fosc3/fosc Input port (P26) Prescaler/clock control circuit INCL4 EXCL2 Clock selection circuit Timer 4 8-bit reload data register (D4) 8-bit down counter (PTM4) Underflow interrupt Compare match interrupt Interrupt circuit Control circuit Underflow Compare match Comparator 8-bit compare data register (CD4) Underflow signal Timer 4 control registers fosc3/fosc Input port (P26) Prescaler/clock control circuit INCL5 EXCL2 Clock selection circuit Timer 5 8-bit reload data register () To LCD driver Underflow interrupt Compare match interrupt Interrupt circuit Control circuit Underflow Compare match 8-bit down counter (PTM5) Comparator 8-bit compare data register (C) fosc3/fosc Input port (P27) Prescaler/clock control circuit INCL6 EXCL3 Clock selection circuit Timer 5 control registers Timer 6 8-bit reload data register () Data bus 8-bit down counter (PTM6) Underflow interrupt Compare match interrupt Interrupt circuit Control circuit Underflow Compare match Comparator 8-bit compare data register (C) Underflow signal Timer 6 control registers fosc3/fosc Input port (P27) Prescaler/clock control circuit INCL7 EXCL3 Clock selection circuit Timer 7 8-bit reload data register (D7) To serial I/F (Ch. ) Underflow interrupt Compare match interrupt Interrupt circuit Control circuit Underflow Compare match 8-bit down counter (PTM7) Comparator 8-bit compare data register (CD7) Timer 7 control registers Fig Configuration of 6-bit programmable timer (Timers 47) 3.2 Operation Mode Timers and, Timers 2 and 3, Timers 4 and 5, or Timers 6 and 7 can be used as two channels of 8-bit timers or one channel of 6-bit timer. Two kinds of operation modes are provided corresponding to this configuration, and it can be selected by the 8/ 6-bit mode selection registers MODE6_A (for Timer ) through MODE6_D (for Timer 67). When "" is set to the MODE6_A register, Timers and enter the 8-bit mode (8-bit 2 channels) and when "" is set, they enter the 6-bit mode (6-bit channel). In the 8-bit mode, Timers and can be controlled individually. In the 6-bit mode, the underflow signal of Timer is used as the input clock of Timer so that the down counters operate as a 6-bit counter. The timer in the 6-bit mode is controlled with the control registers for Timer except for the clock output. MODE6_B through MODE6_D have the same function. Figure 3.2. shows the timer configuration depending on the operation mode and Table 3.2. shows the configuration of the control registers. SC88655 TECHNICAL MANUAL EPSON 97

106 3 POGAMMABLE TIME [8-bit mode] 8-bit data [6-bit mode] Low-order 8-bit data Timer input clock Timer Interrupt request TOUT output Timer input clock Timer Timer input clock Timer Interrupt request TOUT output Timer underflow signal Timer Interrupt request TOUT output 8-bit data High-order 8-bit data Fig Counter configuration in 8- and 6-bit mode (example of Timers and ) Table 3.2.(a) Control registers in 8-bit mode (example of Timers and ) Address Bit Name Function S Comment FF3 D7 MODE6_A PTM 8/6-bit mode selection 6-bit x 8-bit x 2 PTNEN_A External clock noise rejector selection Enable Disable D4 register D3 PTOUT PTM clock output control PTUN PTM un/stop control On un Off Stop D PSET PTM preset Preset No operation D CKSEL PTM input clock selection External clock Internal clock FF3 D7 D4 register D3 PTOUT PTM clock output control PTUN PTM un/stop control On un Off Stop D PSET PTM preset Preset No operation D CKSEL PTM input clock selection External clock Internal clock "" when being read eserved register W "" when being read W Constantly "" when being read eserved register "" when being read Table 3.2.(b) Control registers in 6-bit mode (example of Timers and ) Address Bit Name Function S Comment FF3 D7 MODE6_A PTM 8/6-bit mode selection 6-bit x 8-bit x 2 PTNEN_A External clock noise rejector selection Enable Disable D4 Invalid (fixed at "") Invalid Fixed at "" D3 PTOUT Invalid (fixed at "") PTUN PTM un/stop control Invalid un Fixed at "" Stop D PSET PTM preset Preset No operation D CKSEL PTM input clock selection External clock Internal clock "" when being read eserved register W "" when being read FF3 D7 D4 register Constantly "" when being read eserved register D3 PTOUT PTM clock output control PTUN Invalid (fixed at "") On Invalid Off Fixed at "" D D PSET CKSEL Invalid (fixed at "") Invalid (fixed at "") Invalid Invalid Fixed at "" Fixed at "" W "" when being read Note: The register names contain a timer number (7) to identify the timer to which the register belongs. The following explanation uses "x" instead of the timer number except when it is required. For example, PTUNx represents PTUN through PTUN7. Furthermore, a pair of timers are described as Timer(L) and Timer(H) in explanations for 6-bit mode. Timer(L) = Timer, Timer 2, Timer 4 or Timer 6 Timer(H) = Timer, Timer 3, Timer 5 or Timer 7 This is used for register names. 98 EPSON SC88655 TECHNICAL MANUAL

107 3.3 Setting of Input Clock The clock to be input to the counter can be selected from either the internal clock or external clock by the input clock selection register (CKSEL) provided for each timer. The internal clock is an output of the prescaler. The external clock is used for the event counter function. A signal from the I/ O port is used as the count clock. Table 3.3. shows the input clock selection register and input clock of each timer. Table 3.3. Input clock selection Timer Timer Timer Timer 2 Timer 3 Timer 4 Timer 5 Timer 6 Timer 7 egister setting CKSEL = "" CKSEL = "" CKSEL = "" CKSEL = "" CKSEL2 = "" CKSEL2 = "" CKSEL3 = "" CKSEL3 = "" CKSEL4 = "" CKSEL4 = "" CKSEL5 = "" CKSEL5 = "" CKSEL6 = "" CKSEL6 = "" CKSEL7 = "" CKSEL7 = "" Input clock INCL (Prescaler) EXCL (P24 input) INCL (Prescaler) EXCL (P24 input) INCL2 (Prescaler) EXCL (P25 input) INCL3 (Prescaler) EXCL (P25 input) INCL4 (Prescaler) EXCL2 (P26 input) INCL5 (Prescaler) EXCL2 (P26 input) INCL6 (Prescaler) EXCL3 (P27 input) INCL7 (Prescaler) EXCL3 (P27 input) When the external clock is selected, a signal from the I/O port is input to the programmable timer. An noise rejector is incorporated in the external clock input circuit and it can be enabled/disabled using the external clock noise rejector select registers PTNEN_A through PTNEN_D corresponding to the EXCL through EXCL3 inputs. Writing "" to PTNEN_A (D) enables the noise rejector for the external clock EXCL (3). The noise rejector regards pulses less than a 6/fOSC seconds in width as noise and rejects them. The external clock must have a pulse width at least double the rejected width. Note: An external clock cannot be input when the OSC oscillation circuit is OFF. When using the noise rejector, be sure to turn the OSC oscillation circuit ON. When PTNEN_A (D) is "", the external clock bypasses the noise rejector. When the internal clock is used, select a source clock and a division ratio of the prescaler to set the clock frequency for each timer. The source clock is specified using the source clock selection register PTFx provided for each timer. When "" is written to PTFx, the OSC clock is selected as the source clock for Timer x. When "" is written, the OSC3 clock is selected. The OSC3 oscillation circuit must be on before the OSC3 can be used. See Chapter 8, "Oscillation Circuits" for the controlling of the OSC3 oscillation circuit. 3 POGAMMABLE TIME The prescaler provides the division ratio selection register PSTxPSTx2 for each timer. Note that the division ratio varies depending on the selected source clock. Table Division ratio and control registers egister Dividing ratio PSTx2 PSTx PSTx (OSC3) fosc3/496 fosc3/24 fosc3/256 fosc3/64 fosc3/32 fosc3/8 fosc3/2 fosc3/ (OSC) fosc/28 fosc/64 fosc/32 fosc/6 fosc/8 fosc/4 fosc/2 fosc/ The set clock is output to Timer x by writing "" to the clock control register PPTx. When the 6-bit mode is selected, the programmable timer operates with the clock input to Timer(L), and Timer(H) inputs the Timer(L) underflow signal as the clock. Therefore, the setting of Timer(H) input clock is invalid. 3.4 Operation and Control of Timer eload data register and setting of initial value The reload data register (Dx) is used to set an initial value of the down counter. In the 8-bit mode, Dx is used as an 8-bit register separated for each timer. In the 6-bit mode, the D(L) register is handled as low-order 8 bits of reload data, and the D(H) register is as high-order 8 bits. The reload data register can be read and written, and all the registers are set to FFH at initial reset. Data written in this register is loaded into the down counter, and a down counting starts from the value. The down counter is preset, in the following two cases: ) When software presets The software preset can be done using the preset control bits PSETx corresponding to Timer x. When the preset control bit is set to "", the content of the reload data register is loaded into the down counter at that point. In the 6-bit mode, a 6-bit reload data is loaded all at one time by setting PSET(L). In this case, writing to PSET(H) is invalid. 2) When down counter has underflowed during a count Since the down counter presets the reload data by the underflow, the underflow period is decided according to the value set in the reload data register. This underflow generates an interrupt, and controls the clock (TOUTx signal) output. SC88655 TECHNICAL MANUAL EPSON 99

108 3 POGAMMABLE TIME Compare data register The programmable timer has a built-in data comparator so that count data can be compared with an optional value. The compare data register (CDx) is used to set the value to be compared. In the 8-bit mode, CDx is used as an 8-bit register separated for each timer. In the 6-bit mode, the CD(L) register is handled as low-order 8 bits of compare data, and the CD(H) register is as high-order 8 bits. The compare data register can be read and written, and all the registers are set to H at initial reset. The programmable timer compares count data with the compare data register (CDx), and generates a compare match signal when they become the same value. This compare match signal generates an interrupt, and controls the clock (TOUTx signal) output. Timer operation Timer is equipped with PTUNx register which controls the UN/STOP of the timer. Timer x starts down counting by writing "" to the PTUNx register. However, it is necessary to control the input clock and to preset the reload data before starting a count. When "" is written to PTUNx register, clock input is prohibited, and the count stops. This UN/STOP control does not affect data in the counter. The data in the counter is maintained during count deactivation, so it is possible to resume counting from the data. In the 8-bit mode, the timers can be controlled individually by the PTUNx register. In the 6-bit mode, the PTUN(L) register controls a pair of timers as a 6-bit timer. In this case, control of the PTUN(H) register is invalid. The buffers PTMx is attached to the counter, and reading is possible in optional timing. When the counter agrees with the data set in the compare data register during down counting, the timer generates a compare match interrupt. And, when the counter underflows, an underflow interrupt is generated, and the initial value set in the reload data register is loaded to the counter. The interrupt generated does not stop the down counting. After an underflow interrupt is generated, the counter continues counting from the initial value reloaded. PTUNx PSETx Dx CDx Input clock PTMx7 PTMx6 PTMx5 PTMx4 PTMx3 PTMx2 PTMx PTMx Note: Preset A6H 58H A6H 58H Compare match interrupt generation Fig Basic operation timing of counter (an example of 8-bit mode) F3H 58H eload Underflow interrupt generation The programmable timer counts down at the falling edge of the input clock and at the same time it generates an interrupt if the counter underflows. Then it starts loading the reload data to the counter and the counter data is determined at the next rising edge of the input clock (period shown in as in the figure). To avoid improper reloading, do not rewrite the reload data after an interrupt occurs until the counter data is determined including the reloading period. Be especially careful when using the OSC (low-speed clock) as the clock source of the programmable timer and the CPU is operating with the OSC3 (high-speed clock). EPSON SC88655 TECHNICAL MANUAL

109 3 POGAMMABLE TIME 3.5 Interrupt Function The 6-bit programmable timer can generate an interrupt with the compare match signal and underflow signal of each timer. Figure 3.5. shows the configuration of the 6-bit programmable timer interrupt circuit. The compare match signal and underflow signal of each timer set the corresponding interrupt factor flag to "". At that point, the interrupt is generated. The interrupt can also be prohibited by setting the interrupt enable register to correspond with the interrupt factor flag. Furthermore, the priority level of the interrupt for the CPU can be set to an optional level (3) using the interrupt priority register. Table 3.5. shows the interrupt factor flags, interrupt enable registers and interrupt priority registers corresponding to the interrupt factors. In the 8-bit mode, the compare match interrupt factor flag and underflow interrupt factor flag are individually set to "" by the timers. In the 6-bit mode, the interrupt factor flags of Timer(H) are set to "" by the compare match and underflow in 6 bits. efer to Chapter 7, "Interrupt and Standby Status", for details of the interrupt control registers and operations subsequent to interrupt generation. The exception processing vector addresses for the 6- bit programmable timer interrupt are set as follows: Timer compare match interrupt: 24H Timer underflow interrupt: 22H Timer underflow interrupt: 2H Timer compare match interrupt: EH Timer 2 underflow interrupt: CH Timer 2 compare match interrupt: AH Timer 3 underflow interrupt: 8H Timer 3 compare match interrupt: 6H Timer 4 underflow interrupt: 48H Timer 4 compare match interrupt: 46H Timer 5 underflow interrupt: 44H Timer 5 compare match interrupt: 42H Timer 6 underflow interrupt: 4H Timer 6 compare match interrupt: 3EH Timer 7 underflow interrupt: 3CH Timer 7 compare match interrupt: 3AH Interrupt factor Timer Compare match Counter underflow Timer Counter underflow Compare match Timer 2 Counter underflow Compare match Timer 3 Counter underflow Compare match Timer 4 Counter underflow Compare match Timer 5 Counter underflow Compare match Timer 6 Counter underflow Compare match Timer 7 Counter underflow Compare match Table 3.5. Interrupt control registers Interrupt factor flag Interrupt enable register Name Address Dx Name Address Dx FTC FFBH D ETC FF5H D FTU FFBH D ETU FF5H D FTU FFBH ETU FF5H FTC FFBH D3 ETC FF5H D3 FTU2 FFBH D4 ETU2 FF5H D4 FTC2 FFBH ETC2 FF5H FTU3 FFBH ETU3 FF5H FTC3 FFBH D7 ETC3 FF5H D7 FTU4 FFEH D ETU4 FF8H D FTC4 FFEH D ETC4 FF8H D FTU5 FFEH ETU5 FF8H FTC5 FFEH D3 ETC5 FF8H D3 FTU6 FFEH D4 ETU6 FF8H D4 FTC6 FFEH ETC6 FF8H FTU7 FFEH ETU7 FF8H FTC7 FFEH D7 ETC7 FF8H D7 Interrupt priority register Name Address Dx PPT FFH PPT FFH D3 PPT2 PPT3 PPT4 PPT5 PPT6 PPT7 FFH D4 FFH FFH D4 FFH FFH FFH D7 SC88655 TECHNICAL MANUAL EPSON

110 3 POGAMMABLE TIME Address Underflow Address Interrupt priority register PPT, PPT Interrupt factor flag FTU Address Compare match Address Address Interrupt enable register ETU Interrupt factor flag FTC Interrupt enable register ETC Interrupt priority level judgment circuit Timer Timer Timer interrupt request Timer interrupt request Address Underflow Address Interrupt priority register PPT2, PPT3 Interrupt factor flag FTU2 Data bus Address Compare match Address Address Address Underflow Address Interrupt enable register ETU2 Interrupt factor flag FTC2 Interrupt enable register ETC2 Interrupt priority register PPT4, PPT5 Interrupt factor flag FTU4 Interrupt priority level judgment circuit Timer 2 Timer 3 Timer 2 interrupt request Timer 3 interrupt request Address Compare match Address Address Interrupt enable register ETU4 Interrupt factor flag FTC4 Interrupt enable register ETC4 Interrupt priority level judgment circuit Timer 4 Timer 5 Timer 4 interrupt request Timer 5 interrupt request Address Underflow Address Address Compare match Address Address Interrupt priority register PPT6, PPT7 Interrupt factor flag FTU6 Interrupt enable register ETU6 Interrupt factor flag FTC6 Interrupt enable register ETC6 Interrupt priority level judgment circuit Timer 6 Timer 7 Fig Configuration of 6-bit programmable timer interrupt circuit Timer 6 interrupt request Timer 7 interrupt request 2 EPSON SC88655 TECHNICAL MANUAL

111 3 POGAMMABLE TIME 3.6 Setting TOUT Outputs The 6-bit programmable timer can generate TOUT signals with the underflow and compare match signals of each timer. The TOUT signal generated in the 6-bit programmable timer can be output from the I/O port terminal shown in Table 3.6. so that a clock is supplied for external devices or it can be used as a PWM waveform output. Table 3.6. TOUT output terminal Timer Timer Timer Timer 2 Timer 3 Output clock name TOUT TOUT TOUT2 TOUT2 TOUT3 TOUT3 Output terminal P2 P2 P2 P23 P2 P23 The TOUT signal rises at the falling edge of the underflow signal and falls at the falling edge of the compare match signal. TOUT is the inverted TOUT signal. Therefore, it is possible to change the frequency and duty ratio of the TOUT signal by setting the reload data register (D) and compare data register (CD). However, it needs a condition setting: D > CD, CD. In the case of D CD, TOUT signal is fixed at "". The TOUT output can be controlled ON and OFF using the clock output control register PTOUTx of each timer and the TOUT output can be controlled using the inverted clock output control register PTOUTx of Timer 2 or Timer 3. When PTOUTx (PTOUTx) is set to "", the TOUTx (TOUTx) signal is output from the corresponding port terminal, when "" is set, the port is set for DC output. When PTOUTx (PTOUTx) is "", settings of the I/O control register IOC2/IOC2/IOC23 and data register P2D/P2D/P23D become invalid. Note: If PTOUT and PTOUT are set to "" at the same time, PTOUT is effective. Similarly, if PTOUT2 (PTOUT2) and PTOUT3 (PTOUT3) are set to "", PTOUT3 (PTOUT3) is effective. In the 6-bit mode, the output is controlled by the control register PTOUT(H) for Timer(H). The clock is output from Timer(H). Since the TOUTx (TOUTx) signal is generated asynchronously from the register PTOUTx (PTOUTx), when the signal is turned ON or OFF by the register settings, a hazard of a /2 cycle or less is generated. Figure 3.6. shows the output waveform of TOUT signal. Input clock Dx register CDx register Down counter Compare match signal Underflow signal TOUTx signal CD register value D register value + PTOUTx/PTOUTx Output from TOUTx (P2/P2) terminal Output from TOUTx (P23) terminal Fig Output waveform of TOUT signal SC88655 TECHNICAL MANUAL EPSON 3

112 3 POGAMMABLE TIME 3.7 Setting Transfer ate of Serial Interface The underflow signals of Timer and Timer 7 can be used as the source clock for serial interface Ch. and Ch., respectively. The transfer rate is set using the registers PSTx and Dx for Ch. or PST7x and D7x for Ch.. (since only the underflow signal is used as the serial interface clock source, the CDx or CD7x register value does not affect the transfer rates. It can be set to any value). Transfer rate (bps) 9,2 9,6 4,8 2,4, Since the underflow signal of Timer is divided by 32 in the serial interface, the value set in the register Dx or D7x which corresponds to the transfer rate is shown in the following expression: fdiv D = - 32 bps D:Dx or D7x set value fdiv: Input clock frequency (setting of PSTx or PST7x) bps: Transfer rate Table 3.7. Example of transfer rate setting OSC3 oscillation frequency / Programmable timer settings fosc3 = MHz fosc3 = 3.72 MHz fosc3 = MHz fosc3 = 4.38 MHz PSTx Dx PSTx Dx PSTx Dx PSTx Dx PST7x D7x PST7x D7x PST7x D7x PST7x D7x H 3H H 4H H 5H H 6H H 7H H 9H H BH H DH H FH H 3H H 7H H BH H FH H 27H H 2FH H 37H H 3FH H 4FH H 5FH H 6FH H 7FH H 9FH H BFH H DFH 2H FH 3H 9H H BFH H DFH 2H 3FH 3H 3H 2H 5FH 2H 6FH Since the underflow signal only is used as the clock source, the CDx or CD7x register value does not affect the transfer rates. 3.8 Setting Clock for LCD Driver Display Timing Generator The underflow signal of Timer 5 can be used as the source clock for the display timing generator in the LCD driver. This makes it possible to set the frame frequency minutely. The frequency is set up using the registers PST5x and x (since only the underflow signal is used as the source clock, the Cx register value does not affect the frame signal. It can be set to any value). The Timer 5 underflow signal is divided by 2 before supplying to the display timing generator, so set a value represented by the following expressions to the register x. fdiv x = - 2 fcl or fdiv x = ff fdiv: Input clock frequency (setting of PST5x) fcl: Display timing generator source clock frequency (Hz) ff: Frame frequency (Hz) 4 EPSON SC88655 TECHNICAL MANUAL

113 3.9 Details of Control egister FF2 D7 PPT Programmable timer clock control PST2 Programmable timer division ratio PST2 PST PST (OSC3) (OSC) fosc3 / 496 fosc / 28 PST fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 D4 PST fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / D3 PPT Programmable timer clock control PST2 Programmable timer division ratio PST2 PST PST (OSC3) (OSC) fosc3 / 496 fosc / 28 D PST fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 D PST fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / FF2 D7 PPT3 Programmable timer 3 clock control PST32 PST3 D4 PST3 Programmable timer 3 division ratio PST32 PST3 PST3 (OSC3) (OSC) fosc3 / 496 fosc / 28 fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / D3 PPT2 Programmable timer 2 clock control PST22 Programmable timer 2 division ratio PST22 PST2 PST2 (OSC3) (OSC) fosc3 / 496 fosc / 28 D PST2 fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 D PST2 fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / On On On On Off Off Off Off 3 POGAMMABLE TIME Table 3.9. shows the programmable timer control bits. Table 3.9.(a) Programmable timer control bits Address Bit Name Function S Comment FF23 D7 D4 D3 PTF3 PTF2 D PTF D PTF register Programmable timer 3 source clock selection Programmable timer 2 source clock selection Programmable timer source clock selection Programmable timer source clock selection fosc fosc fosc fosc fosc3 fosc3 fosc3 fosc3 Constantly "" when being read eserved register SC88655 TECHNICAL MANUAL EPSON 5

114 3 POGAMMABLE TIME Table 3.9.(b) Programmable timer control bits Address Bit Name Function S Comment FF24 D7 PPT5 Programmable timer 5 clock control PST52 Programmable timer 5 division ratio PST52 PST5 PST5 (OSC3) (OSC) fosc3 / 496 fosc / 28 PST5 fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 D4 PST5 fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / D3 PPT4 Programmable timer 4 clock control PST42 Programmable timer 4 division ratio PST42 PST4 PST4 (OSC3) (OSC) fosc3 / 496 fosc / 28 D PST4 fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 D PST4 fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / FF25 D7 PPT7 Programmable timer 7 clock control PST72 PST7 D4 PST7 Programmable timer 7 division ratio PST72 PST7 PST7 (OSC3) (OSC) fosc3 / 496 fosc / 28 fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / D3 PPT6 Programmable timer 6 clock control PST62 Programmable timer 6 division ratio PST62 PST6 PST6 (OSC3) (OSC) fosc3 / 496 fosc / 28 D PST6 fosc3 / 24 fosc / 64 fosc3 / 256 fosc / 32 fosc3 / 64 fosc / 6 fosc3 / 32 fosc / 8 D PST6 fosc3 / 8 fosc / 4 fosc3 / 2 fosc / 2 fosc3 / fosc / FF27 D7 D4 D3 PTF7 Programmable timer 7 source clock selection PTF6 Programmable timer 6 source clock selection D PTF5 Programmable timer 5 source clock selection D PTF4 Programmable timer 4 source clock selection FF3 D7 MODE6_A PTM 8/6-bit mode selection PTNEN_A External clock noise rejector selection D4 register D3 PTOUT PTM clock output control PTUN PTM un/stop control D PSET PTM preset D CKSEL PTM input clock selection On On On On fosc fosc fosc fosc Off Off Off Off fosc3 fosc3 fosc3 fosc3 6-bit x 8-bit x 2 Enable Disable On Off un Stop Preset No operation External clock Internal clock Constantly "" when being read "" when being read eserved register W "" when being read 6 EPSON SC88655 TECHNICAL MANUAL

115 3 POGAMMABLE TIME Table 3.9.(c) Programmable timer control bits Address Bit Name Function S Comment FF3 D7 D4 register D3 PTOUT PTM clock output control PTUN PTM un/stop control On un Off Stop D PSET PTM preset Preset No operation D CKSEL PTM input clock selection External clock Internal clock FF32 D7 D7 PTM reload data D7 (MSB) PTM reload data PTM reload data D4 D4 PTM reload data D4 D3 D3 PTM reload data D3 High Low PTM reload data D D PTM reload data D D D PTM reload data D (LSB) FF33 D7 D7 PTM reload data D7 (MSB) PTM reload data PTM reload data D4 D4 PTM reload data D4 D3 D3 PTM reload data D3 High Low D D D D PTM reload data PTM reload data D PTM reload data D (LSB) FF34 D7 CD7 PTM compare data D7 (MSB) C PTM compare data C PTM compare data D4 CD4 PTM compare data D4 D3 CD3 PTM compare data D3 High Low C PTM compare data D CD PTM compare data D D CD PTM compare data D (LSB) FF35 D7 CD7 PTM compare data D7 (MSB) C PTM compare data C PTM compare data D4 CD4 PTM compare data D4 D3 CD3 PTM compare data D3 High Low C PTM compare data D CD PTM compare data D D CD PTM compare data D (LSB) FF36 D7 PTM7 PTM data D7 (MSB) PTM6 PTM data PTM5 PTM data D4 PTM4 PTM data D4 D3 PTM3 PTM data D3 High Low PTM2 PTM data D PTM PTM data D D PTM PTM data D (LSB) W Constantly "" when being read eserved register "" when being read SC88655 TECHNICAL MANUAL EPSON 7

116 3 POGAMMABLE TIME Table 3.9.(d) Programmable timer control bits Address Bit Name Function S Comment FF37 D7 PTM7 PTM6 PTM5 PTM data D7 (MSB) PTM data PTM data D4 PTM4 PTM data D4 D3 PTM3 PTM data D3 High Low D D PTM2 PTM PTM PTM data PTM data D PTM data D (LSB) FF38 D7 MODE6_B PTM23 8/6-bit mode selection PTNEN_B External clock noise rejector selection 6-bit x Enable 8-bit x 2 Disable "" when being read D4 D3 PTOUT2 PTM2 inverted clock output control PTOUT2 PTM2 clock output control PTUN2 PTM2 un/stop control On On un Off Off Stop D PSET2 PTM2 preset Preset No operation W "" when being read D CKSEL2 PTM2 input clock selection External clock Internal clock FF39 D7 D4 D3 PTOUT3 PTM3 inverted clock output control PTOUT3 PTM3 clock output control PTUN3 PTM3 un/stop control On On un Off Off Stop D PSET3 PTM3 preset Preset No operation D CKSEL3 PTM3 input clock selection External clock Internal clock FF3A D7 7 PTM2 reload data D7 (MSB) 6 PTM2 reload data 5 PTM2 reload data D4 4 PTM2 reload data D4 D3 3 PTM2 reload data D3 High Low 2 PTM2 reload data D PTM2 reload data D D PTM2 reload data D (LSB) FF3B D7 D37 D36 D35 PTM3 reload data D7 (MSB) PTM3 reload data PTM3 reload data D4 D34 PTM3 reload data D4 D3 D33 PTM3 reload data D3 High Low D D D32 D3 D3 PTM3 reload data PTM3 reload data D PTM3 reload data D (LSB) FF3C D7 C7 PTM2 compare data D7 (MSB) C6 PTM2 compare data C5 PTM2 compare data D4 C4 PTM2 compare data D4 D3 C3 PTM2 compare data D3 High Low C2 PTM2 compare data D C PTM2 compare data D D C PTM2 compare data D (LSB) W Constantly "" when being read "" when being read 8 EPSON SC88655 TECHNICAL MANUAL

117 3 POGAMMABLE TIME Table 3.9.(e) Programmable timer control bits Address Bit Name Function S Comment FF3D D7 CD37 CD36 CD35 PTM3 compare data D7 (MSB) PTM3 compare data PTM3 compare data D4 CD34 PTM3 compare data D4 D3 CD33 PTM3 compare data D3 High Low D D CD32 CD3 CD3 PTM3 compare data PTM3 compare data D PTM3 compare data D (LSB) FF3E D7 PTM27 PTM26 PTM25 PTM2 data D7 (MSB) PTM2 data PTM2 data D4 PTM24 PTM2 data D4 D3 PTM23 PTM2 data D3 High Low D D PTM22 PTM2 PTM2 PTM2 data PTM2 data D PTM2 data D (LSB) FF3F D7 PTM37 PTM36 PTM35 PTM3 data D7 (MSB) PTM3 data PTM3 data D4 PTM34 PTM3 data D4 D3 PTM33 PTM3 data D3 High Low D D PTM32 PTM3 PTM3 PTM3 data PTM3 data D PTM3 data D (LSB) FF8 D7 MODE6_C PTM45 8/6-bit mode selection PTNEN_C External clock 2 noise rejector selection 6-bit x Enable 8-bit x 2 Disable D4 D3 register register "" when being read eserved register PTUN4 PTM4 un/stop control un Stop D PSET4 PTM4 preset Preset No operation W "" when being read D CKSEL4 PTM4 input clock selection External clock Internal clock FF8 D7 D4 D3 register register PTUN5 PTM5 un/stop control un Stop D PSET5 PTM5 preset Preset No operation D CKSEL5 PTM5 input clock selection External clock Internal clock FF82 D7 D47 PTM4 reload data D7 (MSB) D46 PTM4 reload data D45 PTM4 reload data D4 D44 PTM4 reload data D4 D3 D43 PTM4 reload data D3 High Low D42 PTM4 reload data D D4 PTM4 reload data D D D4 PTM4 reload data D (LSB) W Constantly "" when being read eserved register "" when being read SC88655 TECHNICAL MANUAL EPSON 9

118 3 POGAMMABLE TIME Table 3.9.(f) Programmable timer control bits Address Bit Name Function S Comment FF83 D PTM5 reload data D7 (MSB) PTM5 reload data PTM5 reload data D4 4 PTM5 reload data D4 D3 3 PTM5 reload data D3 High Low D D 2 PTM5 reload data PTM5 reload data D PTM5 reload data D (LSB) FF84 D7 CD47 CD46 CD45 PTM4 compare data D7 (MSB) PTM4 compare data PTM4 compare data D4 CD44 PTM4 compare data D4 D3 CD43 PTM4 compare data D3 High Low D D CD42 CD4 CD4 PTM4 compare data PTM4 compare data D PTM4 compare data D (LSB) FF85 D7 C7 C6 C5 PTM5 compare data D7 (MSB) PTM5 compare data PTM5 compare data D4 C4 PTM5 compare data D4 D3 C3 PTM5 compare data D3 High Low D D C2 C C PTM5 compare data PTM5 compare data D PTM5 compare data D (LSB) FF86 D7 PTM47 PTM46 PTM45 PTM4 data D7 (MSB) PTM4 data PTM4 data D4 PTM44 PTM4 data D4 D3 PTM43 PTM4 data D3 High Low D D PTM42 PTM4 PTM4 PTM4 data PTM4 data D PTM4 data D (LSB) FF87 D7 PTM57 PTM56 PTM55 PTM5 data D7 (MSB) PTM5 data PTM5 data D4 PTM54 PTM5 data D4 D3 PTM53 PTM5 data D3 High Low D D PTM52 PTM5 PTM5 PTM5 data PTM5 data D PTM5 data D (LSB) FF88 D7 MODE6_D PTM67 8/6-bit mode selection PTNEN_D External clock 3 noise rejector selection 6-bit x Enable 8-bit x 2 Disable D4 D3 register register PTUN6 PTM6 un/stop control un Stop D PSET6 PTM6 preset Preset No operation D CKSEL6 PTM6 input clock selection External clock Internal clock W "" when being read eserved register "" when being read EPSON SC88655 TECHNICAL MANUAL

119 3 POGAMMABLE TIME Table 3.9.(g) Programmable timer control bits Address Bit Name Function S Comment FF89 D7 D4 D3 register register PTUN7 PTM7 un/stop control un Stop D PSET7 PTM7 preset Preset No operation D CKSEL7 PTM7 input clock selection External clock Internal clock FF8A D7 7 PTM6 reload data D7 (MSB) 6 PTM6 reload data 5 PTM6 reload data D4 4 PTM6 reload data D4 D3 3 PTM6 reload data D3 High Low 2 PTM6 reload data D PTM6 reload data D D PTM6 reload data D (LSB) FF8B D7 D77 D76 D75 PTM7 reload data D7 (MSB) PTM7 reload data PTM7 reload data D4 D74 PTM7 reload data D4 D3 D73 PTM7 reload data D3 High Low D D D72 D7 D7 PTM7 reload data PTM7 reload data D PTM7 reload data D (LSB) FF8C D7 C7 PTM6 compare data D7 (MSB) C6 PTM6 compare data C5 PTM6 compare data D4 C4 PTM6 compare data D4 D3 C3 PTM6 compare data D3 High Low C2 PTM6 compare data D C PTM6 compare data D D C PTM6 compare data D (LSB) FF8D D7 CD77 PTM7 compare data D7 (MSB) CD76 PTM7 compare data CD75 PTM7 compare data D4 CD74 PTM7 compare data D4 D3 CD73 PTM7 compare data D3 High Low CD72 PTM7 compare data D CD7 PTM7 compare data D D CD7 PTM7 compare data D (LSB) FF8E D7 PTM67 PTM6 data D7 (MSB) PTM66 PTM6 data PTM65 PTM6 data D4 PTM64 PTM6 data D4 D3 PTM63 PTM6 data D3 High Low PTM62 PTM6 data D PTM6 PTM6 data D D PTM6 PTM6 data D (LSB) W Constantly "" when being read eserved register "" when being read SC88655 TECHNICAL MANUAL EPSON

120 3 POGAMMABLE TIME Table 3.9.(h) Programmable timer control bits Address Bit Name Function S Comment FF8F D7 PTM77 PTM76 PTM75 PTM7 data D7 (MSB) PTM7 data PTM7 data D4 PTM74 PTM7 data D4 D3 PTM73 PTM7 data D3 High Low D D PTM72 PTM7 PTM7 PTM7 data PTM7 data D PTM7 data D (LSB) MODE6_A: FF3H D7 MODE6_B: FF38H D7 MODE6_C: FF8H D7 MODE6_D: FF88H D7 Selects either the 8/6 bit mode. When "" is written: 6 bits channel When "" is written: 8 bits 2 channels eading: Valid MODE6_A, MODE6_B, MODE6_C and MODE6_D are the 8/6-bit mode selection registers corresponding to Timers and, Timers 2 and 3, Timers 4 and 5, and Timers 6 and 7, respectively. Select whether Timer(L) and Timer(H) are used as 2 channels independent 8-bit timers or as channel combined 6-bit timer. When "" is written to the MODE6_A (D) register, 8-bit 2 channels is selected and when "" is written, 6-bit channel is selected. At initial reset, this register is set to "" (8-bit 2 channels). PTNEN_A: FF3H PTNEN_B: FF38H PTNEN_C: FF8H PTNEN_D: FF88H Enables/disables the noise rejector in the external clock input circuit. When "" is written: Enabled When "" is written: Disabled eading: Valid Writing "" to PTNEN_A (D) enables the noise rejector for the external clock EXCL (3). The noise rejector regards pulses less than a 6/fOSC seconds in width as noise and rejects them. When PTNEN_A (D) is "", the external clock bypasses the noise rejector. At initial reset, this register is set to "" (disabled). CKSEL: FF3H D CKSEL: FF3H D CKSEL2: FF38H D CKSEL3: FF39H D CKSEL4: FF8H D CKSEL5: FF8H D CKSEL6: FF88H D CKSEL7: FF89H D Selects the input clock for each timer. When "" is written: External clock When "" is written: Internal clock eading: Valid The clock to be input to each timer is selected from either the external clock (input signal of input port) or the internal clock (prescaler output clock). When "" is written to the CKSELx register, the internal clock (prescaler output INCLx) is selected as the input clock for Timer x. When "" is written, the external clock (EXCL (P24 input) for Timers and, EXCL (P25 input) for Timers 2 and 3, EXCL2 (P26 input) for Timers 4 and 5, EXCL3 (P27 input) for Timers 6 and 7) is selected and the timer functions as an event counter. In the 6-bit mode, the setting of the CKSEL(H) register is invalid. At initial reset, this register is set to "" (internal clock). 2 EPSON SC88655 TECHNICAL MANUAL

121 3 POGAMMABLE TIME PTF: FF23H D PTF: FF23H D PTF2: FF23H PTF3: FF23H D3 PTF4: FF27H D PTF5: FF27H D PTF6: FF27H PTF7: FF27H D3 Selects the source clock for each timer (when internal clock is used). When "" is written: fosc When "" is written: fosc3 eading: Valid When "" is written to the PTFx register, the OSC clock is selected as the source clock for Timer x. When "" is written, the OSC3 clock is selected. At initial reset, this register is set to "" (fosc3). PSTPST2: FF2H D PSTPST2: FF2H D4 PST2PST22: FF2H D PST3PST32: FF2H D4 PST4PST42: FF24H D PST5PST52: FF24H D4 PST6PST62: FF25H D PST7PST72: FF25H D4 Selects the input clock for each timer (when internal clock is used). It can be selected from 8 types of division ratio shown in Tables 3.9.(a) and (b). This register can also be read. At initial reset, this register is set to "". PPT: FF2H D3 PPT: FF2H D7 PPT2: FF2H D3 PPT3: FF2H D7 PPT4: FF24H D3 PPT5: FF24H D7 PPT6: FF25H D3 PPT7: FF25H D7 Controls the clock supply of each timer (when internal clock is used). When "" is written: ON When "" is written: OFF eading: Valid By writing "" to the PPTx register, the clock that is selected with the PSTx register is output to Timer x. When "" is written, the clock is not output. At initial reset, the this register is set to "" (OFF). DD7: FF32H DD7: FF33H 7: FF3AH D3D37: FF3BH D4D47: FF82H 7: FF83H 7: FF8AH D7D77: FF8BH Sets the initial value for the counter of each timer. Each counter loads the reload data set in this register and counts using it as the initial value. The reload data set in this register is loaded into the counter when "" is written to PSETx, or when a counter underflow occurs. This register can also be read. At initial reset, this register is set to "FFH". CDCD7: FF34H CDCD7: FF35H CC7: FF3CH CD3CD37: FF3DH CD4CD47: FF84H CC7: FF85H CC7: FF8CH CD7CD77: FF8DH Sets the compare data for each timer. The timer compares the data set in this register with the corresponding counter data, and outputs the compare match signals when they are the same. The compare match signal controls the interrupt and the TOUT output waveform. This register can also be read. At initial reset, this register is set to "H". PTMPTM7: FF36H PTMPTM7: FF37H PTM2PTM27: FF3EH PTM3PTM37: FF3FH PTM4PTM47: FF86H PTM5PTM57: FF87H PTM6PTM67: FF8EH PTM7PTM77: FF8FH The counter data of each timer can be read. Data can be read at any given time. However, in the 6-bit mode, reading PTM(L) does not latch the Timer(H) counter data in PTM(H). To avoid generating a borrow from Timer(L) to Timer(H), read the counter data after stopping the timer by writing "" to PTUN(L). PTMx can only be read, so writing operation is invalid. At initial reset, PTMx is set to "FFH". SC88655 TECHNICAL MANUAL EPSON 3

122 3 POGAMMABLE TIME PSET: FF3H D PSET: FF3H D PSET2: FF38H D PSET3: FF39H D PSET4: FF8H D PSET5: FF8H D PSET6: FF88H D PSET7: FF89H D Presets the reload data to the counter. When "" is written: Preset When "" is written: Invalid eading: Always "" Writing "" to PSETx presets the reload data in the Dx register to the counter of Timer x. When the counter of Timer x is in UN status, the counter restarts immediately after presetting. In the case of STOP status, the counter maintains the preset data. No operation results when "" is written. In the 6-bit mode, writing "" to PSET(H) is invalid because 6-bit data is preset by PSET(L) only. PSETx is only for writing, and it is always "" during reading. PTUN: FF3H PTUN: FF3H PTUN2: FF38H PTUN3: FF39H PTUN4: FF8H PTUN5: FF8H PTUN6: FF88H PTUN7: FF89H Controls the UN/STOP of the counter. When "" is written: UN When "" is written: STOP eading: Valid The counter of Timer x starts down-counting by writing "" to the PTUNx register and stops by writing "". In STOP status, the counter data is maintained until it is preset or the counter restarts. When STOP status changes to UN status, the counter resumes counting from the data maintained. In the 6-bit mode, the timers are controlled with the PTUN(L) register, and the PTUN(H) register is fixed at "". At initial reset, this register is set to "" (STOP). PTOUT: FF3H D3 PTOUT: FF3H D3 PTOUT2: FF38H D3 PTOUT3: FF39H D3 Controls the output of the TOUT signal. When "" is written: TOUT signal output When "" is written: DC output eading: Valid The PTOUTx is the output control register for the TOUTx signal (Timer x output clock). When PTOUT or PTOUT is set to "", the TOUT or TOUT signal is output from the P2 port terminal. When PTOUT2 or PTOUT3 is set to "", the TOUT2 or TOUT3 signal is output from the P2 port terminal. When "" is set, P2/P2 is set for DC output. At this time, settings of the I/O control register IOC2/IOC2 and data register P2D/P2D become invalid. In the 6-bit mode, the timers are controlled with the PTOUT(H) register, and the PTOUT(L) register is fixed at "". At initial reset, this register is set to "" (DC output). Note: If PTOUT and PTOUT are set to "" at the same time, PTOUT is effective. Similarly, if PTOUT2 and PTOUT3 are set to "", PTOUT3 is effective. Furthermore, if the programmable timer is set in 6-bit mode, the TOUT and TOUT2 signals cannot be output. PTOUT2: FF38H D4 PTOUT3: FF39H D4 Controls the output of the TOUT signal. When "" is written: TOUT signal output When "" is written: DC output eading: Valid The PTOUTx is the output control register for the TOUTx signal (Timer x inverted output clock). When PTOUT2 or PTOUT3 is set to "", the TOUT2 or TOUT3 signal is output from the P23 port terminal. When "" is set, P23 is set for DC output. At this time, settings of the I/O control register IOC23 and data register P23D become invalid. In the 6-bit mode, the timers are controlled with the PTOUT3 register, and the PTOUT2 register is fixed at "". At initial reset, this register is set to "" (DC output). Note: If PTOUT2 and PTOUT3 are set to "" at the same time, PTOUT3 is effective. 4 EPSON SC88655 TECHNICAL MANUAL

123 3 POGAMMABLE TIME 3. Precautions () The programmable timer actually enters into UN or STOP status at the falling edge of the input clock after writing to the PTUNx register. Consequently, when "" is written to PTUNx, the timer stops after counting once more (+). PTUNx is read as "" until the timer actually stops. Figure 3.. shows the timing chart at the UN/STOP control. Input clock PTUNx(D) PTUNx(W) PTMx 42H 4H 4H 3FH 3EH 3DH Fig. 3.. Timing chart at UN/STOP control (2) When the SLP instruction is executed while the programmable timer is running (PTUNx = ""), the timer stops counting during SLEEP status. When SLEEP status is canceled, the timer starts counting. However, the operation becomes unstable immediately after SLEEP status is canceled. Therefore, when shifting to SLEEP status, stop the 6-bit programmable timer (PTUNx = "") prior to executing the SLP instruction. Same as above, the TOUT signal output should be disabled (PTOUTx = "") so that an unstable clock is not output to the clock output port terminal. (3) In the 6-bit mode, reading PTM(L) does not latch the Timer(H) counter data in PTM(H). To avoid generating a borrow from Timer(L) to Timer(H), read the counter data after stopping the timer by writing "" to PTUN(L). (4) For the reason below, pay attention to the reload data write timing when changing the interval of the programmable timer interrupts while the programmable timer is running. The programmable timer counts down at the falling edge of the input clock and at the same time it generates an interrupt if the counter underflows. Then it starts loading the reload data to the counter and the counter data is determined at the next rising edge of the input clock (period shown in as ➀ in the figure). (eload data = 25H) Input clock Counter data 3H 2H H H 25H 24H (continuous mode) Underflow (interrupt is generated) Counter data is determined by reloading Fig eload timing for programmable timer To avoid improper reloading, do not rewrite the reload data after an interrupt occurs until the counter data is determined including the reloading period ➀. Be especially careful when using the OSC (low-speed clock) as the clock source of the programmable timer and the CPU is operating with the OSC3 (high-speed clock). ➀ SC88655 TECHNICAL MANUAL EPSON 5

124 4 WATCHDOG TIME 4 WATCHDOG TIME 4. Configuration of Watchdog Timer The SC88655 has a built-in watchdog timer that uses the OSC oscillation circuit as its clock source. The watchdog timer provides a mask option to select an overflow cycle or to disable the watchdog timer. The overflow signal can generate a nonmaskable interrupt (NMI) or CPU reset, this is also selectable by mask option Figure 4.. shows the block diagram of the watchdog timer. When the watchdog timer is used, it must be reset periodically with software. If the watchdog timer is not reset within the selected overflow period, it generates a non-maskable interrupt or CPU reset to the CPU. Place a watchdog timer reset routine at a path where the CPU executes periodically, such as a main loop or timer interrupt handler routine, to detect program runaway as if the watchdog timer reset routine is not executed. The watchdog timer is active in HALT mode. Therefore, if HALT state continues for longer than the selected period, the CPU starts exception processing. The watchdog timer stops in SLEEP mode. Note: The overflow cycle has an error of less than28/fosc seconds according to the watchdog timer reset timings. 4.2 Mask Option The watchdog timer overflow cycle can be selected by mask option. Watchdog timer overflow cycle Not use 32768/fOSC (-sec cycle when fosc = 32 khz) 65536/fOSC (2-sec cycle when fosc = 32 khz) 372/fOSC (4-sec cycle when fosc = 32 khz) When "Not use" is selected, the watchdog timer does not activate as no clock is supplied. In this case, the OSC oscillation circuit can be stopped by software control (see Chapter 8, "Oscillation Circuits"). When "32768/fOSC", "65536/fOSC", or "372/ fosc" is selected, the watchdog overflow cycle is configured to second, 2 seconds or 4 seconds, respectively. In this case, the OSC oscillation circuit cannot be stopped by software control since the OSC clock is always required. Furthermore, mask option allows selection of either NMI or CPU reset to be generated by the watchdog timer overflow signal. Watchdog timer overflow signal Interrupt (NMI) eset When "Interrupt (NMI)" is selected, the watchdog timer overflow signal will be sent to the NMI (level 4) input of the core CPU. This interrupt cannot be disabled and the NMI exception occurs in priority over other interrupts. See the "SC88 Core CPU Manual" for more information on the NMI exception processing. The NMI exception processing vector address is set at 4H. The CPU reset signal resets only the CPU and does not initialize the peripheral circuit registers (see Chapter 5, "Initial eset"). The reset exception processing vector address is set at H. OSC oscillation circuit WDST fosc /28 Divider Watchdog timer reset signal fosc fosc Not used fosc 372 Watchdog timer Mask option Fig. 4.. Watchdog timer block diagram Overflow signal Mask option NMI CPU reset 6 EPSON SC88655 TECHNICAL MANUAL

125 4 WATCHDOG TIME 4.3 Details of Control egister Table 4.3. shows the control bit for the watchdog timer. Table 4.3. Watchdog timer control bit Address Bit Name Function S Comment FF4 D7 FOUTON FOUT output control On Off FOUT2 FOUT frequency selection FOUT D4 FOUT FOUT2 FOUT FOUT Frequency fosc3 / 8 fosc3 / 4 fosc3 / 2 fosc3 / fosc / 8 fosc / 4 fosc / 2 fosc / D3 D D WDST Watchdog timer reset eset No operation W Constantly "" when being read WDST: FF4H D esets the watchdog timer. When "" is written: Watchdog timer is reset When "" is written: No operation eading: Constantly "" By writing "" to WDST, the watchdog timer is reset, after which it is immediately restarted. Writing "" will mean no operation. Since WDST is for writing only, it is constantly set to "" during readout. 4.4 Precautions () When the watchdog timer is used, the software must reset it within the cycles selected by mask option. (2) Do not execute the SLP instruction for 2 msec after a NMI interrupt has occurred (when fosc is khz). SC88655 TECHNICAL MANUAL EPSON 7

126 5 LCD DIVE 5 LCD DIVE 5. Configuration of LCD Driver The SC88655 has a built-in dot matrix LCD driver that can drive an LCD panel with a maximum of 8,92 dots (28 segments 64 commons). Figure 5.. shows the configuration of the LCD driver and the drive power supply. 5.2 LCD Power Supply The on-chip power supply circuit generates the LCD drive voltages VCVC5. See Chapter 4, "Power Supply" for controlling the power supply circuit. Note that the LCD power supply should be turned ON in the procedure shown below (in the reverse order to turn OFF).. Turn the clock source for the display timing generator ON. (OSC oscillation circuit or programmable timer 5) 2. Turn the display timing generator ON. 3. Turn the supply voltage booster circuit ON. 4. Turn the VC5 voltage generator ON. 5. Turn the VC4 voltage generator ON. 6. Turn the LCD driver circuit ON. OSC oscillation circuit Programmable timer 5 underflow signal fosc Divider Display timing generator LCDCS Power supply circuit Supply voltage booster circuit Voltage booster clock Display data AM Display data AM DSPA VC5 voltage generator VC4 voltage generator VC5 Display clock LCD driver circuit I/O ports LCLK LFM LCDON DSPC DSPEV COMEV SEGEV CL (P26) F (P27) COM63 SEG27 Fig. 5.. Configuration of LCD driver 8 EPSON SC88655 TECHNICAL MANUAL

127 5 LCD DIVE 5.3 Display Timing Generator 5.3. Generating frame signal This LCD driver has a display timing generator included to generate the LCD display clock and the supply voltage booster clock. The configuration of the circuit block is shown in Figure The display timing generator control register LCDCSLCDCS is used to turn the circuit ON/ OFF and to select the source clock. Table Controlling display timing generator LCDCS LCDCS Source clock (flcd) Programmable timer 5 underflow signal fosc/2 fosc/ OFF Setting LCDCSLCDCS to "" stops supplying the clock to the display timing generator, as a result the display timing generator stops outputting the voltage booster and display clocks. When a source clock (flcd) is selected, the display timing generator starts generating the voltage booster and display clocks. The source clock can be selected from the OSC divided clocks (fosc/, fosc/2) or the underflow signal of the programmable timer 5. When the LCDON register is set to "", the LCD driver divides the display clock to generate the CL and F signals. The display clock frequency fcl and the frame frequency ff can be expressed by the following equation, fcl = flcd/8 ff = fcl/64 = flcd/52 where flcd represents the frequency of the selected source clock. The following shows the frame frequency when an OSC divided clock is selected as the source clock (when fosc = khz): 64 Hz when fosc/ is selected 32 Hz when fosc/2 is selected Use of the programmable timer 5 allows fine adjustment of the frame frequency. See Section 3.8, "Setting Clock for LCD Driver Display Timing Generator", for setting the programmable timer. ff represents a frame frequency and the LCD alternating signal (F) cycle is two frames, so the F signal cycle is ff/2. Setup ff to approximately 6 to 8 Hz as a guide. The LCD driver circuit generates /64 duty LCD drive waveforms as shown in Figure based on the timing generated by the display timing generator. Note: The display timing generator also outputs the voltage booster clock to generate the LCD drive voltages. Therefore, be sure to select a source clock before turning the onchip power supply circuit ON. Programmable timer 5 underflow OSC oscillation circuit fosc /2 Divider / /2 LCDCS Selector flcd Timing generator circuit LCD display clock LCD driver CL signal fcl F signal ff/2 LCLK LFM LCDON I/O port P26 I/O port P27 P26 terminal P27 terminal Voltage booster clock CL signal (LCD synchronous signal) F signal (LCD alternating signal) fcl (Display clock frequency) ff/2 (Frame frequency) flcd (Source clock frequency) Fig Display timing generator SC88655 TECHNICAL MANUAL EPSON 9

128 5 LCD DIVE COM SEG CL F COM fcl [Hz] ff [Hz] VDD VSS VDD VSS VC5 VC4 VC3 VC2 VC VSS COM COM2 VC5 VC4 VC3 VC2 VC VSS VC5 VC4 VC3 VC2 VC VSS SEG VC5 VC4 VC3 VC2 VC VSS SEG VC5 VC4 VC3 VC2 VC VSS VC5 VC4 VC3 COMSEG VC2 VC V SS (GND) -VC -VC2 -VC3 -VC4 -VC5 VC5 VC4 VC3 COMSEG VC2 VC V SS (GND) -VC -VC2 Fig LCD drive waveform (/64 duty) -VC3 -VC4 -VC5 2 EPSON SC88655 TECHNICAL MANUAL

129 5 LCD DIVE CL, F signal outputs The CL signal (LCD synchronous clock) and F signal (LCD alternating signal) that are generated by the display timing generator can be output externally from the P26 and P27 port terminals, respectively. This makes it possible to monitor the fcl and ff settings. The LCLK register is used for output control of the CL signal (source clock selected using LCDCS). When LCLK is set to "", the CL signal is output from the P26 terminal. The LFM register is used for output control of the F signal. When LFM is set to "", the F signal is output from the P27 terminal. Figure shows the output waveforms of the CL and F signals. Since these signals are generated asynchronously with the LCLK and LFM registers, hazard may occur on the waveforms when the signal is turned ON/OFF using the register. LCLK/LFM CL output (P26) F output (P27) "" "" Fig CL and F signal output waveforms When LCLK or LFM is set to "", the data register (P26D, P27D) and I/O control register (IOC26, IOC27) of the I/O port P26 or P27 are not effective. When LCLK or LFM is set to "", the P26 or P27 terminal functions as an I/O port. 5.4 Display Data AM The SC88655 has a built-in 2K-byte display data AM (892 bits per screen 2). The display data AM is allocated to address EHEF7FH. Two screen areas are reserved in the display data AM and the area to be displayed can be selected using the display data AM area select register DSPA. When "" is written to DSPA, display area is selected and when "" is written, display area is selected. The memory allocation for the SEG and COM terminals can be reversed using the SEGEV and COMEV registers, respectively. The correspondence between the display data AM bits and the common/segment terminals are shown in Figures 5.4. and When "" is written to the display data AM bit, the corresponding dot on the LCD panel goes ON and when "" is written, it goes OFF. Since display data AM is designed to permit reading/writing, it can be controlled in bit units by logical operation instructions and other means (read, modify and write instructions). Even when external memory has expanded into the display data AM area, this area is not released to external memory. Access to this area is always via display data AM. Note: The LCDON register must be set to "" to generate the CL and F signals. SC88655 TECHNICAL MANUAL EPSON 2

130 5 LCD DIVE Address ExH ExH E2xH E3xH E4xH E5xH E6xH E7xH E8xH E9xH EAxH EBxH ECxH EDxH EExH EFxH ExH ExH E2xH E3xH E4xH E5xH E6xH E7xH E8xH E9xH EAxH EBxH ECxH H H EH FH D7 D4 D3 D D D7 D4 D3 D D D7 D4 D3 D D D7 D4 D3 D D EDxH EExH Display area EFxH E2xH E2xH E22xH E23xH E24xH E25xH E26xH E27xH E28xH E29xH E2AxH E2BxH E2CxH E2DxH E2ExH E2FxH E3xH E3xH E32xH E33xH E34xH E35xH E36xH E37xH E38xH E39xH E3AxH E3BxH E3CxH E3DxH E3ExH E3FxH SEG(normal) SEG(reverse) : SEGEV = "" 2: SEGEV = "" 3: COMEV = "" 4: COMEV = "" Fig Display data AM map (display area ) COM (normal) COM (reverse) EPSON SC88655 TECHNICAL MANUAL

131 5 LCD DIVE Address E8xH E8xH E82xH E83xH E84xH E85xH E86xH E87xH E88xH E89xH E8AxH E8BxH E8CxH E8DxH E8ExH E8FxH E9xH E9xH E92xH E93xH E94xH E95xH E96xH E97xH E98xH E99xH E9AxH E9BxH E9CxH H H EH FH D7 D4 D3 D D D7 D4 D3 D D D7 D4 D3 D D D7 D4 D3 D D E9DxH E9ExH Display area E9FxH EAxH EAxH EA2xH EA3xH EA4xH EA5xH EA6xH EA7xH EA8xH EA9xH EAAxH EABxH EACxH EADxH EAExH EAFxH EBxH EBxH EB2xH EB3xH EB4xH EB5xH EB6xH EB7xH EB8xH EB9xH EBAxH EBBxH EBCxH EBDxH EBExH EBFxH SEG(normal) SEG(reverse) : SEGEV = "" 2: SEGEV = "" 3: COMEV = "" 4: COMEV = "" Fig Display data AM map (display area ) COM (normal) COM (reverse) SC88655 TECHNICAL MANUAL EPSON 23

132 5 LCD DIVE 5.5 Display Control The display status by the built-in LCD driver and the contrast can be controlled with software. The LCD display status can be selected by the LCD display control registers DSPC and DSPC. elationship between the register values and display statuses is shown in Table Table 5.5. LCD display control DSPC DSPC LCD display All dots ON All dots OFF Normal display Display OFF Display ON/OFF When DSPCDSPC are set to "", the LCD drive waveforms are output from the COM and SEG terminals. When DSPCDSPC are set to "", the COM and SEG terminals output VSS (GND), as a result the display turns OFF. At initial reset, display is turned OFF (DSPC DSPC = ""). All dots ON When DSPCDSPC are set to "", all the dots on the LCD panel are lit with dynamic drive. In this case, all the SEG terminals output an ON waveform (VC5 or VSS). This software control does not affect the contents of the display data AM. everse display The display on the LCD panel in normal display mode (DSPCDSPC = "") can be reversed (black pixels are turned white and vice versa) by setting the reverse display control register DSPEV to "". Normal screen appears when DSPEV = "". This software control does not affect the contents of the display data AM. At initial reset, reverse display is disabled (DSPEV = ""). If reverse display (DSPEV = "") and all dots ON (DSPCDSPC = "") are specified simultaneously, the display is reversed (all dots are lit). If reverse display (DSPEV = "") and all dots OFF (DSPCDSPC = "") are specified simultaneously, the display is not reversed (all dots go out). Contrast adjustment The LCD contrast can be adjusted by controlling the VC5 voltage in the power supply circuit. See Chapter 4, "Power Supply", for controlling VC5 and Chapter 9, "Electrical Characteristics", for adjustable range of the LCD drive voltage. All dots OFF When DSPCDSPC are set to "", all the dots on the LCD panel go out with dynamic drive. In this case, all the SEG terminals output an OFF waveform (VC3 or VC2) and all the COM terminals output an OFF waveform (VC4 and VC). This software control does not affect the contents of the display data AM. 24 EPSON SC88655 TECHNICAL MANUAL

133 5.6 Details of Control egisters 5 LCD DIVE Table 5.6. shows the LCD driver control bits. Table 5.6. LCD driver control bits Address Bit Name Function S Comment FF8 D7 LCLK LFM CL output control F output control D4 SEGEV SEG output assignment control COMEV COM output assignment control D3 DSPA LCD display data AM area selection DSPEV everse display control D DSPC LCD display control DSPC DSPC Display All dots on D DSPC All dots off Normal display Display off FF9 D7 LCDON LCD driver circuit On/Off control LBIAS LCD bias selection D4 VCON VC4 voltage generator On/Off control D3 VC5ON VC5 voltage generator On/Off control LBON Supply voltage booster On/Off control D LCDCS Display timing generator control LCDCS LCDCS Source clock P timer 5 D LCDCS fosc/2 fosc/ Off On Off On Off Normal everse Normal everse Display area Display area Normal everse On /9 bias On On On Off /7 bias Off Off Off "" when being read LCDCS, LCDCS: FF9H D, D Controls the display timing generator. Table Controlling display timing generator LCDCS LCDCS Source clock (flcd) Programmable timer 5 underflow signal fosc/2 fosc/ OFF Setting LCDCSLCDCS to "" stops supplying the clock to the display timing generator, as a result all the LCD output signals go to a VSS level. When a source clock is selected, the display timing generator inputs the clock as the CL signal and starts generating the frame (F) signal. The display timing generator also outputs the voltage booster clock to generate the LCD drive voltages. Therefore, be sure to select a source clock before turning the on-chip power supply circuit ON. At initial reset, LCDCS is set to "" (OFF). LCDON: FF9H Turns the LCD driver circuit ON and OFF. When "" is written: ON When "" is written: OFF eading: Valid When LCDON is set to "", the LCD driver circuit activates and allows display controls. However, the LCD drive voltages must be supplied to the LCD driver circuit before setting LCDON to "" (see Chapter 4, "Power Supply"). When LCDON is set to "", the LCD driver circuit deactivates and display controls will be ineffective. At initial reset, LCDON is set to "" (OFF). SC88655 TECHNICAL MANUAL EPSON 25

134 5 LCD DIVE DSPC, DSPC: FF8H D, D Controls the LCD display. Table LCD display control DSPC DSPC LCD display All dots ON All dots OFF Normal display Display OFF The four settings mentioned above can be made without changing the display memory data. At initial reset, this register is set to "" (display OFF). DSPEV: FF8H everses the display. When "" is written: Normal display When "" is written: everse display eading: Valid When DSPEV is set to "", the display on the LCD panel is reversed (black pixels are turned white and vice versa). Normal screen appears when DSPEV = "". This software control does not affect the contents of the display data AM. This control is effective when normal display or all dots ON (DSPCDSPC = "" or "") is selected. When all dots OFF (DSPCDSPC = "") is selected, display is not reversed (all dots go out). At initial reset, DSPEV is set to "" (normal display). DSPA: FF8H D3 Selects the display area. When "" is written: Display area When "" is written: Display area eading: Valid An area to be displayed is selected from two areas in the display data AM. When DSPA is set to "", display area is selected and when set to "", display area is selected. See Figures 5.4. and for the display areas. At initial reset, DSPA is set to "" (display area ). COMEV: FF8H D4 everses the memory allocation for the COM terminals. When "" is written: Normal (ascending order) When "" is written: eversed (descending order) eading: Valid See Figures 5.4. and for correspondence between the display data AM and COM terminals. At initial reset, COMEV is set to "" (normal). SEGEV: FF8H everses the memory allocation for the SEG terminals. When "" is written: Normal (ascending order) When "" is written: eversed (descending order) eading: Valid See Figures 5.4. and for correspondence between the display data AM and SEG terminals. At initial reset, SEGEV is set to "" (normal). LFM: FF8H Controls the F signal output. When "" is written: F signal output ON When "" is written: F signal output OFF eading: Valid When LFM is set to "", the F signal is output from the P27 terminal. When LFM is set to "", the P27 terminal functions as an I/O port. At initial reset, LFM is set to "" (F signal output OFF). LCLK: FF8H D7 Controls the CL signal output. When "" is written: CL signal output ON When "" is written: CL signal output OFF eading: Valid When LCLK is set to "", the CL signal is output from the P26 terminal. When LCLK is set to "", the P26 terminal functions as an I/O port. At initial reset, LCLK is set to "" (CL signal output OFF). 26 EPSON SC88655 TECHNICAL MANUAL

135 5 LCD DIVE 5.7 Precautions () The display timing generator outputs the voltage booster clock to generate the LCD drive voltages. Therefore, be sure to select a source clock using the LCDCS register before turning the on-chip power supply circuit ON. (2) Since the CL and F signals are generated asynchronously with the LCLK and LFM registers, hazard may occur on the waveforms when the signal is turned ON/OFF using the register. (3) Be sure to set LCDCS, LCDON, VCON, VC5ON and LBON to OFF before executing the SLP instruction. Also note that a hazard may occur if LCDCS is changed when LCLK and LFM is ON. SC88655 TECHNICAL MANUAL EPSON 27

136 6 SVD CICUIT 6 SUPPLY VOLTAGE DETECTION (SVD) CICUIT 6. Configuration of SVD Circuit The SC88655 has a built-in SVD (supply voltage detection) circuit, so that the software can find when the source voltage lowers. Turning the SVD circuit ON/OFF and the SVD criteria voltage setting can be done with software. Figure 6.. shows the configuration of the SVD circuit. VDD SVD circuit Criteria voltage setting circuit Detection output VSS SVDDT SVDON SVDS3 SVDS Fig. 6.. Configuration of SVD circuit Data bus 6.2 SVD Operation The SVD circuit compares the criteria voltage set by software and the supply voltage (VDDVSS) and sets its results into the SVDDT latch. By reading the data of this SVDDT latch, it can be determined by means of software whether the supply voltage is normal or has dropped. The criteria voltage can be set for the 3 types shown in Table 6.2. by the SVDS3SVDS registers. Table 6.2. Criteria voltage setting SVDS3 SVDS2 SVDS SVDS Criteria voltage (V) When the SVDON register is set to "", source voltage detection by the SVD circuit is executed. As soon as the SVDON register is reset to "", the result is loaded to the SVDDT latch and the SVD circuit goes OFF. To obtain a stable detection result, the SVD circuit must be ON for at least 5 µsec. So, to obtain the SVD detection result, follow the programming sequence below.. Set SVDON to "" 2. Maintain for 5 µsec minimum 3. Set SVDON to "" 4. ead SVDDT When the SVD circuit is ON, the IC draws a large current, so keep the SVD circuit off unless it is. 28 EPSON SC88655 TECHNICAL MANUAL

137 6.3 Details of Control egister 6 SVD CICUIT Table 6.3. shows the SVD circuit control bits. Table 6.3. SVD circuit control bits Address Bit Name Function S Comment FFC D7 D4 SVDDT SVDON SVD detection data SVD circuit On/Off Low On Normal Off Constantly "" when being read D3 D D SVDS3 SVDS2 SVDS SVDS SVD criteria voltage setting SVDS3 SVDS2 SVDS SVDS Voltage (V) : : : : :.8 SVDS3SVDS: FFCH D3D Criteria voltage for SVD is set as shown in Table At initial reset, this register is set to "". SVDON: FFCH D4 Controls the SVD circuit ON and OFF. When "" is written: SVD circuit ON When "" is written: SVD circuit OFF eading: Valid When the SVDON register is set to "", a supply voltage detection is executed by the SVD circuit. As soon as SVDON is reset to "", the result is loaded to the SVDDT latch. To obtain a stable detection result, the SVD circuit must be ON for at least 5 µsec. At initial reset, this register is set to "". SVDDT: FFCH This is the result of supply voltage detection. When "" is read: Supply voltage (VDDVSS) Criteria voltage When "" is read: Supply voltage (VDDVSS) < Criteria voltage Writing: Invalid The result of supply voltage detection at time of SVDON is set to "" can be read from this latch. At initial reset, SVDDT is set to "". 6.4 Precautions () To obtain a stable detection result, the SVD circuit must be ON for at least 5 µsec. So, to obtain the SVD detection result, follow the programming sequence below.. Set SVDON to "" 2. Maintain for 5 µsec minimum 3. Set SVDON to "" 4. ead SVDDT (2) The SVD circuit should normally be turned OFF because SVD operation increase current consumption. SC88655 TECHNICAL MANUAL EPSON 29

138 7 SUMMAY OF NOTES 7 SUMMAY OF NOTES 7. Notes for Low Current Consumption The SC88655 can turn circuits, which consume a large amount of power, ON or OFF by control registers. You can reduce power consumption by creating a program that operates the minimum necessary circuits using these control registers. Next, which circuit systems' operation can be controlled and their control registers (instructions) are explained. You should refer to these when programming. See Chapter 9, "Electrical Characteristics", for the current consumption. efer to "Precautions" in each peripheral section for precautions of each peripheral circuit. Circuit type CPU Oscillation circuit Power supply circuit LCD driver circuit SVD circuit Table 7.. Circuit systems and control registers Control register (Instruction) Status at time of initial resetting HALT and SLP instructions CLKCHG SOSC3 SOSC LBON VC5ON VCON LCDON DSPC SVDON Operation status OSC3 clock (CLKCHG = "") OSC3 oscillation ON (SOSC3 = "") OSC oscillation ON (SOSC = "") Supply voltage booster circuit OFF (LBON = "") VC5 voltage generator OFF (VC5ON = "") VC4 voltage generator ON (VCON = "") LCD driver circuit OFF (LCDON = "") Display OFF (DSPC = "") OFF status (SVDON = "") 3 EPSON SC88655 TECHNICAL MANUAL

139 7.2 Precautions on Mounting <Oscillation Circuit> Oscillation characteristics change depending on conditions (board pattern, components used, etc.). In particular, when a ceramic or crystal oscillator is used, use the oscillator manufacturer's recommended values for constants such as capacitance and resistance. Disturbances of the oscillation clock due to noise may cause a malfunction. Consider the following points to prevent this: () Components which are connected to the OSC, OSC2, OSC3 and OSC4 terminals, such as oscillators, resistors and capacitors, should be connected in the shortest line. (2) As shown in the right hand figure, make a VSS pattern as large as possible at circumscription of the OSC, OSC2, OSC3 and OSC4 terminals and the components connected to these terminals. Furthermore, do not use this VSS pattern for any purpose other than the oscillation system. Sample VSS pattern (OSC3) OSC4 OSC3 VSS In order to prevent unstable operation of the oscillation circuit due to current leak between OSC/OSC3 and VDD, please keep enough distance between OSC/OSC3 and VDD or other signals on the board pattern. <eset Circuit> The power-on reset signal which is input to the ESET terminal changes depending on conditions (power rise time, components used, board pattern, etc.). Decide the time constant of the capacitor and resistor after enough tests have been completed with the application product. When the built-in pull-up resistor of the ESET terminal is used, take into consideration dispersion of the resistance for setting the constant. In order to prevent any occurrences of unnecessary resetting caused by noise during operating, components such as capacitors and resistors should be connected to the ESET terminal in the shortest line. 7 SUMMAY OF NOTES <Power Supply Circuit> Sudden power supply variation due to noise may cause malfunction. Consider the following points to prevent this: () The power supply should be connected to the VDD and VSS terminal with patterns as short and large as possible. (2) When connecting between the VDD and VSS terminals with a bypass capacitor, the terminals should be connected as short as possible. Bypass capacitor connection example SC88655 TECHNICAL MANUAL EPSON 3 VDD VSS VDD VSS (3) Components which are connected to the VD and V terminals, such as capacitors and resistors, should be connected in the shortest line. <Arrangement of Signal Lines> In order to prevent generation of electromagnetic induction noise caused by mutual inductance, do not arrange a large current signal line near the circuits that are sensitive to noise such as the oscillation unit. When a signal line is parallel with a high-speed line in long distance or intersects a high-speed line, noise may generated by mutual interference between the signals and it may cause a malfunction. Do not arrange a high-speed signal line especially near circuits that are sensitive to noise such as the oscillation unit. Prohibited pattern Large current signal line High-speed signal line OSC4 OSC3 VSS

140 7 SUMMAY OF NOTES <Precautions for Visible adiation (when bare chip is mounted)> Visible radiation causes semiconductor devices to change the electrical characteristics. It may cause this IC to malfunction. When developing products which use this IC, consider the following precautions to prevent malfunctions caused by visible radiations. () Design the product and implement the IC on the board so that it is shielded from visible radiation in actual use. (2) The inspection process of the product needs an environment that shields the IC from visible radiation. (3) As well as the face of the IC, shield the back and side too. 32 EPSON SC88655 TECHNICAL MANUAL

141 8 BASIC EXTENAL WIING DIAGAM 8 BASIC EXTENAL WIING DIAGAM LCD panel 28 x 64 C3 C V 3.6 V CG X'tal CG3 X'tal3 or Ceramic 5 CD3 Open C C2 C3 C4 C5 C6 ( Cres ) - + CP 3 VSS OSC OSC2 OSC3 OSC4 VD V CA3P CAM CAP CA4P CA2M CA2P VC VC2 VC3 VC4 VC5 ESET VDD SEG SC88655 [The potential of the substrate (back of the chip) is VSS.] 7 (AA7) 7 (A8A5) 223 (A6A9) 24 (D) 25 (W) 333 (CECE3) PP7 (DD7) P (SIN) P (SOUT) P2 (SCLK) P3 (SDY) P4 (SIN) P5 (SOUT) P6 (SCLK) P7 (SDY) P2 (TOUT/TOUT) P2 (TOUT2/TOUT3) P22 (FOUT) P23 (TOUT2/TOUT3) P24 (BEQ/EXCL) P25 (BACK/EXCL) P26 (CL/EXCL2) P27 (F/EXCL3) TEST : OSC = Crystal oscillation 2: OSC = C oscillation 3: OSC3 = Crystal or Ceramic oscillation 4: OSC3 = C oscillation 5: Example for V = 5 VDD (V > VC5) The external circuit configuration depends on the supply voltage and LCD drive voltage values. SEG27 COM COM63 ecommended values for external parts Symbol Name X'tal Crystal oscillator CG Trimmer capacitor C esistor for C oscillation X'tal3 Crystal oscillator Ceramic Ceramic oscillator CG3 Gate capacitor CD3 Drain capacitor ecommended value khz 25 pf.5 MΩ 4 MHz 4 MHz 5 pf (Crystal oscillation) 3 pf (Ceramic oscillation) 5 pf (Crystal oscillation) 3 pf (Ceramic oscillation) Symbol Name C3 esistor for C oscillation C Capacitor between VSS and VD C2 Capacitor between VSS and V C3C6 Booster capacitor CP Capacitor for power supply Cres Capacitor for ESET terminal ecommended value 39 kω. µf.4.7 µf.4.7 µf 3.3 µf.47 µf (Not required when the reset voltage detection circuit is used.) Note: The above table is simply an example, and is not guaranteed to work. SC88655 TECHNICAL MANUAL EPSON 33

142 9 ELECTICAL CHAACTEISTICS 9 ELECTICAL CHAACTEISTICS 9. Absolute Maximum ating (VSS = V) Item Symbol Condition ated value Unit Note Power voltage Liquid crystal power voltage Input voltage Output voltage High level output current Low level output current VDD V, VC5 VI VO IOH IOL terminal Total of all terminals terminal Total of all terminals -.3 to to to VDD to VDD V V V V ma ma ma ma Permitted loss Operating temperature Storage temperature Soldering temperature / time PD Topr Tstg Tsol 2-2 to to C, sec (lead section) mw C C Note) In case of plastic package. 9.2 ecommended Operating Conditions Operating power voltage Operating frequency Capacitor between VD and VSS Capacitor between V and VSS Item Symbol Condition Min. Typ. Max. Unit VDD fosc fosc3 Capacitor between CA3P and CAM C3 Capacitor between CAP and CAM C4 Capacitor between CA4P and CA2M C5 Capacitor between CA2P and CA2M C6 Note) When LCD drive power is not used, the capacitor is not necessary. Configuration of C3C6 is different depending on the boosting ratio. C C2 Crystal/C oscillation C oscillation Crystal/ceramic oscillation V khz MHz MHz µf µf µf µf µf µf Note 34 EPSON SC88655 TECHNICAL MANUAL

143 9 ELECTICAL CHAACTEISTICS 9.3 DC Characteristics Unless otherwise specified: VDD =.8 to 3.6 V, VSS = V, Ta = -2 to 7 C Item Symbol Condition Min. Typ. Max. Unit High level input voltage Low level input voltage High level schmitt input voltage () Low level schmitt input voltage () High level schmitt input voltage (2) Low level schmitt input voltage (2) High level output current Low level output current Input leak current Output leak current Input pull-up resistance Input terminal capacitance VIH VIL VT+ VT- VT2+ VT2- IOH IOL ILI ILO IN CIN Pxx Pxx ESET, MCU/MPU ESET, MCU/MPU Pxx Pxx Pxx, xx, VOH =.9 VDD Pxx, xx, VOL =. VDD Pxx, ESET, MCU/MPU Pxx, xx Pxx, ESET, MCU/MPU Pxx VIN = V, f = MHz, Ta = 25 C.8VDD.5VDD.VDD.5VDD.VDD VDD.2VDD.9VDD.5VDD.9VDD.5VDD V V V V V V ma ma µa µa kω pf Note) When CMOS level is selected by mask option. 2 When CMOS Schmitt level is selected by mask option. 3 When addition of pull-up resistor is selected by mask option. Note VDD VOUT (V) VT- VT+ VDD VIN (V) SC88655 TECHNICAL MANUAL EPSON 35

144 9 ELECTICAL CHAACTEISTICS 9.4 Analog Circuit Characteristics LCD drive circuit Unless otherwise specified: VDD = 2. to 3.6 V, VSS = V, Ta = 25 C, No panel load Item Symbol Condition Min. Typ. Max. Unit Voltage booster circuit operating voltage V voltage range VDD V Double boosted Triple boosted Quadruple boosted Quintuple boosted V V V V V VC5 voltage range (for /9 bias) VC5 Set using LSEL2 and LEV5. Typ Typ..7 V VC4 VC3 VC2 VC.889 VC5.778 VC5.222 VC5. VC5 V V V V VC5 voltage range (for /7 bias) VC5 Set using LSEL2 and LEV5. Typ Typ..7 V VC4 VC3 VC2 VC.857 VC5.74 VC5.286 VC5.43 VC5 V V V V Note) See the plot below for the VC5 voltage adjustable range. Note VC5 [V] Ta = 25 C, VDD =.8 to 3.6V, Double to quintuple boosted Operating voltage range VDD [V] Operating voltage range VC5 [V] 4 LSEL2 = 6 2 LSEL2 = 5 LSEL2 = 4 LSEL2 = 3 LSEL2 = 2 8 LSEL2 = 6 LSEL2 = LEV5: Level 63 VC5 output voltage adjustment range (Typ.) 36 EPSON SC88655 TECHNICAL MANUAL

145 9 ELECTICAL CHAACTEISTICS SVD circuit Unless otherwise specified: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C Item Symbol Condition Min. Typ. Max. Unit SVD voltage VSVD SVDS3 = "" SVDS3 = "" SVDS3 = "2" SVDS3 = "3" SVDS3 = "4" SVDS3 = "5" SVDS3 = "6" SVDS3 = "7" SVDS3 = "8" V V V V V V V V V SVDS3 = "9" SVDS3 = "" SVDS3 = "" SVDS3 = "2" SVDS3 = "3" SVDS3 = "4" SVDS3 = "5" Typ Typ..9 V V V V V V V SVD circuit response time tsvd 5 µs Note VD circuit Unless otherwise specified: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C Item Symbol Condition Min. Typ. Max. Unit eset detection voltage Hysteresis voltage Operation limit voltage VST+ VST VSTOP VDD = L H (eset release level) VDD = H L (eset level) VDD = L H L Typ Typ V V mv V Note VST VST VDD Power supply voltage VSS eset voltage VSTOP VST- VST+ VST+ VST+ VST- VST- 2 VST- VSTOP detector output eset signal negated eset signal negated eset signal negated Unsteady reset range 2 eset hold range (eset status is held for a certain time after the power supply voltage exceeds the reset release level.) 2 2 SC88655 TECHNICAL MANUAL EPSON 37

146 9 ELECTICAL CHAACTEISTICS 9.5 Power Current Consumption Unless otherwise specified: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C, C =. µf, C2C6 = µf, No panel load Item Symbol Condition Min. Typ. Max. Unit Note Current consumption in SLEEP mode Current consumption in HALT mode Current consumption during execution VD circuit current SVD circuit current LCD driver circuit current ISLP IHALT IHALT2 IHALT3 IHALT4 IEXE IEXE2 IEXE3 IEXE4 IVD ISVD ILCD ILC ILCD3 ILCD4 OSC = OFF, OSC3 = OFF OSC = 32 khz Crystal, OSC3 = OFF OSC = 32 khz C, OSC3 = OFF OSC = OFF, OSC3 = 8 MHz Ceramic OSC = OFF, OSC3 = 2 MHz C OSC = 32 khz Crystal, OSC3 = OFF OSC = 32 khz C, OSC3 = OFF OSC = OFF, OSC3 = 8 MHz Ceramic OSC = OFF, OSC3 = 2 MHz C VDD = 3.6 V VDD = 3.6 V VDD = 2. V, Quintuple boosted, VC5 = 8 V, White screen displayed VDD = 2. V, Quintuple boosted, VC5 = 8 V, Checker pattern displayed VDD = 3. V, Triple boosted, VC5 = 8 V, White screen displayed VDD = 3. V, Triple boosted, VC5 = 8 V, Checker pattern displayed µa µa µa µa µa µa µa µa µa µa µa µa µa µa µa Note) 2 3 This value is added to the current consumption in SLEEP mode/in HALT mode/during execution when the reset voltage detector is selected by mask option. This value is added to the current consumption in SLEEP mode/in HALT mode/during execution when the SVD circuit is active. SVDON = "", SVDS3 = "Fh" This value is added to the current consumption in SLEEP mode/in HALT mode/during execution when the LCD driver circuit is active. LCDCS = "", LBON = "", VC5ON = "", LBIAS = "", DSPC = "", LSEL2 and LEV5 = arbitrarily 38 EPSON SC88655 TECHNICAL MANUAL

147 9 ELECTICAL CHAACTEISTICS 9.6 AC Characteristics Operating range Condition: VDD =.8 to 3.6 V, VSS = V, Ta = -2 to 7 C Item Symbol Condition Min. Typ. Max. Unit Operating frequency Instruction execution time (during operation with OSC clock) Instruction execution time (during operation with OSC3 clock) fosc fosc3 tcy tcy VDD =.8 to 3.6 V -cycle instruction 2-cycle instruction 3-cycle instruction 4-cycle instruction 5-cycle instruction 6-cycle instruction -cycle instruction 2-cycle instruction 3-cycle instruction 4-cycle instruction 5-cycle instruction 6-cycle instruction khz MHz µs µs µs µs µs µs µs µs µs µs µs µs Note SC88655 TECHNICAL MANUAL EPSON 39

148 9 ELECTICAL CHAACTEISTICS External memory access ead cycle Condition: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD, VIH2 =.6 V, VIL2 =.6 V, VOH =.8VDD, VOL =.2VDD, CL = pf (load capacitance) Item Symbol Min. Typ. Max. Unit Address set-up time in read cycle Address hold time in read cycle ead signal pulse width Data input set-up time in read cycle Data input hold time in read cycle tras trah trp trds trdh tc+tl-5+n tc/2 th-4 tc-+n tc/2 5 ns ns ns ns ns Note) Substitute the number of states for wait insertion in n. Write cycle Condition: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD, VIH2 =.6 V, VIL2 =.6 V, VOH =.8VDD, VOL =.2VDD, CL = pf (load capacitance) Item Symbol Min. Typ. Max. Unit Address set-up time in write cycle Address hold time in write cycle Write signal pulse width Data output set-up time in write cycle Data output hold time in write cycle twas twah twp twds twdh tc-9 th-4 tl-2+n tc/2 tc-9+n tc/2 th-4 th+4 ns ns ns ns ns Note) Substitute the number of states for wait insertion in n. Note Note tc* ICLK VIH2 VIL2 th* tl* AA9 CE VOH VOL D VOH VOL tras trah DIN trp VIH VIL trds trdh AA9 CE VOH VOL W DOUT twas VIH VIL VOH VOL twp twds twah twdh * In the case of crystal oscillation and ceramic oscillation: th =.5tc ±.5tc, tl = tc - th (/tc: oscillation frequency) * In the case of C oscillation: th =.5tc ±.tc, tl = tc - th (/tc: oscillation frequency) 4 EPSON SC88655 TECHNICAL MANUAL

149 9 ELECTICAL CHAACTEISTICS Serial interface Clock synchronous master mode Condition: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD, VOH =.8VDD, VOL =.2VDD Item Symbol Min. Typ. Max. Unit Transmitting data output delay time eceiving data input set-up time eceiving data input hold time tsmd tsms tsmh 25 ns ns ns Note Clock synchronous slave mode Condition: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD, VOH =.8VDD, VOL =.2VDD Item Symbol Min. Typ. Max. Unit Transmitting data output delay time eceiving data input set-up time eceiving data input hold time tssd tsss tssh 25 ns ns ns Note Asynchronous system Condition: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C Item Symbol Min. Typ. Max. Unit Note Start bit detection error time Erroneous start bit detection range time tsa tsa2 9t/6 t/6 t/6 s s 2 Note) 2 Start bit detection error time is a logical delay time from inputting the start bit until internal sampling begins operating. (Time as far as AC is excluded.) Erroneous start bit detection range time is a logical range to detect whether a LOW level (start bit) has been input again after a start bit has been detected and the internal sampling clock has started. When a HIGH level is detected, the start bit detection circuit is reset and goes into a wait status until the next start bit. (Time as far as AC is excluded.) SCLK OUT VOL VOH SOUT tsmd VOH VOL SIN VIH VIL tsms tsmh SCLK IN VIL VIH SOUT tssd VOH VOL SIN VIH VIL tsss tssh Start bit Stop bit SIN Sampling clock tsa Erroneous start bit detection signal tsa2 t SC88655 TECHNICAL MANUAL EPSON 4

150 9 ELECTICAL CHAACTEISTICS Input clock SCLK, EXCL input clock Condition: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C, VIH =.8VDD, VIL =.2VDD Item Symbol Min. Typ. Max. Unit SCLK input clock time EXCL input clock time (with noise rejector) EXCL input clock time (without noise rejector) Cycle time "H" pulse width "L" pulse width Cycle time "H" pulse width "L" pulse width Cycle time "H" pulse width "L" pulse width tsccy tsch tscl tevcy tevh tevl tevcy tevh tevl 2 64/fOSC 32/fOSC 32/fOSC 2 µs µs µs s s s µs µs µs Input clock rising time Input clock falling time tckr tckf ns ns Note SCLK EXCL tsccy tckf tckr VIH VIL tscl tsch tevcy tckf tckr VIH VIL tevl tevh ESET input clock Condition: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C, VIH =.5VDD, VIL =.VDD Item Symbol Min. Typ. Max. Unit ESET input time tsr µs Note tsr ESET VIL VIH 42 EPSON SC88655 TECHNICAL MANUAL

151 9.7 Oscillation Characteristics 9 ELECTICAL CHAACTEISTICS Oscillation characteristics change depending on conditions (board pattern, components used, etc.). Use the following characteristics as reference values. In particular, when a ceramic oscillator or crystal oscillator is used for OSC3, use the oscillator manufacturer s recommended values for constants such as capacitance and resistance. The oscillation start time is important because it becomes the wait time when OSC3 clock is used. (If OSC3 is used as CPU clock before oscillation stabilizes, the CPU may malfunction.) OSC (Crystal) Unless otherwise specified: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C, Crystal oscillator = C-2X ( = 3 kω (Typ.), CL = 2.5 pf)*, CG = 25 pf, CD = Built-in Item Symbol Condition Min. Typ. Max. Unit Oscillation start time External gate capacitance Built-in drain capacitance Frequency/IC deviation Frequency/power voltage deviation Frequency adjustment range tsta CG CD f/ IC f/ V f/ CG Including board capacitance In case of the chip VDD = constant VDD = constant, CG = to 25 pf s pf pf ppm ppm/v ppm * C-2X Made by EPSON TOYOCOM Note OSC (C) Unless otherwise specified: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C Item Symbol Condition Min. Typ. Max. Unit Oscillation start time Frequency/IC deviation tsta f/ IC C = constant µs % Note OSC3 (Crystal) Unless otherwise specified: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C, Crystal oscillator = CA-3*, F = MΩ, CG3 = CD3 = 5 pf Item Symbol Condition Min. Typ. Max. Unit Note Oscillation start time tsta ms Note) * CA-3 Made by EPSON TOYOCOM The crystal oscillation start time changes by the crystal oscillator to be used, CG3 and CD3. OSC3 (Ceramic) Unless otherwise specified: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C, Ceramic oscillator = KB-4.MSB/KB-8.MSB*, F = MΩ, CG3 = CD3 = 3 pf Item Symbol Condition Min. Typ. Max. Unit Note Oscillation start time tsta ms Note) * KB-4.MSB/KB-8.MSB Made by Kyocera The ceramic oscillation start time changes by the ceramic oscillator to be used, CG3 and CD3. OSC3 (C) Unless otherwise specified: VDD =.8 to 3.6 V, VSS = V, Ta = 25 C Item Symbol Condition Min. Typ. Max. Unit Oscillation start time Frequency/IC deviation tsta f/ IC C = constant µs % Note SC88655 TECHNICAL MANUAL EPSON 43

152 9 ELECTICAL CHAACTEISTICS 9.8 Characteristics Curves (reference value) High level output current characteristic. Ta = 7 C, Max. value VDDVOH [V] IOH [ma] -6-9 VDD =.8 V -2-5 VDD = 3.6 V VDD = 2.4 V Low level output current characteristic 5 VDD = 3.6 V VDD = 2.4 V VDD =.8 V Ta = 7 C, Min. value 2 IOL [ma] VOL [V] VC5 voltage - temperature characteristic.5vc5 Typ. value, VC5 = 8 V VC5 [V].4VC5.3VC5.2VC5.VC5.VC5.99VC5.98VC5.97VC5.96VC5.95VC Ta [ C] 44 EPSON SC88655 TECHNICAL MANUAL

153 9 ELECTICAL CHAACTEISTICS VC5 voltage - load characteristic 8.3 Typ. value, VC5 = 8 V VC5 [V] IVC5 [ma] SVD voltage - temperature characteristic.5vsvd Typ. value, SVDSx = FH VSVD [V].4VSVD.3VSVD.2VSVD.VSVD.VSVD.99VSVD.98VSVD.97VSVD.96VSVD.95VSVD Ta [ C] In HALT status current consumption - temperature characteristic (During operation with OSC) <Crystal oscillation, fosc = khz> Typ. value IHALT [µa] Ta [ C] SC88655 TECHNICAL MANUAL EPSON 45

154 9 ELECTICAL CHAACTEISTICS In HALT status current consumption - resistance characteristic (During operation with OSC) <C oscillation> 35 Ta = 25 C 3 IHALT2 [µa] Max. Typ. C [kω] In HALT status current consumption - resistance characteristic (During operation with OSC3) <C oscillation> 6 Ta = 25 C 5 IHALT3 [µa] Max. Typ. C3 [kω] In HALT status current consumption - frequency characteristic (During operation with OSC3) <Crystal oscillation/ceramic oscillation> Ta = 25 C 25 2 Max. IHALT4 [µa] 5 Typ fosc3 [MHz] 46 EPSON SC88655 TECHNICAL MANUAL

155 9 ELECTICAL CHAACTEISTICS In executed status current consumption - temperature characteristic (During operation with OSC) <Crystal oscillation, fosc = khz> Typ. value 8 IEXE [µa] Ta [ C] In executed status current consumption - resistance characteristic (During operation with OSC) <C oscillation> Ta = 25 C IEXE2 [µa] Max. Typ. C [kω] In executed status current consumption - resistance characteristic (During operation with OSC3) <C oscillation> Ta = 25 C IEXE3 [µa] 3 2 Max. Typ. C3 [kω] SC88655 TECHNICAL MANUAL EPSON 47

156 9 ELECTICAL CHAACTEISTICS In executed status current consumption - frequency characteristic (During operation with OSC3) <Crystal oscillation/ceramic oscillation> Ta = 25 C 4 2 Max. IEXE4 [µa] Typ fosc3 [MHz] LCD driver circuit current - power voltage characteristic Ta = 25 C, Typ. value, VC5 = 8 V, white screen displayed 2 ILCD [µa] Quintuple boosted Quadruple boosted Triple boosted 2 ILC [µa] VDD [V] Ta = 25 C, Typ. value, VC5 = 8 V, checker pattern displayed Quintuple boosted Quadruple boosted Triple boosted VDD [V] 48 EPSON SC88655 TECHNICAL MANUAL

157 9 ELECTICAL CHAACTEISTICS C oscillation frequency characteristic Note: Oscillation frequency changes depending on the conditions (components used, board pattern, etc.). In particular, the OSC3 oscillation frequency changes extensively depending on the product form and board capacitance. Therefore, select the resistance value after evaluating the actual product. (The OSC3 resistance value should be set to C3 5 kω.) OSC oscillation frequency - resistor characteristic Ta = 25 C, Typ. value fosc [khz] C [kω] OSC oscillation frequenc - temperature characteristic Typ. value, C = 5 kω fosc [khz] Ta [ C] SC88655 TECHNICAL MANUAL EPSON 49

158 9 ELECTICAL CHAACTEISTICS OSC3 oscillation frequency - resistor characteristic Ta = 25 C, Typ. value fosc3 [khz] C3 [kω] OSC3 oscillation frequenc - temperature characteristic Typ. value, C3 = 39 kω fosc3 [khz] Ta [ C] 5 EPSON SC88655 TECHNICAL MANUAL

159 2 PACKAGE FO TEST SAMPLES 2 PACKAGE FO TEST SAMPLES SC88655COFQTP (Unit: mm) Inserting QTP into the socket Make sure the orientation of the carrier when inserting it into the socket. Note: The analog characteristic values evaluated using a test sample may differ from those of the actual product due to the parasitic capacitance on the board and other conditions. QTP pin 8 Socket pin SC88655 TECHNICAL MANUAL EPSON 5

160 52 EPSON SC88655 TECHNICAL MANUAL 2 PACKAGE FO TEST SAMPLES SC88655COFQTP pin - pad correspondence table IC Pad Name VDD OSC2 OSC VSS VD OSC4 OSC3 TEST MCU/MPU ESET VSS P27/F/EXCL3 P26/CL/EXCL2 P25/BACK/EXCL P24/BEQ/EXCL P23/TOUT2/TOUT3 P22/FOUT P2/TOUT2/TOUT3 P2/TOUT/TOUT P7/SDY P6/SCLK P5/SOUT P4/SIN P3/SDY P2/SCLK P/SOUT P/SIN VDD P7/D7 P6/ P5/ P4/D4 P3/D3 P2/ P/D P/D /A /A 2/A2 3/A3 4/A4 5/A5 6/A6 7/A7 /A8 /A9 2/A 3/A 4/A2 5/A3 6/A4 7/A5 2/A6 2/A7 22/A8 23/A9 24/D 25/W 3/CE 3/CE 32/CE2 33/CE3 (N.C.) VDD VSS (N.C.) CA3P CAM CAP V CA4P CA2M CA2P V VSS VC VC2 VC3 VC4 VC5 QTP pin No Socket pin No IC Pad QTP pin No Socket pin No IC Pad Name SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG2 SEG2 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 (N.C.) (N.C.) (N.C.) (N.C.) COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM4 COM4 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM5 COM5 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM6 COM6 COM62 COM63 (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) QTP pin No Socket pin No IC Pad Name SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG3 SEG3 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG4 SEG4 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG5 SEG5 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG6 SEG6 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG7 SEG7 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG8 SEG8 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG9 SEG9 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG SEG SEG2 SEG3 QTP pin No Socket pin No Name (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) (N.C.) COM3 COM3 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM2 COM2 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM COM COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM COM (N.C.) (N.C.) (N.C.) (N.C.) SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG SEG SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG2 SEG2 SEG22 SEG23

161 APPENDIX A PEIPHEAL CICUIT BOAD FO SC88655 (S5UC88P + S5UC88655P2 + S5UC88655T) APPENDIX A PEIPHEAL CICUIT BOAD FO SC88655 (S5UC88P + S5UC88655P2 + S5UC88655T) This manual describes how to use the Peripheral Circuit Board for SC88655 (S5UC88P + S5UC88655P2 + S5UC88655T). This circuit board is used to provide emulation functions when it is installed in the ICE (S5UC88H5), a debugging tool for the 8-bit Single Chip Microcomputer SC88 Family. The explanation assumes that the SC88655 circuit data has been downloaded into the SC88 Family Peripheral Circuit Board (S5UC88P). For how to download circuit data into the S5UC88P and specifications of the boards, refer to Sections A.4 and A.6, respectively. For details on ICE functions and how to operate the debugger, refer to the separately prepared manuals. A. Names and Functions of Each Part The following explains the names and functions of each part of the S5UC88P, S5UC88655P2 and S5UC88655T. () SW LCDVCC (on the back) I/O # connector (2) (26) Main board (S5UC88P) I/O #3 connector (26) Add-on board (S5UC88655P2) (27) (28) CN- LCD panel (demonstration) board (S5UC88655T) Fig. A.. Board layout The LCD panel (demonstration) board (S5UC88655T) is required when debugging displays on LCD using the peripheral circuit board for SC (3) (4) (5) (6) (7) (8) (9) (26) VLCD VSVD H OSC L H OSC3 L ESET S5UC88P SC88 Family Peripheral circuit board EPSON LED I/O # I/O #2 MONITO (24) (25) (26) Fig. A..2 Panel layout (S5UC88P) SC88655 TECHNICAL MANUAL EPSON 53

162 APPENDIX A PEIPHEAL CICUIT BOAD FO SC88655 (S5UC88P + S5UC88655P2 + S5UC88655T) () SW When downloading circuit data, set this switch to the "3" position. Otherwise, set to position "". (2) LCDVCC (on the back of the S5UC88P board) Unused. However, make sure that the switches are set as a combination as shown in the table below. Table A.. Setting LCDVCC LCDVCC (3) VLCD control Unused. ON OFF OFF OFF OFF ON OFF OFF OFF OFF ON OFF ON OFF OFF ON (4) VSVD control This control is used for varying the power supply voltage to confirm the supply voltage detection (SVD) function. (efer to Section A.5.2, "Differences from Actual IC".) (5) OSC H control This control is used for coarse adjustment of the OSC C oscillation frequency. (6) OSC L control This control is used for fine adjustment of the OSC C oscillation frequency. (7) OSC3 H control This control is used for coarse adjustment of the OSC3 C oscillation frequency. (8) OSC3 L control This control is used for fine adjustment of the OSC3 C oscillation frequency. (9) ESET switch This switch initializes the internal circuits of this board and feeds a reset signal to the ICE. () LED (MPU/MCU) Indicates the MPU or MCU mode. Lit: MPU mode Not lit: MCU mode () LED 2 (BUSMOD), LED 3 (CPUMOD) Indicates the bus and CPU modes (BUSMOD/ CPUMOD register settings). Table A..2 Bus and CPU modes BUSMOD Lit Lit Not lit Not lit CPUMOD Lit Not lit Lit Not lit Bus mode Expansion Single chip CPU mode Maximum Minimum Maximum Minimum (2) LED 4 (CLKCHG) Indicates the CPU operating clock. Lit: OSC3 (CLKCHG register = "") Not lit: OSC (CLKCHG register = "") (3) LED 5 (SOSC) Indicates the OSC oscillation status. Lit: OSC oscillation is on (SOSC register = "") Not lit: OSC oscillation is off (SOSC register = "") (4) LED 6 (SOSC3) Indicates the OSC3 oscillation status. Lit: OSC3 oscillation is on (SOSC3 register = "") Not lit: OSC3 oscillation is off (SOSC3 register = "") (5) LED 7 (SVDON) Indicates the SVD circuit status. Lit: SVD circuit is on (SVDON register = "") Not lit: SVD circuit is off (SVDON register = "") (6) LED 8 (LBON) Indicates the supply voltage booster circuit status. Lit: Supply voltage booster circuit is on (LBON register = "") Not lit: Supply voltage booster circuit is off (LBON register = "") (7) LED 9 (VC5ON) Indicates the VC5 voltage generator status. Lit: VC5 voltage generator is on (VC5ON register = "") Not lit: VC5 voltage generator is off (VC5ON register = "") (8) LED (VCON) Indicates the VC4 voltage generator status. Lit: VC4 voltage generator is on (VCON register = "") Not lit: VC4 voltage generator is off (VCON register = "") (9) LED (LCDON) Indicates the LCD driver circuit status. Lit: LCD driver circuit is on (LCDON register = "") Not lit: LCD driver circuit is off (LCDON register = "") (2) LED 2 (HALT/SLEEP) Indicates the CPU status. Lit: HALT or SLEEP Not lit: UN 54 EPSON SC88655 TECHNICAL MANUAL

163 APPENDIX A PEIPHEAL CICUIT BOAD FO SC88655 (S5UC88P + S5UC88655P2 + S5UC88655T) (2) LED 3 Unused. (22) LED 4 (OSC operating clock) The OSC operating clock is connected to this LED. The corresponding monitor pin (pin 4) can be used to check the OSC clock frequency. (23) LED 5 (OSC3 operating clock) The OSC3 operating clock is connected to this LED. The corresponding monitor pin (pin 5) can be used to check the OSC3 clock frequency. (24) LED 6 (FPGA configuration) If the FPGA on the S5UC88P includes circuit data, this LED lights when the power is turned on. If this LED does not light at powerup, a circuit data must be written to the FPGA before debugging can be started (turn the power on again after writing data). (26) I/O #, I/O #3 connectors These are the connectors for connecting the I/ O and LCD panel board. The I/O cables (8- pin/4-pin 2 flat type, 4-pin/2-pin 2 flat type) are used to connect to the target system. (27) LCD module (standard TCM) This is a dot LCD panel module using the standard TCM (see Appendix C). This LCD module has included an actual SC88655 device, note, however, that the chip is configured to work as only an LCD driver using the device test function (unreleased). (28) ICE connector (CN-) Connect between this connector and I/O # connector on the S5UC88P using the I/O cable (8-pin/4-pin 2 flat type). (25) LED signal monitor connector This connector provides the signals that drive the LEDs shown above for monitoring. The signals listed below are output from the connector pins. The signal level is high when the LED is lit and is low when the LED is not lit Fig. A..3 LED signal monitor connector Pin : LED (MPU/MCU mode) Pin 2: LED 2 (Bus mode) Pin 3: LED 3 (CPU mode) Pin 4: LED 4 (CPU operating clock) Pin 5: LED 5 (OSC oscillation status) Pin 6: LED 6 (OSC3 oscillation status) Pin 7: LED 7 (SVD circuit status) Pin 8: LED 8 (Supply voltage booster circuit status) Pin 9: LED 9 (VC5 voltage generator status) Pin : LED (VC4 voltage generator status) Pin : LED (LCD driver circuit status) Pin 2: LED 2 (HALT/SLEEP, UN status) Pin 4: LED 4 (OSC operating clock) Pin 5: LED 5 (OSC3 operating clock) Pin 8: OSC C oscillation frequency monitor pin Pin 9: OSC3 C oscillation frequency monitor pin Pins 3, 6, 7 and 2 are not used. The C oscillation clock is connected to pins 8 and 9. (The C oscillation circuit on this board always operates even if crystal oscillation is selected by mask option and regardless of the SOSC/3 register status.) These pins can be used to monitor C oscillation when adjusting the oscillation frequency SC88655 TECHNICAL MANUAL EPSON 55

164 VLCD VSVD H OSC L LCD MONITO L ESET ON/OFF APPENDIX A PEIPHEAL CICUIT BOAD FO SC88655 (S5UC88P + S5UC88655P2 + S5UC88655T) A.2 Installation A.2. Installing S5UC88655P2 to S5UC88P Aim the I/O connectors on the add-on board (S5UC88655P2) at the front panel of the main board (S5UC88P) and insert the four connectors on the back of the S5UC88655P2 board into the corresponding connectors on the S5UC88P board. S5UC88655P2 A.3 Connecting to the Target System This section explains how to connect the S5UC88P + S5UC88655P2 to the target system and the LCD panel board (S5UC88655T). Note: Turn the power of all equipment off before connecting or disconnecting cables. Use the I/O cables (8-pin/4-pin 2 flat type, 4- pin/2-pin 2 flat type) to connect the target system to the I/O # and I/O #3 connectors of the front panel. Connect the 8-pin and 4-pin cable connectors to the I/O # and I/O #3 connectors, respectively, and the CN-2 connector of the 4- pin 2 cable and the 2-pin 2 cable connectors (CN3- and CN3-2) to the target system. The LCD panel board (S5UC88655T) is connected to the I/O # connector of the front panel using the CN- connector of the 4-pin 2 cable. Be careful as power (VDD) is supplied to the I/O # and I/O #3 connectors. H OSC3 S5UC88P SC88 Family Peripheral circuit board EPSON I/O # I/O #2 POWE EMU SLP/HALT TGOUT STOPOUT TCIN BKIN GND ESET DIAG ICE88U EC88 Family In-Circuit Emulator S5UC88P Fig. A.2.. Installing S5UC88655P2 to S5UC88P I/O #3 (4-pin) I/O # (8-pin) A.2.2 Installing into the ICE (S5UC88H5) Insert the S5UC88P along by the lower guide rail of the ICE (S5UC88H5), until the connectors fit into the ICE back-panel connectors. ICE (S5UC88H5) S5UC88P S5UC88P +S5UC88655P2 EPSON Fig. A.2.2. Installing into the ICE (S5UC88H5) Note: The S5UC88P and S5UC88655P2 may fail to operate if they are not adequately mounted, so be sure to mount them securely. CN3-2 (2-pin) CN3- (2-pin) CN-2 (4-pin) CN- (4-pin) CN3-2 CN3- Target board CN-2 LCD panel (demonstration) board (S5UC88655T) Fig. A.3. Connecting to the target system The following shows the clock frequencies generated from the on-board crystal oscillation circuits: OSC crystal oscillation circuit: khz OSC3 crystal oscillation circuit: MHz When C oscillation is selected, the oscillation frequency can be adjusted using the controls on the front panel (OSCH and OSCL for adjusting OSC, OSC3H and OSC3L for adjusting OSC3). Use a frequency counter or other equipment to be connected to the OSC C oscillation frequency monitor pin (pin 8) on the monitor connector or OSC3 C oscillation frequency monitor pin (pin 9) for monitoring the frequency during adjustment. Be sure of the frequency when using this monitor pin because the C oscillation frequency is initially undefined. 56 EPSON SC88655 TECHNICAL MANUAL

165 APPENDIX A PEIPHEAL CICUIT BOAD FO SC88655 (S5UC88P + S5UC88655P2 + S5UC88655T) Notes: The LCD panel board operating clock frequency is limited to that of the connected LCD module (standard TCM). If the LCD panel is out of synchronization with the S5UC88P + S5UC88655P2, reset the system using the ESET switch on the S5UC88P. I/O connector pin assignment No Table A.3. I/O # connector 4-pin CN- 4-pin CN-2 Pin name VDD (3.3 V) VDD (3.3 V) VSS VSS DMTAD DMTAD DMTA DMTAD3 DMTAD4 DMTA DMTA DMTAD7 DMTAD8 DMTAD9 DMTAD DMTAD DMTA DMTAD3 DMTAD4 DMTA N.C. DMTEB DMTEB DMTEB2 DMTEB3 DMTEB4 DMTEB5 DMTEB6 DMTEB7 N.C. DMT_XESET N.C. DMT_PK DMT_PL DMT_I/O DMT_I/O DMT_I/O2 DMT_I/O3 DMT_DBS DMT_DBS No Pin name /A8 /A9 2/A 3/A 4/A2 5/A3 6/A4 7/A5 2/A6 2/A7 22/A8 23/A9 24/D 25/W 3/CE 3/CE 32/CE2 33/CE3 N.C. GND_IN OSC3EX GND_IN OSCEX GND_IN N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. No Note: Table A.3.2 I/O #3 connector 2-pin CN3-2-pin CN3-2 Pin name No. Pin name P2/TOUT/TOUT VSS P2/TOUT2/TOUT3 2 VSS P22/FOUT 3 P/D P23/TOUT2/TOUT3 4 P/D P24/BEQ/EXCL 5 P2/ P25/BACK/EXCL 6 P3/D3 P26/CL/EXCL2 7 P4/D4 P27/F/EXCL3 8 P5/ ESET 9 P6/ MCU/MPU P7/D7 N.C. VDD (3.3 V) N.C. 2 VDD (3.3 V) /A 3 P/SIN /A 4 P/SOUT 2/A2 5 P2/SCLK 3/A3 6 P3/SDY 4/A4 7 P4/SIN 5/A5 8 P5/SOUT 6/A6 9 P6/SCLK 7/A7 2 P7/SDY The pin names of the CN- connector indicates the internal signals connected to the connector. This connector must be used to connect the LCD panel (demonstration) board (S5UC88655T) Fig. A.3.2 CN-/CN-2 pin layout 39 4 SC88655 TECHNICAL MANUAL EPSON 57

166 APPENDIX A PEIPHEAL CICUIT BOAD FO SC88655 (S5UC88P + S5UC88655P2 + S5UC88655T) A.4 Downloading Circuit Data to the S5UC88P This board (S5UC88P) comes with the FPGA that contains factory inspection data, therefore the circuit data for the model to be used should be downloaded. The following explains the downloading procedure. ) Set the switch "SW" on this board to the "3" position. 2) Install this board to the ICE (S5UC88H5) as shown in Section A ) Connect the ICE to the host PC. Then turn the host PC and ICE on. 4) Invoke the debugger included in the ICE or assembler package. For how to use the ICE and debugger, refer to the manuals supplied with the ICE and assembler package. 5) Download the circuit data file (.mcs) corresponding to the model by entering the following commands in the command window. >XFE (erase all) >XFW <file name> (download the specified file) 2 >XFCP <file name> (compare the specified file and downloaded data) 6) Terminate the debugger and then turn the ICE off. 7) emove this board from the ICE and set the switch "SW" on the board to the "" position. 8) Install this board to the ICE again. 9) Turn the ICE on and invoke the debugger again. Debugging can be started here. See Figure A.., "Board layout", for the location of SW. 2 The downloading takes about 5 minutes. A.5 Precautions Take the following precautions when using the Peripheral Circuit Board for SC A.5. Precaution for operation () Turn the power of all equipment off before connecting or disconnecting cables. (2) The mask option data must be loaded before debugging can be started. A.5.2 Differences from actual IC Caution is called for due to the following function and property related differences with the actual IC. If these precautions are overlooked, it may not operate on the actual IC, even if it operates on the ICE in which the Peripheral Circuit Board for SC88655 has been installed. () I/O differences Interface power voltage This board and target system interface voltage is set to +3.3 V. To obtain the same interface voltage as in the actual IC, attach a level shifter or similar circuit on the target system side to accommodate the required interface voltage. Drive capability of each output port The drive capability of each output port on this board is higher than that of the actual IC. When designing the application system and software, refer to Chapter 9, "Electrical Characteristics", to confirm the drive capability of each output port. Input port characteristics The AC characteristic of the input terminal is different from that of the actual IC and it affects the input interrupt function. Therefore, evaluate the operation in the actual IC if the rise/fall time of the input signal is long. Protective diode of each port All I/O ports incorporate a protective diode for VDD and VSS, and the interface signals between this board and the target system are set to +3.3 V. Therefore, this board and the target system cannot be interfaced with a voltage exceeding VDD even if the output ports are configured with open-drain output. 58 EPSON SC88655 TECHNICAL MANUAL

167 APPENDIX A PEIPHEAL CICUIT BOAD FO SC88655 (S5UC88P + S5UC88655P2 + S5UC88655T) Pull-up resistance value The pull-up resistance values on this board are set to kω which differ from those for the actual IC. For the resistance values on the actual IC, refer to Chapter 9, "Electrical Characteristics". Note that when using pull-up resistors to pull the input terminals high, the input terminals may require a certain period to reach a valid high level. Exercise caution if a key matrix circuit is configured using a combination of output and input ports, since rise delay times on these input ports differ from those of the actual IC. (2) Differences in current consumption The amount of current consumed by this board differs significantly from that of the actual IC. Inspecting the LEDs on the S5UC88P front panel may help keep track of approximate current consumption. The following factors/components greatly affect device current consumption: Those which can be verified by LEDs and monitor pins a) un and Halt execution ratio (verified by LEDs and monitor pins on the ICE) b) CPU operating clock change control (LED 4: monitor pin 4) c) OSC oscillation on/off control (LED 5: monitor pin 5) d) OSC3 oscillation on/off control (LED 6: monitor pin 6) e) SVD circuit on/off control (LED 7: monitor pin 7) f) Supply voltage booster circuit (LED 8: monitor pin 8) g) VC5 voltage generator (LED 9: monitor pin 9) h) VC4 voltage generator (LED : monitor pin ) i) LCD control (LED : monitor pin ) j) SLEEP and HALT execution ratio (LED 2: monitor pin 2) k) OSC operating clock (LED 4: monitor pin 4) l) OSC3 operating clock (LED 5: monitor pin 5) Those that can only be counteracted by system or software m) Current consumed by the internal pull-up resistors n) Input ports in a floating state (3) Functional precautions SVD circuit The SVD function is realized by artificially varying the power supply voltage using the VSVD control on the front panel of the S5UC88P. There is a finite delay time from when the power to the SVD circuit turns on until actual detection of the voltage. The delay time on this board differs from that of the actual IC. efer to Chapter 9, "Electrical Characteristics", when setting the appropriate wait time for the actual IC. The evaluation voltages supported in this board are different from those of the actual IC. When debugging the SVD operation using this board, evaluate the SVD results as levels not voltages. Oscillation circuit The OSC crystal oscillation frequency is fixed at khz. The OSC C oscillation frequency can be adjusted in the range of approx. 2 khz to 5 khz using the control on the S5UC88P front panel. Note that the actual IC does not operate with all of these frequencies; refer to Chapter 9, "Electrical Characteristics", to select the appropriate operating frequency. The OSC3 crystal oscillation frequency is fixed at MHz. The OSC3 C oscillation frequency can be adjusted in the range of approx. khz to 8 MHz using the control on the S5UC88P front panel. Note that the actual IC does not operate with all of these frequencies; refer to Chapter 9, "Electrical Characteristics", to select the appropriate operating frequency. The Peripheral Circuit Board for SC88655 does not include the OSC3 ceramic oscillation circuit. When ceramic oscillation circuit is selected by mask option, the Peripheral Circuit Board for SC88655 uses the on-board crystal oscillation circuit. When using an external clock, adjust the external clock (amplitude: 3.3 V ±5%, duty: 5% ±%) and input to the OSCEX or OSC3EX terminal with VSS as GND. Moreover, the GND_IN terminals adjacent to the OSCEX and OSC3EX terminals should be connected to the GND line in order to stabilize the clock waveforms. SC88655 TECHNICAL MANUAL EPSON 59

168 APPENDIX A PEIPHEAL CICUIT BOAD FO SC88655 (S5UC88P + S5UC88655P2 + S5UC88655T) This board can operate normally even when the CPU clock is switched to OSC3 (CLKCHG = "") immediately after the OSC3 oscillation control circuit is turned on (SOSC3 = "") without a wait time inserted. In the actual IC, an oscillation stability wait time is required before switching the CPU clock after the OSC3 oscillation is turned on. efer to Chapter 9, "Electrical Characteristics", when setting the appropriate wait time for the actual IC. This board can operate normally even when the CPU clock is switched to OSC (CLKCHG = "") immediately after the OSC oscillation control circuit is turned on (SOSC = "") without a wait time inserted. In the actual IC, an oscillation stability wait time is required before switching the CPU clock after the OSC oscillation is turned on. efer to Chapter 9, "Electrical Characteristics", when setting the appropriate wait time for the actual IC. This board starts operating without waiting for an oscillation start time after SLEEP status is cancelled. Use separate instructions to switch the clock from OSC3 to OSC and to turn off the OSC3 oscillation circuit. If executed simultaneously with a single instruction, these operations, although good with this board, may not function properly with the actual IC. This board contains oscillation circuits for OSC and OSC3. Keep in mind that even though the actual IC may not have a resonator connected to its OSC3, this board can operate with the OSC3 circuit. Because the logic level of the oscillation circuit is high, the timing at which the oscillation starts on this board differs from that of the actual IC. Access to undefined address space If any undefined space in the SC88655's internal OM/AM or I/O is accessed for data read or write operations, the read/written value is indeterminate. Additionally, it is important to remain aware that the indeterminate state differs between the Peripheral Circuit Board for SC88655 and the actual IC. eset circuit Keep in mind that the operation sequence from when the ICE with this board installed is powered on until the time at which the program starts running differs from the sequence of the actual IC. This is because this board becomes capable of operating as a debugging system after the user program and optional data are downloaded. Internal power supply circuit The LCD drive voltage on this board is different from that on the actual IC. Function option Input interface level The actual IC allows selection of the input interface level for PP7 and P2P27 either COMS level or CMOS Schmitt level by a function option. This board supports CMOS level only and selection of the function option using Winfog does not affect the interface level of this board. (4) Notes on model support Parameter file The OM, AM and I/O spaces in the ICE with this board installed are configured when the debugger on the personal computer starts up using the parameter file (88655.par) provided for each model. The parameter file allows the user to modify its contents according to the OM and AM spaces actually used. Do not configure areas other than below when using the IC in single chip maximum mode. OM area: H to BFFFH H to 8FFFFH AM area: CH to E3FFH E8H to EBFFH Stack area: CH to DFFFH Access disable area When using this board for development of an SC88655 application, be sure not to read and write from/to I/O memory addresses FF22H and FFCH to FFDDH. Furthermore, do not change the initial values when writing to bit D4 of address FF23H. 6 EPSON SC88655 TECHNICAL MANUAL

169 APPENDIX A PEIPHEAL CICUIT BOAD FO SC88655 (S5UC88P + S5UC88655P2 + S5UC88655T) A.6 Product Specifications A.6. S5UC88P specifications S5UC88P Dimensions (mm): (wide) 65 (depth) 44.6 (height) Weight: Approx. 5 g Power supply: DC 5 V ± 5%, less than A (supplied from ICE main unit) I/O connection cable (8-pin/4-pin x 2, 2 cables) S5UC88P connector (8-pin): KEL 883E-8-7L, or equivalent Cable connector (8-pin): KEL 8822E-8-7 Cable connector (4-pin): 3M SC 2 Cable: 4-pin flat cable 2 Interface: CMOS interface (3.3 V) Length: Approx. 4 cm Monitor signal cable S5UC88P connector: 3M 76-52SC, or equivalent Cable connector (-pin): 3M 79-65SC Interface: CMOS interface (3.3 V) Length: Approx. 4 cm Accessories 4-pin connector for the target system: 3M LCSC 4 A.6.2 S5UC88655P2 specifications S5UC88655P2 Dimensions (mm): 84 (W) 52 (D) 2 (H) I/O cable (-pin/5-pin x 2) S5UC88655P2 connector (-pin): KEL 883E--7L-F Cable connector (-pin): KEL 8822E--7-F Cable connector (5-pin): Connector 3M SC 2 Strain relief 3M Cable: 5-pin flat cable Interface: CMOS interface (3.3 V) Length: Approx. 4 cm I/O cable (4-pin/2-pin x 2) S5UC88655P2 connector (4-pin): KEL 883E-4-7L-F Cable connector (4-pin): KEL 8822E-4-7-F Cable connector (2-pin): Connector 3M SC 2 Strain relief 3M Cable: 2-pin flat cable Interface: CMOS interface (3.3 V) Length: Approx. 4 cm Accessories 5-pin connector for the target system: 3M LCPL 2 2-pin connector for the target system: 3M LCPL 2 A.6.3 S5UC88655T specifications S5UC88655T Dimensions (mm): (W) 5 (D) 38 (H) S5UC88655T connector 3M LCPL Interface CMOS interface (3.3 V) SC88655 TECHNICAL MANUAL EPSON 6

170 APPENDIX B USING FONT DATA APPENDIX B USING FONT DATA Font packages that can be used to display on LCD are provided for the SC The package contains a sample program that runs on the SC88-Family microcomputer to display this font data on an LCD, an application note for the sample program, and a bitmap utility that can be used to create custom font data. The font data is supplied in an object file format (assembler output file identified by the extension.obj) to enable it to be embedded in the SC88- Family microcomputer programs. Simply by linking this object file to the created application program, the font data can be used easily. Notes: Before the font data included with the package and the typefaces shown in the manual can be used, a contract for a license to use the typefaces must be concluded between Seiko Epson and the purchaser. The programs necessary to obtain font data from the character codes and display the font data on an LCD must be created by the user. List of font packages S5UC dot Japanese font (JIS level- and level-2, other characters) S5UC dot Korean font (KSX) User-developed program Please contact Seiko Epson for other font packages. Compile Assemble Linker Font data object Locator Executable file 62 EPSON SC88655 TECHNICAL MANUAL