INTEGRATED CIRCUITS V3.1. Version Originator Date FZB Comments

Transcription

1 INTEGRATED CIRCUITS DATA SHEET Change history: V3. Version Originator Date FZB Comments V2. P.Oelhafen 2 Jul. 33 RFS update V2. P.Oelhafen 4 Aug. 44 RFS update fig4 correction V2.2 P.Oelhafen 9 Aug. 46 Update fig4 correction V3. P. Mueller 24 Jul 3 8_v2 Update (from 2.2)for shrink PCF882/2 65 x 2 pixels matrix LCD driver November 29, 2

2 65 x 2 pixels matrix LCD driver PCF882/2 CONTENTS FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING INFORMATION 7 PIN FUNCTIONS 7. R to R64 row driver outputs 7.2 C to C column driver outputs 7.3 V SS,2 : Negative power supply rails 7.4 V DD,2,3 : Positive power supply rails 7.5 V LCDIN : LCD power supply 7.6 V LCDOUT : LCD power supply 7.7 V LCDSENSE : voltage multiplier regulation input (VLCD) 7.8 T to T5: test pads 7.9 SDIN: serial data line 7. SCLK: serial clock line 7. D/C: mode select 7.2 SCE: chip enable 7.3 OSC: oscillator 7.4 RES: reset 8 FUNCTIONAL DESCRIPTION 8. Oscillator 8.2 Address counter (AC) 8.3 Display data RAM (DDRAM) 8.4 Timing generator 8.5 Display address counter 8.6 LCD row and column drivers 9 ADDRESSING 9. data structure INSTRUCTIONS. Initialization.2 Reset function.3 Function Set.3. PD.3.2 V.3.3 H.4 Display Control.4. D, E.5 Set Y address of RAM.6 Set X address of RAM.7 Set HV-generator stages.8 Bias system.9 Temperature Control. Set V OP value: LIMITING VALUES 2 HANDLING 3 DC CHARACTERISTICS 4 AC CHARACTERISTICS 5 SERIAL INTERFACE 6 RESET 7 APPLICATION INFORMATION 8 CHIP INFORMATION 9 PADS INFORMATION 2 DEVICE PROTECTION DIAGRAM 2 TRAY INFORMATION 22 DEFINITIONS 23 LIFE SUPPORT APPLICATIONS November 9, 2 2

3 65 x 2 pixels matrix LCD driver PCF882/2 FEATURES Single Chip Lcd Controller/driver 65 Row, 2 Column Outputs Display Data Ram 65x2 Bits On-chip: Configurable 5 (4, 3, 2) * Voltage Multiplier Generating V lcd (External V lcd Also Possible) Generation Of Intermediate Lcd Bias Voltages Oscillator Requires No External Components (External Clock Also Possible) External Res (Reset) Input Pin Serial Interface Max. 4.Mbit/s Cmos Compatible Inputs Mux Rate: 65 Logic Supply Voltage Range V dd -v ss 2.5 To 5.5V High voltage generator Supply Voltage Range V dd2,3 -v ss 2.5V To 4.5V Display Supply Voltage Range V lcd -v ss 4.5 To 9.V Low Power Consumption, Suitable For Battery Operated Systems Temperature Compensation Of V lcd. Temperature Range: -4 To +85 Degree Slim chip layout, suited for chip-on-glass (COG) applications. 2 APPLICATIONS Telecom Equipment 3 GENERAL DESCRIPTION The PCF882 is a Low Power Cmos Lcd Controller Driver, designed to drive a graphic display of 65 Rows and 2 Columns. All necessary functions for the display are provided in a single chip, including on-chip generation of Lcd supply and bias voltages, resulting in a minimum of external components and low power consumption. The PCF882 interfaces to microcontrollers via a Serial Bus Interface. 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION PCF882U/2DA/2 TRAY chip with bumps in tray November 9, 2 3

4 65 x 2 pixels matrix LCD driver PCF882/2 5 BLOCK DIAGRAM C TO C R TO R64 V LCDIN BIAS VOLTAGE GENERATOR COLUMN DRIVERS DATA LATCHES ROW DRIVERS SHIFT REGISTER V LCDSENSE V LCDOUT HIGH VOLTAGE GENERATOR 4 stages RESET OSCILLATOR RES OSC V DD,2,3 V SS,2 DISPLAY DATA RAM (DPRAM) [65x2] TIMING GENERATOR T T2 ADDRESS COUNTER DISPLAY ADDRESS COUNTER T3 T4 T5 DATA REGISTER I/O BUFFER SDIN SCLK D/C SCE Fig. block diagram November 9, 2 4

5 65 x 2 pixels matrix LCD driver PCF882/2 6 PINNING INFORMATION SYMBOL R to R64 C to C V SS,2 V DD,2,3 V LCDIN V LCDOUT V LCDSENSE T T2 T3 T4 T5 SDIN SCLK D/C SCE OSC RES DESCRIPTION LCD row driver outputs LCD column driver outputs ground supply voltage LCD supply voltage (VLCD) Voltage multiplier output (VLCD) Voltage multiplier regulation input (VLCD) test input test 2 output test 3 I/O test 4 input test 5 input serial data input serial clock input data/command chip enable oscillator external reset input 7 PIN FUNCTIONS 7. R to R64 row driver outputs These pads output the row signals. 7.2 C to C column driver outputs These pads output the column signals. 7.3 V SS,2 : Negative power supply rails The 2 supply rails V SS and V SS2 must be connected together. 7.4 V DD,2,3 : Positive power supply rails V DD2, and V DD3 are the supply voltage for the internal voltage generator. Both have the same voltage and may be connected together outside of the chip. V DD is used as supply for the rest of the chip. V DD can be connected together with V DD2,3 but in this case care must be taken to respect the supply voltage range (see chapter DC Characteristics ). If the internal voltage generator is not used the pin V DD2,3 must be connected to the pin V DD or connected to power. 7.5 V LCDIN; : LCD power supply Positive power supply for the liquid crystal display. An external LCD supply voltage can be supplied using the V LCDIN pad. In this case, V LCDOUT has to be left open, and the internal voltage generator has to be programmed to zero. If the PCF882 is in power-down mode, the external LCD supply voltage has to be switched off. November 9, 2 5

6 65 x 2 pixels matrix LCD driver PCF882/2 7.6 V LCDOUT : LCD power supply Positive power supply for the liquid crystal display. If the internal voltage generator is used, the two supply rails V LCDIN and V LCDOUT must be connected together. If an external supply is used this pin must be left open. 7.7 V LCDSENSE : voltage multiplier regulation input (VLCD) V LCDSENSE is the input of the internal voltage multiplier regulation. If the internal voltage generator is used then V LCDSENSE must be connected to V LCDOUT. If a external supply voltage is used then the V LCDSENSE can be let open or connected to ground. 7.8 T to T5: test pads T,T3, T4 and T5 must be connected to V SS, T2 must be left open. Not accessible to user. 7.9 SDIN: serial data line Input for the data line. 7. SCLK: serial clock line Input for the clock signal Mbits/s. 7. D/C: mode select Input to select either command/address or data input. 7.2 SCE: chip enable The enable pin allows data to be clocked in. Signal is active low. 7.3 OSC: oscillator When the on-chip oscillator is used this input must be connected to V DD. An external clock signal, if used, is connected to this input. If the oscillator and external clock are both inhibited by connecting the OSC pin to V SS the display is not clocked and may be left in a DC state. To avoid this the chip should always be put into Power Down Mode before stopping the clock. 7.4 RES: reset This signal will reset the device and must be applied to properly initialize the chip. Signal is active low. 8 FUNCTIONAL DESCRIPTION 8. Oscillator The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC input must be connected to V DD. An external clock signal, if used, is connected to this input. 8.2 Address counter (AC) The address counter assigns addresses to the display data RAM for writing. The X-address X[6:] and the Y-address Y[3:] are set separately. After a write operation the address counter is automatically incremented by according to the V flag (see chapter ADDRESSING ). November 9, 2 6

7 65 x 2 pixels matrix LCD driver PCF882/2 8.3 Display data RAM (DDRAM) The PCF882 contains a 65 x 2 bit static RAM which stores the display data. The RAM is divided into 8 banks of 2 bytes (8 x 8 x 2 bits) and one bank of 2 bits (x2 bits). During RAM access, data is transferred to the RAM via the serial interface. There is a direct correspondence between X-address and column output number. 8.4 Timing generator The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not affected by operations on the data buses. 8.5 Display address counter The display is generated by continuously shifting rows of RAM data to the dot matrix LCD via the column outputs. The display status (all dots on/off and normal/inverse video) is set by bits E and D in the command Display control (see table 2). 8.6 LCD row and column drivers The PCF882 contains 65 row and 2 column drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. Fig.2 shows typical waveforms. Unused outputs should be left unconnected. November 9, 2 7

8 65 x 2 pixels matrix LCD driver PCF882/2 ROW R (t) V LCD V 2 V 3 V 4 V 5 V SS frame n frame n+ V state (t) V state2 (t) ROW R (t) V LCD V 2 V 3 V 4 V 5 V SS COL C (t) V LCD V 2 V 3 V 4 V 5 V SS COL C (t) V LCD V 2 V 3 V 4 V 5 V SS V LCD - V SS V 3 - V SS Vstate(t) V LCD - V 2 V V 3 - V 2 V 4 - V 5 V V SS - V 5 V 4 - V LCD V SS - V LCD V LCD - V SS V 3 - V SS Vstate2(t) V LCD - V 2 V V 3 - V 2 V 4 - V 5 V V SS - V 5 V 4 - V LCD V SS - V LCD V state (t) = C(t) - R(t) V state2 (t) = C(t) - R(t) Fig.2 Typical LCD driver waveforms. November 9, 2 8

9 65 x 2 pixels matrix LCD driver PCF882/2 bank DPRAM Top of LCD bank bank 2 bank 3 bank 7 bank 8 Fig.3 DPRAM to display mapping. November 9, 2 9

10 65 x 2 pixels matrix LCD driver PCF882/2 9 ADDRESSING Data is downloaded in bytes into the RAM matrix of PCF882 as indicated in Figs.3, 4, 5, 6. The display RAM has a matrix of 65 by 2 bits. The columns are addressed by the address pointer. The address ranges are: X to (), Y to 8 (). Addresses outside these ranges are not allowed. In vertical addressing mode (V=) the Y address increments after each byte (see Fig.6). After the last Y address (Y = 8) Y wraps around to and X increments to address the next column. In horizontal addressing mode (V=) the X address increments after each byte (see Fig.5). After the last X address (X = ) X wraps around to and Y increments to address the next row. After the very last address (X =, Y = 8) the address pointers wrap around to address (X =, Y = ). 9. data structure MSB LSB MSB 8 LSB X-address Y-address Fig.4 RAM format, addressing November 9, 2

11 65 x 2 pixels matrix LCD driver PCF882/ X-address 8 Y-address Fig.5 sequence of writing data bytes into RAM with vertical addressing (V=) Y-address X-address Fig.6 sequence of writing data bytes into RAM with horizontal addressing (V=) INSTRUCTIONS The instruction format is divided into two modes: If D/C (mode select) is set low the current byte is interpreted as command byte (see Table Instruction set ). Fig.8 shows an example of a serial data stream for initialising the chip. If D/C is set high the following bytes are stored in the DISPLAY DATA RAM. After every data byte the address counter is incremented automatically. The level of the D/C signal is read during the last bit of data byte. Every instruction can be sent in any order to the PCF882. The MSB of a byte is transmitted first. Fig.8 shows one possible command stream, used to set up the LCD driver. The serial interface is initialized when SCE is high. In this state SCLK clock pulses have no effect and no power is consumed by the serial interface. A negative edge on SCE enables the serial interface and indicates the start of a data transmission. November 9, 2

12 65 x 2 pixels matrix LCD driver PCF882/2 MSB (DB7) LSB (DB) data data Fig.7 general format of data stream function set (H=) bias system set V OP temperature control function set (H=) display control Y address X address Fig.8 serial data stream, example Fig.9 and Fig. show the serial bus protocol. When SCE is high, sclk clocks are ignored. During the high time of SCE the serial interface is initialized (see Fig.2). SDIN is sampled at the positive edge of SCLK. D/C indicates, whether the byte is a command (D/C=) or RAM data (D/C=). It is read with the eighth SCLK pulse. If SCE stays low after the last bit of a command/databyte, the serial interface expects DB7 of the next byte at the next positive edge of SCLK (see Fig.2). In case that SCLK goes low after the last data bit (DB), either: A rising clock edge is required to latch the last data bit. Or the last bit is latched when SCE goes high. A reset pulse with RES interrupts the transmission. No data are written into the RAM. The registers are cleared. If SCE is low after the positive edge of RES, the serial interface is ready to receive bit 7 of a command/databyte(see Fig.2). SCE D/C SCLK SDIN DB7 DB6 DB5 DB4 DB3 DB2 DB DB Fig.9 serial bus protocol - transmission of one byte November 9, 2 2

13 65 x 2 pixels matrix LCD driver PCF882/2 SCE D/C SCLK SDIN DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB7 DB6 DB5 Fig. serial bus protocol - transmission of several bytes SCE D/C RES SCLK SDIN DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB7 DB6 DB5 Fig. serial bus Reset function (SCE) SCE RES D/C SCLK SDIN DB7 DB6 DB5 DB4 DB3 DB7 DB6 DB5 DB4 DB3 DB2 DB DB DB7 DB6 DB5 DB4 Fig.2 serial bus Reset function (RES) November 9, 2 3

14 65 x 2 pixels matrix LCD driver PCF882/2 Table Instruction set COMMAND BYTE D/C DB7 DB6 DB5 DB4 DB3 DB2 DB DB INSTRUCTION DESCRIPTION (H = or ) NOP No operation Function Set PD V H Power down control. Entry mode. Extended Instruction Set control (H) Write Data D 7 D 6 D 5 D 4 D 3 D 2 D D Writes data to Display RAM. INSTRUCTION DESCRIPTION (H = ) reserved X X Do not use Display Control D E Sets display configuration. Set higher, lower PRS V LCD programming range select. program. range Vop Set Y address of Y 3 Y 2 Y Y Sets Y-address of RAM. RAM. Y 8 Set X address of RAM. X 6 X 5 X 4 X 3 X 2 X X Sets X-address part of RAM. X INSTRUCTION DESCRIPTION (H = ) reserved Do not use reserved X Do not use Temperature TC TC set temperature coefficient (TCx) Control HVgen stages S S # of HVgen voltage multiplication Bias System BS 2 BS BS Set Bias System(BSx) reserved X X X X X X Do not use (reserved for test...) Set V OP V OP6 V OP5 V OP4 V OP3 V OP2 V OP V OP Write V OP to register Table 2 Explanations for symbols in table Bit RESET STATE PD Chip is active Chip is in power down mode V Horizontal addressing Vertical addressing H Use basic instruction set Use extended instruction set PRS Vlcd programming range LOW Vlcd programming range HIGH D,E Display blank Normal mode All display segments on Inverse video mode TC[:] V LCD temperature coefficient V LCD temperature coefficient V LCD temperature coefficient 2 V LCD temperature coefficient 3 D = E = TC[:] = November 9, 2 4

15 65 x 2 pixels matrix LCD driver PCF882/2 S[:] 2* voltage multiplier 3* voltage multiplier 4* voltage multiplier S[:] = 5* voltage multiplier Vop[6;] V LCD programming Vop[6:] = BS[2:] bias system BS[2:] =. Initialization Immediately following power-on, all internal registers as well the RAM content are undefined. A RES pulse must be applied. Reset is accomplished by applying an external reset pulse (active low) at the pad RES. When reset occurs within the specified time, all internal registers are reset however the RAM is still undefined. The state after reset is described in section.2. RES input must be <=.3 V DD when V DD reaches V DDmin (or higher) within a maximal time t VHRL after V DD going high (see Fig.6)..2 Reset function After reset the LCD driver has the following state: Power down mode (PD = ) Horizontal addressing (V = ) Normal instruction set (H = ) Display blank (E = D = ) Address counter X[6:] =, Y[3:] = Temperature control mode (TC[:] = ) Bias system (BS[2:] = ) V LCD is equal to, the HV generator is switched off (V OP [6:] = and PRS=) After power-on, RAM data are undefined, the reset signal doesn t change the content of the RAM. All LCD-outputs at V SS (display off)..3 Function Set.3. PD all LCD outputs at V SS (display off) bias generator and V LCD generator off, V LCD can be disconnected oscillator off (external clock possible) serial bus, command, etc function RAM contents not cleared; RAM data can be written. Vlcd discharged to Vss in power down mode..3.2 V When V =, the horizontal addressing is selected. The data is written into the DDRAM as shown in Fig.5. When V =, the vertical addressing is selected. The data is written into the DDRAM as shown in Fig.6 November 9, 2 5

16 65 x 2 pixels matrix LCD driver PCF882/2.3.3 H When H = the commands display control, set Y address, set X address, set the PRS bit (low or high range of the high voltage generator) can be performed, when H = the others can be executed. The commands write data and function set can be executed in both cases..4 Display Control.4. D, E The bits D and E select the display mode (see Table 2)..5 Set Y address of RAM Y[3:] defines the Y address vector address of the display RAM. X/Y Address range Y Y Y Y 3 2 CONTENT ALLOWED X-RANGE bank (display RAM) to bank (display RAM) to bank 2 (display RAM) to bank 3 (display RAM) to bank 4 (display RAM) to bank 5 (display RAM) to bank 6 (display RAM) to bank 7 (display RAM) to bank 8 (display RAM) to In the bank 8 only the LSB is accessed..6 Set X address of RAM The X address points to the columns. The range of X is... (65 hex)..7 Set HV-generator stages The PCF882/2 incorporates a software configurable voltage multiplier. After reset (RES) the voltage multiplier is set to 2*V DD2. Other voltage multiplier factors are set via the command Set HV-gen stages (see table, 2)..8 Bias system The bias voltage levels are set in the ratio of R - R - nr - R - R giving a /(n+4) bias system. Different multiplex rates require different factors n (see Table 3). This is programmed by BS[2:]. For MUX :65 the optimum Bias value n is given by resulting in /9 bias. n = 65 3 = 5.62 = 5 November 9, 2 6

17 65 x 2 pixels matrix LCD driver PCF882/2 Table 3 Programming the required Bias system BS[2] BS[] BS[] n recommend mux-rate 7 : 6 :8 5 :65 / :65 4 :48 3 :4 / :34 2 :24 :8 / :6 : / :9 / :8 Table 4 LCD bias voltage symbol bias voltages bias voltages for n=5 (/9 bias) V V LCD V LCD V2 (n+3) / (n+4) 8/9 x V LCD V3 (n+2) / (n+4) 7/9 x V LCD V4 2 / (n+4) 2/9 x V LCD V5 / (n+4) /9 x V LCD V6 V SS V SS.9 Temperature Control Due to the temperature dependency of the liquid crystals viscosity the LCD controlling voltage V LCD must be increased with lower temperature to maintain optimal contrast. There are 4 different temperature coefficients available in the PCF882/2 (see Fig.3). The coefficients are selected by the two bits TC[ : ]. Table 5 shows the typical values of the different temperature coefficients. The coefficients are proportional to the programmed V LCD. November 9, 2 7

18 65 x 2 pixels matrix LCD driver PCF882/2 V LCD T CUT see table5 temperature Fig.3 Temperature coefficients.. Set V OP value: The operation voltage V LCD can be set by software. The generated voltage is dependent on temperature, programmed temperature coefficient (TC) and the programmed voltage at reference temperature (T CUT ). () V LCD T ( ) = ( a + VOP b) ( + ( T T CUT ) TC) The voltage at reference temperature (V LCD (T=T CUT )) can be calculated as: V LCD ( T TCUT ) = = ( a + VOP b) (2) The parameters are explained in table 5.The maximum voltage that can be generated is depending on the V DD2 voltage and the display load current. Two overlapping V LCD ranges are selectable via the command Hvgen control. For the LOW (PRS=) range a=a and for the HIGH (PRS=) range a=a 2 with steps equal to b in both ranges. Note that the charge pump is turned off if V OP [6;] and the bit PRS are all set to zero. (see figure4) For MUX :65 the optimum operation voltage of the liquid can be calculated as + 65 V LCD = V th = 6.85 V th where V th is the threshold voltage of the liquid crystal material used. November 9, 2 8

19 65 x 2 pixels matrix LCD driver PCF882/2 Table 5 Typical values for parameters for the HV-Generator programming SYMBOL VALUE UNIT a 2.94 (PRS=) V a (PRS=) V b.3 V T CUT 27 C V LCD b a Charge pump off a + b a D 7E 7F LOW (PRS=) D 7E 7F HIGH (PRS=) V OP [6:] (programmed) [ hex... 7F hex, prog. range LOW and HIGH Fig.4 V OP programming of PCF882/2 (at T=T CUT ) As the programming range for the internally generated V LCD allows values above the max. allowed V LCD (9V) the user has to ensure while setting the V OP register and selecting the temperature compensation (TC), that under all conditions and including all tolerances the V LCD remains below 9.V. November 9, 2 9

20 65 x 2 pixels matrix LCD driver PCF882/2 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 34); see notes and 2. SYMBOL PARAMETER MIN MAX UNIT V DD supply voltage range V V DD2,3 supply voltage range V V LCD supply voltage range LCD V V i all input voltages -.5 V DD +.5 V I SS ground supply current -5 5 ma I i, Io DC input or output current - ma P TOT total power dissipation - 3 mw P O power dissipation per output - 3 mw T stg storage temperature C V es electrostatic handling voltage according Human Body Model (C=pF, R=.5kΩ) electrostatic handling voltage according Machine Model (C=2pF, L=.75µH) ±8 V ±2 V Notes. Stresses above those listed under Limiting Values may cause permanent damage to the device. 2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V SS unless otherwise noted. 2 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see Handling MOS devices ). November 9, 2 2

21 65 x 2 pixels matrix LCD driver PCF882/2 3 DC CHARACTERISTICS V DD = 2.5 V to 5.5V; V SS = V; V LCD = 4.5 to 9.V; Tamb = -4 C to +85 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V DD supply voltage range V V DD2,3 supply voltage range LCD voltage internally generated (voltage generator enabled) V V LCDIN LCD supply voltage range LCD voltage externally supplied (voltage generator disabled) V LCDOUT LCD supply voltage range; LCD voltage internally generated (voltage generator enabled) note I(V DD,2,3 ) I(V DD,2,3 ) total supply current (normal mode) total supply current (power-down mode) V DD = 2.8V; V LCD = 7.6V; f SCLK = ; T amb = 25 C; no display-load; 4x charge pump note 2, note 7 with internal or external V LCD supply voltage note 3 I(V LCDIN ) supply current external V LCD V DD = 2.8V; V LCD = 7.6V; f SCLK = ; T = 25 C; no display load. note 2, note 4, note V V µa.5 µa 3 µa Logic V IL LOW level input voltage V SS -.3 V DD V V IH HIGH level input voltage.7 V DD - V DD V I L leakage current V I = V DD or V SS µa Column and row outputs R col R row column output resistance C to C row output resistance R to R64 I LOAD = µa Outputs tested one at the time kω kω V col bias tolerance C to C - mv V row bias tolerance R to R64 - mv LCD supply voltage generator V LCD V LCD tolerance internally generated; note 5, 6 V DD = 2.8V; V LCD = 7.6V; f SCLK = ; T amb = 25 C; display-load = µa; note 7 TC V LCD temperature coefficient V DD = 2.8V; f SCLK = ; T amb = -2 to +7 C; display-load = µa; note mv. -3 / C November 9, 2 2

22 65 x 2 pixels matrix LCD driver PCF882/2 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT TC V LCD temperature coefficient V DD = 2.8V; f SCLK = ; T amb = -2 to +7 C; display-load = µa; note 7 TC2 V LCD temperature coefficient 2 V DD = 2.8V; f SCLK = ; T amb = -2 to +7 C; display-load = µa; note 7 TC3 V LCD temperature coefficient 3 V DD = 2.8V; f SCLK = ; T amb = -2 to +7 C; display-load = µa; note / C / C / C Notes to the DC characteristics. The maximum possible V LCD voltage that may be generated is dependent on voltage, temperature and (display) load. 2. internal clock 3. During power down all static currents are switched off. 4. If external V LCD, the display load current is not transmitted to I DD. 5. tolerance depend on the temperature; (typical null at 27 C, maximum tolerance values are measured at the temperate range limit, max. tolerance is proportional to Vlcd. 6. For TC to TC3. 7. f SCLK = means no serial clock. November 9, 2 22

23 65 x 2 pixels matrix LCD driver PCF882/2 4 AC CHARACTERISTICS V DD = 2.5 V to 5.5V; V SS = V; V LCD = 4.5 to 9.V; Tamb = -4 C to +85 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT f OSC oscillator frequency V DD = 2.8V; T amb = -2 to +7 C; khz f EXT external clock frequency khz f FRAME frame frequency () f OSC or f EXT = 38 khz 73 Hz t VHRL VDD to RES LOW (see Fig.6) us t RW reset low pulse width (see Fig.6) 5 ns Serial bus timing characteristics f SCLK clock frequency V DD =3.V±% 4. MHz All signal timing is based on 2% to 8% of V DD and maximum rise&fall time ns. t CYC t PWH t PWL clock cycle SCLK SCLK pulse width high SCLK pulse width low 25 ns ns ns t S2 t H2 t PWH2 t H5 SCE setup time SCE hold time SCE min high time SCE start hold time (2) 6 ns ns ns ns t S3 t H3 D/C setup time D/C hold time ns ns t S4 t H4 SDIN setup time SDIN hold time ns ns Note. T FRAME = f EXT t H5 is the time from the previous SCLK positive edge (irrespective of the state of SCE) to the negative edge of SCE (see Fig.6) November 9, 2 23

24 65 x 2 pixels matrix LCD driver PCF882/2 5 SERIAL INTERFACE SCE t S2 t H2 t PWH2 t S3 t H3 (t H5 ) t H5 D/C t PWL t PWH t CYC t S2 SCLK t S4 t H4 SDIN Fig.5 serial interface timing 6 RESET VDD RES t RW t RW VDD t VHRL RES t RW t RW Fig.6 reset timing November 9, 2 24

25 65 x 2 pixels matrix LCD driver PCF882/2 7 APPLICATION INFORMATION Table 6 programming example for PCF882 STEP SERIAL BUS BYTE DISPLAY OPERATION Start SCE is going low. 2 D/C 3 D/C 4 D/C 5 D/C 6 D/C 7 D/C DB7 DB7 DB7 DB7 DB7 DB7 DB6 DB6 DB6 DB6 DB6 DB6 DB5 DB5 DB5 DB5 DB5 DB5 DB4 DB4 DB4 DB4 DB4 DB4 DB3 DB3 DB3 DB3 DB3 DB3 DB2 DB2 DB2 DB2 DB2 DB2 DB DB DB DB DB DB DB DB DB DB DB DB Function Set. PD=, V=, select extended instruction set (H= mode). Set charge pump range HIGH. PRS= Set V OP. V OP is set to 7.6V Function Set. PD=, V=, select normal instruction set (H= mode). Display Control. Set normal mode (D=, E=). Data Write. Y,X are initialized to by default, so they aren t set here... 8 D/C DB7 DB6 DB5 DB4 DB3 DB2 DB DB Data Write. 9 D/C DB7 DB6 DB5 DB4 DB3 DB2 DB DB Data Write. D/C DB7 DB6 DB5 DB4 DB3 DB2 DB DB Data Write. D/C DB7 DB6 DB5 DB4 DB3 DB2 DB DB Data Write. 2 D/C DB7 DB6 DB5 DB4 DB3 DB2 DB DB Data Write. 3 D/C DB7 DB6 DB5 DB4 DB3 DB2 DB DB Data Write. November 9, 2 25

26 65 x 2 pixels matrix LCD driver PCF882/2 STEP SERIAL BUS BYTE DISPLAY OPERATION 4 D/C DB7 DB6 DB5 DB4 DB3 DB2 DB DB Display Control. Set inverse video mode (D=, E=). 5 D/C DB7 DB6 DB5 DB4 DB3 DB2 DB DB Set X address of RAM. Set address to. 6 D/C DB7 DB6 DB5 DB4 DB3 DB2 DB DB Data Write. The pinning of the PCF882 is optimized for single plane wiring e.g. for chip-on-glass display modules. Display size: 65x2 pixels. DISPLAY 2x VDD VDD3 VDD2 PCF882 VSS2 VSS VLCDIN VLCDOUT VLCDSENSE Res_b 4* I/O C VLCD V DD C VDD V SS Reset *5 if external oscillator. Fig.7 Application diagram: Internal charge pump is used and a single V DD November 9, 2 26

27 65 x 2 pixels matrix LCD driver PCF882/2 DISPLAY 2x VDD VDD3 VDD2 PCF882 VSS2 VSS VLCDIN VLCDOUT VLCDSENSE Res_b 4* I/O C VLCD V DD2 C VDD2 Reset V DD C VDD V SS *5 if external oscillator Fig.8 Application diagram: Internal charge pump is used and two separate V DD (V DD and V DD2 ) DISPLAY 2x VDD VDD3 VDD2 PCF882 VSS2 VSS VLCDIN VLCDOUT VLCDSENSE Res_b 4* I/O VDD C VDD V SS V LCDIN Reset *5 if external oscillator Fig.9 Application diagram: External high voltage generation is used November 9, 2 27

28 65 x 2 pixels matrix LCD driver PCF882/2 The required minimum value for the external capacitors in an application with the PCF882 are: C VLCD = min. nf C VDD, C VDD, C VDD2 = min. uf Higher capacitor values are recommended for ripple reduction. 8 CHIP INFORMATION The PCF882/2 is manufactured in n-well CMOS technology. The substrate is on V SS potential. 9 PADS INFORMATION Pad pitch 63 µm Pad size, 56x9 µm aluminium. Bump dimensions 42 x 8x 5 (+/- 3) µm Wafer thickness, max. 43 µm including bumps Wafer thickness, without bumps typ. 38 µm November 9, 2 28

29 65 x 2 pixels matrix LCD driver PCF882/2 DummyBump Alignment Mark ROW33 ROW5 COL PC882-2 DummyBump ROW5 ROW64 Alignment Mark DummyBump VDD VDD3 VDD2 COL76 OSC SDIN DC_B SCEB T2 SCLK COL5 (,) Y VSS2 X VSS T COL25 T5 T4 VSS T3 VLCDIN VLCDOUT COL ROW8 Pad No. VLCDSENSE RES_B Alignment Mark ROW32 The alignment marks are circular with a diameter of 8um Max chip size:.92mm x 9,84mm ROW Alignment Mark DummyBump ROW9 DummyBump November 9, 2 29

30 65 x 2 pixels matrix LCD driver PCF882/2 Table 7 Pad locations (dimensions in µm). All x/y coordinates are referenced to centre of chip. PAD x (um) y (um) PAD NAME RES_B ROW ROW ROW ROW ROW ROW ROW ROW ROW ROW ROW ROW ROW ROW dummy pad dummy pad ROW ROW ROW ROW ROW ROW ROW ROW ROW ROW ROW ROW ROW ROW ROW ROW ROW ROW ROW COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL42 November 9, 2 3

31 65 x 2 pixels matrix LCD driver PCF882/ COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL COL ROW ROW ROW ROW ROW ROW ROW ROW ROW ROW ROW ROW ROW ROW ROW ROW ROW ROW dummy pad dummy pad ROW ROW ROW ROW ROW55 November 9, 2 3

32 65 x 2 pixels matrix LCD driver PCF882/ ROW ROW ROW ROW ROW ROW ROW ROW ROW dummy pad VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD OSC SDIN DC_B SCE_B T SCLK VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS T T T VSS VSS T VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDOUT VLCDSENSE X(UM) Y(UM) Alignment Mark Alignment Mark Alignment Mark Alignment Mark 4 November 9, 2 32

33 65 x 2 pixels matrix LCD driver PCF882/2 2 DEVICE PROTECTION DIAGRAM V DD V DD3 V LCDIN V LCDOUT V LCDSENSE V SS V DD V DD2 T3, T2 V SS V SS2 V SS V SS2 V SS V SS V SS2 COL - / ROW - 64 VLCDIN PER BLOCK V DD SDIN SCLK SCE_B DC_B OSC RES_B T, T4, T5 VSS VSS V SS Fig.2 Device Protection Diagram November 9, 2 33

34 65 x 2 pixels matrix LCD driver PCF882/2 2 TRAY INFORMATION X G A C Y H, 2, 3,,2 2,2,3 x, B D F,y x,y A E A L K M J Section A-A Fig.22 Tray details. DIMENSIONS PC882 The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram for the orientating and position of the type name on the die surface. Fig.23 Tray alignment. DIM. DESCRIPTION VALUE A Pocket pitch, x direction 3.97 mm B Pocket pitch, y direction 4.6 mm C Pocket width, x direction 9.94 mm D Pocket width, y direction 2.2 mm E Tray width, x direction 5.8 mm F Tray width, y direction 5.8 mm G Distance from cut corner to pocket (,) centre.43 mm H Distance from cut corner to pocket (,) centre 5.8 mm J Tray thickness 3.96 mm K Tray cross section.78 mm L Tray cross section 2.49 mm M Pocket depth.89 mm x No. pockets in X direction 3 y No. pockets in Y direction November 9, 2 34

35 65 x 2 pixels matrix LCD driver PCF882/2 22 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Application information Where application information is given, it is advisory and does not form part of the specification. 23 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. November 9, 2 35