Revision History Revision No. History Draft Date Remark Editor.0 Initial issue. - 2Gb NAND Flash W-die_ Ver.0 - Gb Mobile DDR F-die_ Ver.0 Oct. 2, 200

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1 Rev..0, Oct. 200 K522HHACF-B050 MCP Specification 2Gb (28M x6) NAND Flash + Gb (64M x6 ) Mobile DDR SDRAM datasheet SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. c 200 Samsung Electronics Co., Ltd. All rights reserved. - -

2 Revision History Revision No. History Draft Date Remark Editor.0 Initial issue. - 2Gb NAND Flash W-die_ Ver.0 - Gb Mobile DDR F-die_ Ver.0 Oct. 2, 200 Final K.N.Kang - 2 -

3 . FEATURES <Common> Operating Temperature : -25 C ~ 85 C Package : 53ball FBGA Type - 8x9x.0mmt, 0.5mm pitch <NAND Flash> Voltage Supply :.7V ~.95V Organization - Memory Cell Array : (256M + 8M) x 8bit for 2Gb (52M + 6M) x 8bit for 4Gb DDP - Data Register : (2K + 64) x 8bit Automatic Program and Erase - Page Program : (2K + 64)Byte - Block Erase : (28K + 4K)Byte Page Read Operation - Page Size : (2K + 64)Byte - Random Read : 40μs(Max.) - Serial Access : 42ns(Min.) Fast Write Cycle Time - Page Program time : 250μs(Typ.) - Block Erase Time : 2ms(Typ.) Command/Address/Data Multiplexed I/O Port Hardware Data Protection - Program/Erase Lockout During Power Transitions Reliable CMOS Floating-Gate Technology -Endurance : 00K Program/Erase Cycles with bit/52byte ECC for x8, Command Driven Operation Unique ID for Copyright Protection <Mobile DDR SDRAM> VDD/VDDQ =.8V/.8V Double-data-rate architecture; two data transfers per clock cycle. Bidirectional data strobe (DQS). Four banks operation. Differential clock inputs ( and ). MRS cycle with address key programs. - CAS Latency (2, 3) - Burst Length (2, 4, 8, 6) - Burst Type (Sequential & Interleave) EMRS cycle with address key programs. - Partial Array Self Refresh (Full, /2, /4 Array) - Output Driver Strength Control (Full, /2, /4, /8, 3/4, 3/8, 5/8, 7/8) Internal Temperature Compensated Self Refresh. All inputs except data & DM are sampled at the positive going edge of the system clock (). Data I/O transactions on both edges of data strobe, DM for masking. Edge aligned data output, center aligned data input. No DLL; to DQS is not synchronized. DM for write masking only. Auto refresh duty cycle us for -25 to 85 C Clock stop capability. Operating Frequency ) CAS Latency ) DDR MHz Address configuration Organization Bank Row Column 64Mx6 BA0,BA A0 - A3 A0 - A9 - DM is internally loaded to match DQ and DQS identically

4 2. GENERAL DESCRIPTION The K522HHACF is a Multi Chip Package Memory which combines 2G bit NAND Flash and G bit Mobile DDR synchronous Dynamic RAM. NAND cell provides the most cost-effective solution for the solid state application market. A program operation can be performed in typical 250μs on the (2K+64)Byte page and an erase operation can be performed in typical 2ms on a (28K+4K)Byte block. Data in the data register can be read out at 42ns cycle time per Byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the device s extended reliability of 00K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The device is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility. In Gbit Mobile DDR, Synchronous design make a device controlled precisely with the use of system clock. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. The K522HHACF is suitable for use in data memory of mobile communication system to reduce not only mount area but also power consumption. This device is available in 53-ball FBGA Type

5 3. PIN CONFIGURATION A DNU DNU NC VSSn VCCn VSSQd VDDQd VDDQd VSSQd VSSd VDDd VSSQd DNU DNU B DNU VSSn /REn CLEn /WPn /WEn NC NC NC DQ2d NC NC VDDQd DNU C VSSd NC /WEd ALEn /CEn R/Bn DQ4d DQ8d DQ3d NC NC DQ9d UDMd VDDQd D VDDd /CSd BA0d Index NC NC VSSQd E NC /RASd A2d - VCCn NC NC NC NC NC - NC DQ5d UDQSd F /CASd A2d A0d - NC NC - DQd DQ0d VSSQd G Ed A9d BAd - VSSn NC - VDDd VDDQd d H VDDd Ad A7d - IO8n IO5n - VSSd VDDQd /d J A4d VSSd A5d - IO9n IO4n - LDQSd NC VSSQd K A6d A0d A3d - IO0n IOn VCCn VSSn IO2n IO3n - DQ2d LDMd DQ4d L A3d A8d Ad DQ5d DQ7d VSSQd M VSSd VDDd NC IO5n IO2n IO0n DQ6d DQ3d NC NC NC NC DQ0d VDDQd N DNU VCCn NC IO6n IO3n VSSQd NC DQd NC NC NC NC VDDQd DNU P DNU DNU VSSn IO7n IO4n IOn VDDQd VDDQd VSSQd VSSd VDDd VSSQd DNU DNU 53 FBGA: Top View (Ball Down) NAND Flash Mobile DRAM Power Ground NC/DNU - 5 -

6 4. PIN DESCRIPTION Pin Name Pin Function(NAND Flash) Pin Name Pin Function(Mobile DDR) IO0n ~ IO5n Data Input/Output d, /d System Clock & Differential Clock R/Bn Ready/Busy Output Ed Clock Enable /REn Read Enable /CSd Chip Select /WEn Write Enable /RASd Row Address Strobe ALEn Address Latch Enable /CASd Column Address Strobe /WPn Write Protection /WEd Write Enable /CEn Chip Enable A0d ~ A3d Address Input CLEn Command Latch Enable BA0d ~ BAd Bank Select Address VCCn Power Supply LDMd,UDMd Lower / Upper Input Data Mask VSSn Ground LDQSd, UDQSd Lower / Upper Data Strobe DQ0d ~ DQ5d Data Input/Output VDDd Power Supply Pin Name Pin Function VDDQd Data Out Power DNU Do Not Use VSSd Ground NC No Connected VSSQd DQ Ground - 6 -

7 5. ORDERING INFORMATION K 5 2 2H H A C F - B 0 50 Samsung MCP Memory(2chips) Device Type NAND + Mobile DDR SDRAM NAND Density,Organization 2H: 2G, x6 Mobile DDR Density, Organization H: G, x6 Mobile DDR Speed 50 : 400Mbps@CL3 NAND Speed 0: None Package B : FBGA(HF, OSP LF) Version F : 7th Generation Operating Voltage A:.8V /.8V Flash Block Architecture C : Uniform Block - 7 -

8 6. FUNCTIONAL BLO DIAGRAM VCCn VSSn /CEn /REn /WPn /WEn ALEn CLEn R/Bn 2Gb NAND Flash Memory IO0n to IO5n VDDd VDDQd VSSd VSSQd d, /d Ed /CSd /RASd /CASd /WEd A0d ~ A3d BA0d ~ BAd LDMd, UDMd LDQSd, UDQSd Gb Mobile DDR SDRAM DQ0d to DQ5d - 8 -

9 7. PAAGE DIMENSION 53-Ball Fine pitch Ball Grid Array Package (measured in millimeters) Units:millimeters 0.08 MAX 8.00± ± x 3 = A #A INDEX MARK B #A 9.00±0.0 (Datum A) (Datum B) 3.25 A B C D E F G H J K L M N P x 3 = ± ± ±0.0 TOP VIEW ± M A B BOTTOM VIEW - 9 -

10 2Gb (28M x6) NAND Flash W-die - 0 -

11 VCC VSS A2 - A29* Figure. Functional Block Diagram(x8) X-Buffers Latches & Decoders 2,048M + 64M Bit for 2Gb 4,096M + 28M Bit for 4Gb DDP NAND Flash ARRAY A0 - A Y-Buffers Latches & Decoders Data Register & S/A Y-Gating Command Command Register I/O Buffers & Latches VCC VSS CE RE WE Control Logic & High Voltage Generator Global Buffers Output Driver I/0 0 I/0 7 CLE ALE WP Figure 2. Array Organization(x8) Block = 64 Pages (28K + 4K) Byte 2,048 blocks for 2Gb 4,096 blocks for 4Gb DDP 2K Bytes 64 Bytes 8 bit Page = (2K + 64)Bytes Block = (2K + 64)Byte x 64 Pages = (28K + 4K) Bytes Device = (2K+64)B x 64Pages x 2,048 Blocks = 2,2 Mbits for 2Gb Device = (2K+64)B x 64Pages x 4,096 Blocks = 4,224 Mbits for 4Gb DDP Page Register 2K Bytes 64 Bytes I/O 0 ~ I/O 7 Column Address : Starting Address of the Register. * L must be set to "Low". * The device ignores any additional input of address cycles than required. * A29 is Row address for 4G DDP. In case of 2G Mono, A29 must be set to "Low" [Table ] Array address : (x8) I/O I/O 0 I/O I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 Address st Cycle A 0 A A 2 A 3 A 4 A 5 A 6 A 7 Column Address 2nd Cycle A 8 A 9 A 0 A *L *L *L *L Column Address 3rd Cycle A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 Row Address 4th Cycle A 20 A 2 A 22 A 23 A 24 A 25 A 26 A 27 Row Address 5th Cycle A 28 *A 29 *L *L *L *L *L *L Row Address - -

12 VCC VSS A - A28* Figure 3. unctional Block Diagram(x6) X-Buffers Latches & Decoders 2,048M + 64M Bit for 2Gb 4,096M + 28M Bit for 4Gb DDP NAND Flash ARRAY A0 - A0 Y-Buffers Latches & Decoders Data Register & S/A Y-Gating Command Command Register I/O Buffers & Latches VCC VSS CE RE WE Control Logic & High Voltage Generator Global Buffers Output Driver I/0 0 I/0 5 CLE ALE WP Figure 4. Figure 2-2. Array Organization(x6) Block = 64 Pages (64K + 2K)Word 2,048 blocks for 2Gb 4,096 blocks for 4Gb DDP K Words 32 Words 6 bit Page = (K + 32)Word Block = (K + 32)Word x 64 Pages = (64K + 2K)Words Device = (K + 32)Word x 64Pages x 2,048 Blocks = 2,2 Mbits for 2Gb Device = (K + 32)Word x 64Pages x 4,096 Blocks = 4,224 Mbits for 4Gb DDP Page Register K Words Column Address : Starting Address of the Register. * L must be set to "Low". * The device ignores any additional input of address cycles than required. * A28 is Row address for 4G DDP. In case of 2G Mono, A28 must be set to "Low" 32 Words I/O 0 ~ I/O 5 [Table 2] Array address : (x6) I/O I/O 0 I/O I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8~I/O 5 Address st Cycle A 0 A A 2 A 3 A 4 A5 A 6 A 7 *L Column Address 2nd Cycle A 8 A 9 A 0 *L *L *L *L *L *L Column Address 3rd Cycle A A 2 A 3 A 4 A 5 A6 A 7 A 8 *L Row Address 4th Cycle A 9 A 20 A 2 A 22 A 23 A24 A 25 A 26 *L Row Address 5th Cycle A 27 *A 28 *L *L *L *L *L *L *L Row Address - 2 -

13 .0 Product Introduction NAND Flash Memory has addresses multiplexed into 8 I/Os(x6 device case : lower 8 I/Os). This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase operation, however, only the three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 3 defines the specific commands of the device. In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another page without need for transporting the data to and from the external buffer memory. Since the time-consuming serial access and data-input cycles are removed, system performance for solid-state disk application is significantly increased. [Table 3] Command Sets Function st Cycle 2nd Cycle Acceptable Command during Busy Read 00h 30h Read ID 90h - Read for Copy Back 00h 35h Reset FFh - O Page Program 80h 0h Copy-Back Program 85h 0h Block Erase 60h D0h Random Data Input ) 85h - Random Data Output ) 05h E0h Read Status 70h - O ) Random Data Input/Output can be executed in a page. Caution : Any undefined command inputs are prohibited except for above command set of Table

14 . ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Voltage on any pin relative to V SS V IN -0.6 to V CC -0.6 to ) Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. V I/O -0.6 to Vcc (< 2.45V) Temperature Under Bias T BIAS -30 to +25 C Storage Temperature T STG -65 to +50 C Short Circuit Current I OS 5 ma V.2 RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND, TA=-25 to 85 C) Parameter Symbol Min Typ. Max Unit Supply Voltage V CC V Supply Voltage V SS V.3 DC AND OPERATING CHARACTERISTICS (Recommended operating conditions otherwise noted.) Operating Current Parameter Symbol Test Conditions Min Typ Max Unit Page Read with Serial Access I CC t RC =42ns CE=V IL, I OUT =0mA Program I CC2 - - Erase I CC Stand-by Current(TTL) I SB 2Gb,CE=V IH, WP=0V/V CC - - 4Gb DDP,CE=V IH, WP=0V/V CC ma 2Gb,CE=V CC -0.2, WP=0V/V CC Stand-by Current(CMOS) I SB2 4Gb DDP,CE=V CC -0.2, WP=0V/V CC Input Leakage Current I LI V IN =0 to V cc (max) - - ±0 Output Leakage Current I LO V OUT =0 to V cc (max) - - ±0 Input High Voltage ) V IH - 0.8xV CC - V CC +0.3 μa Input Low Voltage, All inputs V IL ) xVcc Output High Voltage Level V OH I OH =-00μA V CC Output Low Voltage Level V OL I OL =00uA Output Low Current(R/B) I OL (R/B) V OL =0.V ma ) VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations of 20 ns or less. 2) Typical value is measured at Vcc=.8V, TA=25 C. Not 00% tested. V - 4 -

15 .4 VALID BLO Parameter Symbol Min Typ. Max Unit 2Gb N VB 2,008-2,048 Blocks 4Gb DDP N VB 4,06-4,096 Blocks ) The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of invalid blocks. 2) The st block, which is placed on 00h block address, is guaranteed to be a valid block up to K program/erase cycles with x8 : bit/ 52Byte, x6 : bit/256word ECC. 3) Each mono chip in th device has maximum 40 invalid blocks..5 AC TEST CONDITION (TA=-25 to 85 C, Vcc=.7V~.95V unless otherwise noted) Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load Value 0V to V CC 5ns Vcc/2 TTL GATE and CL=30pF.6 CAPACITANCE(TA=25 C, VCC=.8V, f=.0mhz) Item Symbol Test Condition Min Max Unit Input/Output Capacitance (Mono) C I/O V IL =0V - 0 pf Input Capacitance (Mono) C IN V IN =0V - 0 pf Input/Output Capacitance (DDP) C I/O V IL =0V - 20 pf Input Capacitance (DDP) C IN V IN =0V - 20 pf Capacitance is periodically sampled and not 00% tested..7 MODE SELECTION CLE ALE CE WE RE WP Mode H L L H X Command Input Read Mode L H L H X Address Input(5clock) H L L H H Command Input Write Mode L H L H H Address Input(5clock) L L L H H Data Input L L L H X Data Output X X X X H X During Read(Busy) X X X X X H During Program(Busy) X X X X X H During Erase(Busy) X X () X X X L Write Protect X X H X X 0V/V CC 2) Stand-by ) X can be VIL or VIH. 2) WP should be biased to CMOS high or CMOS low for standby

16 .8 Read / Program / Erase Characteristics Parameter Symbol Min Typ Max Unit Read Time (Data Transfer from Cell to Register) tr μs Program Time tprog μs Number of Partial Program Cycles in the Same Page Nop cycles Block Erase Time tbers ms ) Typical program time is defined as the time within which more than 50% of the whole pages are programmed at.8v Vcc and 25 C temperature..9 AC Timing Characteristics for Command / Address / Data Input Parameter Symbol Min Max Unit CLE Setup Time t CLS ) 2 - ns CLE Hold Time t CLH 5 - ns CE Setup Time t CS ) 2 - ns CE Hold Time t CH 5 - ns WE Pulse Width t WP 2 - ns ALE Setup Time t ALS ) 2 - ns ALE Hold Time t ALH 5 - ns Data Setup Time t DS ) 20 - ns Data Hold Time tdh 5 - ns Write Cycle Time t WC 40 - ns WE High Hold Time t WH 0 - ns Address to Data Loading Time t ADL 2) 00 - ns ) The transition of the corresponding control pins must occur only once while WE is held low 2) tadl is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle - 6 -

17 .0 AC Characteristics for Operation Parameter Symbol Min Max Unit ALE to RE Delay t AR 0 - ns CLE to RE Delay t CLR 0 - ns Ready to RE Low t RR 20 - ns RE Pulse Width t RP 2 - ns WE High to Busy t WB - 00 ns WP Low to WE Low (disable mode) WP High to WE Low (enable mode) ) If reset command(ffh) is written at Ready state, the device goes into Busy for maximum 5μs. t WW 00 - ns Read Cycle Time t RC 42 - ns RE Access Time t REA - 30 ns CE Access Time t CEA - 35 ns RE High to Output t RHZ - 00 ns CE High to Output t CHZ - 30 ns CE High to ALE or CLE Don t Care t CSD 0 - ns RE High to Output Hold t ROH 5 - ns CE High to Output Hold t COH 5 - ns RE High Hold Time t REH 0 - ns Output to RE Low t IR 0 - ns RE High to WE Low t RHW 00 - ns WE High to RE Low t WHR 60 - ns Device Resetting Time(Read/Program/Erase) t RST - 5/0/500 () μs - 7 -

18 2.0 NAND Flash Technical Notes 2. Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The st block, which is placed on 00h block address, is guaranteed to be a valid block up to K program/erase cycles with x8:bit/ 52Byte, x6:bit/256word ECC. 2.2 Identifying Initial Invalid Block(s) All device locations are erased(ffh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s) status is defined by the st byte(st word) in the spare area. Samsung makes sure that either the st or 2nd page of every initial invalid block has non-ffh data at the column address of 2048(x6:024). Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the original initial invalid block information and create the initial invalid block table via the following suggested flow chart(figure 5). Any intentional erasure of the original initial invalid block information is prohibited. Start Set Block Address = 0 Increment Block Address Create (or update) Initial Invalid Block(s) Table No * Check "FFh(x6:FFFFh)" Yes Check "FFh(x6:FFFFh)" at the column address 2048(x6:024) of the st and 2nd page in the block No Last Block? Yes End Figure 5. Flow chart to create initial invalid block table - 8 -

19 NAND Flash Technical Notes (Continued) 2.3 Error in write or read operation Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data. Block replacement should be done upon erase or program error. Failure Mode Detection and Countermeasure sequence Erase Failure Status Read after Erase --> Block Replacement Write Program Failure Status Read after Program --> Block Replacement Read Up to Bit-Failure Verity ECC -> ECC Correction ECC : Error Correcting Code --> Hamming Code etc. Example) bit correction & 2bit detection A repetitive page read operation on the same block without erase may cause bit errors, which could be accumulated over time and exceed the coverage of ECC. Software scheme such as caching into RAM is recommended. Program Flow Chart Start Write 80h Write Address Write Data Write 0h Read Status Register I/O 6 =? or R/B =? No * Program Error No Yes I/O 0 = 0? Yes Program Completed * : If program operation results in an error, map out the block including the page in error and copy the target data to another block

20 NAND Flash Technical Notes (Continued) Erase Flow Chart Read Flow Chart Start Start Write 60h Write 00h Write Block Address Write Address Write D0h Write 30h Read Status Register Read Data I/O 6 =? or R/B =? No ECC Generation * Erase Error No Yes I/O 0 = 0? Reclaim the Error No Verify ECC Yes Yes Page Read Completed Erase Completed * : If erase operation results in an error, map out the failing block and replace it with another block. Block Replacement st (n-)th nth { Block A an error occurs. (page) Buffer memory of the controller. st (n-)th nth { Block B 2 (page) * Step When an error happens in the nth page of the Block A during erase or program operation. * Step2 Copy the data in the st ~ (n-)th page to the same location of another free block. (Block B ) * Step3 Then, copy the nth page data of the Block A in the buffer memory to the nth page of the Block B. * Step4 Do not erase or program to Block A by creating an invalid block table or other appropriate scheme

21 NAND Flash Technical Notes (Continued) 2.4 Addressing for program operation Within a block, the pages must be programmed consecutively from the LSB(least significant bit) page of the block to the MSB(most significant bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB among the pages to be programmed. Therefore, LSB doesn't need to be page 0. Page 63 (64) Page 63 (64) : : Page 3 (32) Page 3 () : : Page 2 Page Page 0 (3) (2) () Page 2 Page Page 0 (3) (32) (2) Data register Data register From the LSB page to MSB page DATA IN: Data () Data (64) Ex.) Random page program (Prohibition) DATA IN: Data () Data (64) - 2 -

22 2.5 System Interface Using CE don t-care. For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2,2byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of μ-seconds, de-activating CE during the data-loading and serial access would provide significant savings in power consumption. Figure 6. Program Operation with CE don t-care. CLE CE WE ALE CE don t-care I/Ox 80h Address(5Cycles) Data Input Data Input 0h CE tcs tch CE tcea trea WE twp RE I/Ox out Figure 7. Read Operation with CE don t-care. CLE CE RE ALE R/B tr CE don t-care WE I/Ox 00h Address(5Cycle) 30h Data Output(serial access)

23 I/O DATA ADDRESS Device I/Ox Data In/Out Col. Add Col. Add2 Row Add Row Add2 Row Add3 2Gb(x8) I/O 0 ~ I/O 7 ~2,2byte A0~A7 A8~A A2~A9 A20~A27 A28 4Gb DDP(x8) I/O 0 ~ I/O 7 ~4,224byte A0~A7 A8~A A2~A9 A20~A27 A28~A29 2Gb(x6) I/O 0 ~ I/O 5 ~,056Word A0~A7 A8~A0 A~A8 A9~A26 A27 4Gb DDP(x6) I/O 0 ~ I/O 5 ~2,2Word A0~A7 A8~A0 A~A8 A9~A26 A27~A

24 3.0 TIMING DIAGRAMS 3. Command Latch Cycle CLE tcls tclh CE tcs tch WE twp ALE tals talh tds tdh I/Ox Command 3.2 Address Latch Cycle CLE tcls CE tcs twc twc twc twc WE tals twp twh talh twp tals twh talh twp tals twh talh twp tals twh talh tals talh ALE tds tdh tds tdh tds tdh tds tdh tds tdh I/Ox Col. Add Col. Add2 Row Add Row Add2 Row Add3-24 -

25 3.3 Input Data Latch Cycle CLE tclh CE tch ALE twc tals WE twp tds twh tdh twp tds tdh twp tds tdh I/Ox DIN 0 DIN DIN final 3.4 * Serial Access Cycle after Read(CLE=L, WE=H, ALE=L) CE trc trp trea treh trea trea tchz tcoh RE trhz trhz troh I/Ox Dout Dout Dout trr R/B Transition is measured at ±200mV from steady state voltage with load. This parameter is sampled and not 00% tested

26 3.5 Status Read Cycle CLE tcls tclh tclr CE tcs WE twp tch tcea tchz twhr tcoh RE tds tdh tir trea trhz trhoh I/Ox 70h Status Output 3.6 Read Operation tclr CLE CE twc WE twb tar ALE tr trc trhz RE trr I/Ox 00h Col. Add Col. Add2 Row Add Row Add2 Row Add3 30h Dout N Dout N+ Column Address Row Address Dout M R/B Busy

27 3.7 Read Operation(Intercepted by CE) tclr CLE CE tcsd WE ALE twb tar tcoh tchz tr trc RE trr I/Ox 00h Col. Add Col. Add2 Row Add Row Add2 Row Add3 30h Dout N Dout N+ Dout N+2 Column Address Row Address R/B Busy

28 twb Rev Random Data Output In a Page CLE CE WE tar trhw ALE tr trc RE trr I/Ox 00h Col. Add Col. Add2 Row Add Row Add2 Row Add3 30h Dout N Dout N+ 05h Col Add Col Add2 Column Address Row Address Column Address R/B Busy tclr twhr E0h trea Dout M Dout M

29 3.9 Page Program Operation CLE CE twc twc twc WE ALE tadl twb tprog twhr RE Din Din I/Ox 80h Co.l Add Col. Add2 Row Add Row Add2 Row Add3 0h 70h I/O0 N M SerialData Input Command Column Address Row Address up to m Byte Program Read Status Serial Input Command Command R/B I/O0=0 Successful Program I/O0= Error in Program tadl is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle

30 3.0 Page Program Operation with Random Data Input CLE CE twc twc WE ALE twc RE Din Din Din Din I/Ox 80h Col. Add Col. Add2 Row Add Row Add2 Row Add3 N 0h 70h I/O0 M 85h Col. Add Col. Add2 J K Serial Data Input Command Column Address Row Address Serial Input Random Data Program Column Address Read Status Serial Input Input Command Command Command R/B tadl tadl twb tprog twhr ) tadl is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle

31 3. Copy-Back Program Operation with Random Data Input CLE CE twc WE twhr twb tprog ALE twb trc tr RE tadl 00h Col Add Col Add2 Row Add Row Add2 Row Add3 35h Data Data N 85h Col Add Col Add2 Row Add Row Add2 Row Add3 Data Data N 0h 70h I/Ox Column Address Row Address Column Address Row Address Read Status Command I/Ox R/B Copy-Back Data Input Command ) tadl is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle. Busy Busy I/O0=0 Successful Program I/O0= Error in Program - 3 -

32 3.2 Block Erase Operation CLE CE WE twc ALE twb tbers twhr RE I/Ox 60h Row Add Row Add2 Row Add3 D0h 70h I/O 0 Row Address R/B Auto Block Erase Setup Command Erase Command Busy Read Status Command I/O0=0 Successful Erase I/O0= Error in Erase

33 3.3 Read ID Operation CLE CE WE ALE tar RE I/Ox 90h 00h trea ECh Device Code 3rd cyc. 4th cyc. 5th cyc. Read ID Command Address cycle Maker Code Device Code Device Device Code (2nd Cycle) 3rd Cycle 4th Cycle 5th Cycle 2Gb(x8) AAh 00h 5h 44h 4Gb DDP(x8) ACh 0h 5h 48h 2Gb(x6) BAh 00h 55h 44h 4Gb DDP(x6) BCh 0h 55h 48h ID Definition Table 90 ID : Access command = 90H st Byte 2 nd Byte 3 rd Byte 4 th Byte 5 th Byte Maker Code Device Code Internal Chip Number Page Size, Block Size,Redundant Area Size, Organization Plane Number, Plane Size, ECC Level Description

34 3rd ID Data ITEM Description Internal Chip Number Cell Type Number of Simultaneously Programmed Pages Interleave Program Between Multii-Chips Cache Program Level Cell 4 Level Cell 8 Level Cell 6 Level Cell Not supported supported Not supported supported I/O # th ID Data ITEM Description Page Size (without Redundant Area) Block Size (without Redundant Area) Redundant Area Size (Byte/52byte) Organization KB 2KB 4KB 8KB 64KB 28KB 256KB 52KB 8 6 Reserved Reserved X8 X6 Reserved 0 or I/O #

35 5th ID Data ITEM Description ECC level Plane Number Plane Size (without Redundant Area) bit ECC/52Byte 2bit ECC/52Byte 4bit ECC/52Byte Reserved KB 28KB 256KB 52KB Gb 2Gb 4Gb 8Gb Reseved Reserved 0 I/O #

36 4.0 Device Operation 4. PAGE READ Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,2 bytes(,056 Words) of data within the selected page are transferred to the data registers in 40μs(tR) typically. The system controller can detect the completion of this data transfer(tr) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 42ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address. The device may output random data in a page instead of the consecutive sequential data by writing random data output command. The column address of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated multiple times regardless of how many times it is done in a page. Figure 8. Read Operation CLE CE WE ALE R/B RE tr I/Ox 00h Address(5Cycle) 30h Data Output(Serial Access) Col. Add.,2 & Row Add.,2,3 Data Field Spare Field

37 4.2 PAGE PROGRAM Rev..0 The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte(a word) or consecutive byte up to 2,2 bytes(,056 Words), in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for a single page. The addressing should be done in sequential order in a block. A page program cycle consists of a serial data loading period in which up to 2,2 bytes(,056 Words) of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and then serial data loading. The bytes(words) other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page. The Page Program confirm command(0h) initiates the programming process. Writing 0h alone without previously entering the serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(i/o 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/ O 0) may be checked(figure 9). The internal write verify detects only errors for ""s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register. Figure 9. Program & Read Status Operation R/B tprog I/Ox 80h "0" Address & Data Input 0h 70h I/O0 Pass Col. Add.,2 & Row Add.,2,3 "" Data Fail R/B Figure 0. Random Data Input In a Page tprog I/Ox 80h "0" Address & Data Input 85h Address & Data Input 0h 70h I/O0 Pass Col. Add.,2 & Row Add,2,3 Col. Add.,2 "" Data Data Fail

38 4.3 COPY-BA PROGRAM Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page without data re-loading when the bit error is not in data stored. Since the time-consuming re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also needs to be copied to the newly assigned free block. Copy-Back operation is a sequential execution of Read for Copy-Back and of copy-back program with the destination page address. A read operation with "35h" command and the address of the source page moves the whole 2,2 bytes(,056 Words) data into the internal data buffer. A bit error is checked by sequential reading the data output. In the case where there is no bit error, the data do not need to be reloaded. Therefore Copy-Back program operation is initiated by issuing Page-Copy Data-Input command (85h) with destination page address. Actual programming operation begins after Program Confirm command (0h) is issued. Once the program process starts, the Read Status Register command (70h) may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(i/o 6) of the Status Register. When the Copy-Back Program is complete, the Write Status Bit(I/O 0) may be checked(figure & Figure 2). The command register remains in Read Status command mode until another valid command is written to the command register. During copy-back program, data modification is possible using random data input command (85h) as shown in Figure 2. Figure. Page Copy-Back Program Operation R/B tr tprog I/Ox 00h "0" Add.(5Cycles) 35h Data Output 85h Add.(5Cycles) 0h 70h I/O0 Pass Col. Add.,2 & Row Add.,2,3 Col. Add.,2 & Row Add.,2,3 Source Address Destination Address "" Fail ) Copy-Back Program operation is allowed only within the same memory plane. Figure 2. Page Copy-Back Program Operation with Random Data Input R/B tr tprog I/Ox 00h Add.(5Cycles) 35h Data Output 85h Add.(5Cycles) Data 85h Add.(2Cycles) Data 0h Col. Add.,2 & Row Add.,2,3 Col. Add.,2 & Row Add.,2,3 Col. Add.,2 Source Address Destination Address There is no limitation for the number of repetition. 70h

39 4.4 BLO ERASE Rev..0 The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only Block address is valid while page address is ignored. The Erase Confirm command(d0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 3 details the sequence. R/B Figure 3. Block Erase Operation tbers I/Ox 60h "0" Address Input(3Cycle) D0h 70h I/O0 Pass Row Add,2,3 Fail "" 4.5 READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/ O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to Table 4 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the read command(00h) should be given before starting read cycles. [Table 4] Status Register Definition for 70h Command I/O Page Program Block Erase Read Definition I/O 0 Pass/Fail Pass/Fail Not Use Pass : "0" Fail : "" I/O Not use Not use Not use Don t -cared I/O 2 Not use Not use Not use Don t -cared I/O 3 Not Use Not Use Not use Don t -cared I/O 4 Not Use Not Use Not Use Don t -cared I/O 5 Not Use Not Use Not Use Don t -cared I/O 6 Ready/Busy Ready/Busy Ready/Busy Busy : "0" Ready : "" I/O 7 Write Protect Write Protect Write Protect Protected : "0" Not Protected : "" ) I/Os defined Not use are recommended to be masked out when Read Status is being executed. 4.6 Read ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Five read cycles sequentially output the manufacturer code(ech), and the device code and 3rd, 4th, 5th cycle ID respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 4 shows the operation sequence

40 Figure 4. Read ID Operation CLE CE tclr tcea WE ALE RE tar twhr I/OX 90h trea Device 00h ECh Code 3rd Cyc. 4th Cyc. 5th Cyc. Address. cycle Maker code Device code Device Device Code (2nd Cycle) 3rd Cycle 4th Cycle 5th Cycle 2Gb(x8) AAh 00h 5h 44h 4Gb DDP(x8) ACh 0h 5h 48h 2Gb(x6) BAh 00h 55h 44h 4Gb DDP(x6) BCh 0h 55h 48h 4.7 RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. If the device is already in reset state a new reset command will be accepted by the command register. The R/B pin changes to low for trst after the Reset command is written. Refer to Figure 5 below. Figure 5. RESET Operation R/B trst I/OX FFh [Table 5] Device Status After Power-up After Reset Operation mode Mode 00h Command is latched Waiting for next command

41 4.8 READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/ B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(r/b) and current drain during busy(ibusy), an appropriate value can be obtained with the following reference chart(fig.7). Its value can be determined by the following guidance. Vcc VCC Rp ibusy Ready Vcc.8V device - VOL : 0.V, VOH : VCC-0.V R/B open drain output VOH C L VOL Busy tf tr GND Device Figure 6. Rp vs tr,tf & Rp vs Vcc =.8V, Ta = 25 C, C L = 30pF tr,tf [s] 200n 00n.70 Ibusy tr 0.43 tf m m Ibusy [A] K 2K 3K 4K Rp(ohm) Rp value guidance Rp(min,.8V part) = VCC(Max.) - VOL(Max.) IOL + ΣIL =.85V 3mA + ΣIL where IL is the sum of the input currents of all devices tied to the R/B pin. Rp(max) is determined by maximum permissible limit of tr - 4 -

42 5.0 DATA PROTECTION & POWER UP SEQUENCE The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about.v. WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 00μs is required before internal circuit gets ready for any command sequences as shown in Figure 7. The two step command sequence for program/erase provides additional software protection. Figure 7. AC Waveforms for Power Transition VCC WP WE Ready/Busy Don t care ~.5V ~.5V 00μs High 5 ms max Operation Invalid Don t care

43 5. WP AC TIMING GUIDE Rev..0 Enabling WP during erase and program busy is prohibited. The erase and program operations are enabled and disabled as follows:. Enable Mode Figure 8. Program Operation WE I/O 80h 0h WP R/B tww(min.00ns) 2. Disable Mode WE I/O 80h 0h WP R/B tww(min.00ns) Figure 9. Erase Operation. Enable Mode WE I/O 60h D0h WP R/B tww(min.00ns) 2. Disable Mode WE I/O 60h D0h WP R/B tww(min.00ns)

44 Gb (64M x6 ) Mobile DDR SDRAM - 4 -

45 .0 FUNCTIONAL BLO DIAGRAM Bank Select, 6 Data Input Register Serial to parallel I/O Control LWE LDM 32 6Mx32, ADD Address Register Refresh Counter Row Buffer LRAS LCBR Row Decoder Col. Buffer 6Mx32 6Mx32 6Mx32 Column Decoder Sense AMP Latency & Burst Length 2-bit prefetch 32 6 Output Buffer DQi X6 LE LRAS LCBR LWE LCAS Programming Register LWCBR Strobe Gen. LDM Data Strobe Timing Register DM Input Register, E CS RAS CAS WE DM - 5 -

46 2.0 FUNCTIONAL DESCRIPTION POWER APPLIED POWER ON PRECHARGE ALL BANKS REFS PARTIAL SELF REFRESH SELF REFRESH REFSX EMRS MRS MRS IDLE ALL BANKS PRECHARGED REFA AUTO REFRESH EL EH ACT POWER DOWN POWER DOWN EH EL ROW ACTIVE BURST STOP WRITE READ WRITEA WRITE WRITEA READA READ READ WRITEA READA READA WRITEA PRE READA PRE PRE PRE PRECHARGE PREALL Automatic Sequence Command Sequence Figure. State diagram - 6 -

47 3.0 MODE REGISTER DEFINITION 3. Mode Register Set (MRS) The mode register is designed to support the various operating modes of Mobile DDR SDRAM. It includes Cas latency, addressing mode, burst length, test mode and vendor specific options to make Mobile DDR SDRAM useful for variety of applications. The mode register is written by asserting low on CS, RAS, CAS and WE (The Mobile DDR SDRAM should be in active mode with E already high prior to writing into the mode register). The states of address pins A0 ~ A3 and BA0, BA in the same cycle as CS, RAS, CAS and WE going low are written in the mode register. Two clock cycles are required to complete the write operation in the mode register. Even if the power-up sequence is finished and some read or write operation is executed afterward, the mode register contents can be changed with the same command and two clock cycles. This command must be issued only when all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, Cas latency (read latency from column address) uses A4 ~ A6, A7 ~ A3 is used for test mode. BA0 and BA must be set to low for proper MRS operation. BA BA0 A3 ~ A0/AP A9 A8 A7 A6 A5 A4 A3 A2 A A0 Address Bus 0 0 RFU ) CAS Latency BT Burst Length Mode Register A3 Burst Type 0 Sequential Interleave A6 A5 A4 CAS Latency Reserved 0 0 Reserved 0 0 Reserved Reserved 0 Reserved 0 Reserved Reserved A2 A A0 Burst Type Reserved Reserved 0 Reserved Reserved ) RFU (Reserved for future use) should stay "0" during MRS cycle. Figure 2. Mode Register Set - 7 -

48 [Table ] Burst address ordering for burst length Burst Length Starting Address (A3, A2, A, A0) Sequential Mode Interleave Mode 2 xxx0 0, 0, xxx, 0, 0 xx00 0,, 2, 3 0,, 2, 3 4 xx0, 2, 3, 0, 0, 3, 2 xx0 2, 3, 0, 2, 3, 0, xx 3, 0,, 2 3, 2,, 0 x000 0,, 2, 3, 4, 5, 6, 7 0,, 2, 3, 4, 5, 6, 7 x00, 2, 3, 4, 5, 6, 7, 0, 0, 3, 2, 5, 4, 7, 6 x00 2, 3, 4, 5, 6, 7, 0, 2, 3, 0,, 6, 7, 4, 5 8 x0 3, 4, 5, 6, 7, 0,, 2 3, 2,, 0, 7, 6, 5, 4 x00 4, 5, 6, 7, 0,, 2, 3 4, 5, 6, 7, 0,, 2, 3 x0 5, 6, 7, 0,, 2, 3, 4 5, 4, 7, 6,, 0, 3, 2 x0 6, 7, 0,, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, x 7, 0,, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2,, ,, 2, 3, 4, 5, 6, 7, 8, 9, 0,, 2, 3, 4,5 0,, 2, 3, 4, 5, 6, 7, 8, 9, 0,, 2, 3, 4,5 000, 2, 3, 4, 5, 6, 7, 8, 9, 0,, 2, 3, 4,5, 0, 0, 3, 2, 5, 4, 7, 6, 9, 8,,0,3,2,5, , 3, 4, 5, 6, 7, 8, 9, 0,, 2, 3, 4,5, 0, 2, 3, 0,, 6, 7, 4, 5,0,, 8, 9, 4,5,2,3 00 3, 4, 5, 6, 7, 8, 9, 0,, 2, 3, 4,5, 0,, 2 3, 2,, 0, 7, 6, 5, 4,,0, 9, 8, 5,4,3, , 5, 6, 7, 8, 9, 0,, 2, 3, 4,5, 0,, 2, 3 4, 5, 6, 7, 0,, 2, 3,2,3,4,5, 8, 9, 0, 00 5, 6, 7,8, 9, 0,, 2, 3, 4,5, 0,, 2, 3, 4 5, 4, 7, 6,, 0, 3, 2,3,2,5,4, 9, 8,,0 00 6, 7, 8, 9, 0,, 2, 3, 4,5, 0,, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0,,4,5,2,3,0,, 8, , 8, 9, 0,, 2, 3, 4,5, 0,, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2,, 0, 5,4,3,2,,0, 9, , 9, 0,, 2, 3, 4,5, 0,, 2, 3, 4, 5, 6, 7 8, 9,0,,2,3,4,5, 0,, 2, 3, 4, 5, 6, , 0,, 2, 3, 4,5, 0,, 2, 3, 4, 5, 6, 7, 8 9, 8,,0,3,2,5,4,, 0, 3, 2, 5, 4, 7, ,, 2, 3, 4, 5, 0,, 2, 3, 4, 5, 6, 7, 8, 9 0,, 8, 9, 4,5,2,3, 2, 3, 0,, 6, 7, 4, 5 0, 2, 3, 4, 5, 0,, 2, 3, 4, 5, 6, 7, 8, 9, 0,0, 9, 8, 5,4,3,2, 3, 2,, 0, 7, 6, 5, , 3, 4, 5, 0,, 2, 3, 4, 5, 6, 7, 8, 9, 0, 2,3,4,5, 8, 9, 0,, 4, 5, 6, 7, 0,, 2, 3 0 3, 4, 5, 0,, 2, 3, 4, 5, 6, 7, 8, 9, 0,,2 3,2,5,4, 9, 8,,0, 5, 4, 7, 6,, 0, 3, 2 0 4, 5, 0,, 2, 3, 4, 5, 6, 7, 8, 9, 0,, 2, 3 4,5,2,3,0,, 8, 9, 6, 7, 4, 5, 2, 3, 0, 5, 0,, 2, 3, 4, 5, 6, 7, 8, 9, 0,, 2, 3, 4 5,4,3,2,,0, 9, 8, 7, 6, 5, 4, 3, 2,, 0-8 -

49 3.2 Extended Mode Register Set (EMRS) The extended mode register is designed to support for the desired operating modes of DDR SDRAM. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA, low on BA0(The Mobile DDR SDRAM should be in all bank precharge with E already high prior to writing into the extended mode register). The state of address pins A0 ~ A3 in the same cycle as CS, RAS, CAS and WE going low is written in the extended mode register. Two clock cycles are required to complete the write operation in the extended mode register. Even if the power-up sequence is finished and some read or write operations is executed afterward, the mode register contents can be changed with the same command and two clock cycles. But this command must be issued only when all banks are in the idle state. A0 - A2 are used for partial array self refresh and A5 - A7 are used for driver strength control. "High" on BA and "Low" on BA0 are used for EMRS. All the other address pins except A0,A,A2,A5,A6,A7, BA, BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. BA BA0 A3 ~ A0/AP A9 A8 A7 A6 A5 A4 A3 A2 A A0 Address Bus 0 RFU ) 0 0 DS RFU ) PASR Mode Register DS A7 A6 A5 Driver Strength Full 0 0 /2 0 0 /4 0 / /4 0 3/8 0 5/8 7/8 PASR A2 A A0 Refreshed Area Full Array 0 0 /2 Array 0 0 /4 Array 0 Reserved 0 0 Reserved 0 Reserved 0 Reserved Reserved Figure 3. Extended Mode Register Set ) RFU (Reserved for future use) should stay "0" during EMRS cycle

50 3.3 Internal Temperature Compensated Self Refresh (TCSR). In order to save power consumption, this Mobile DRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the real device temperature. 2. TCSR ranges for IDD6 shown in the table are only examples. 3. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored. Temperature Range Self Refresh Current (IDD6) Full Array /2 Array /4 Array Unit 85 C C ua ) IDD6 85 C is guaranteed, IDD6 45 C is typical value. 3.4 Partial Array Self Refresh (PASR). In order to save power consumption, Mobile DDR SDRAM includes PASR option. 2. Mobile DDR SDRAM supports three kinds of PASR in self refresh mode; Full array, /2 Array, /4 Array. BA=0 BA0=0 BA=0 BA0= BA=0 BA0=0 BA=0 BA0= BA=0 BA0=0 BA=0 BA0= BA= BA0=0 BA= BA0= BA= BA0=0 BA= BA0= BA= BA0=0 BA= BA0= - Full Array - /2 Array - /4 Array Partial Self Refresh Area Figure 4. EMRS code and TCSR, PASR - 0 -

51 4.0 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to VSS V IN, V OUT ~ 2.7 V Voltage on VDD supply relative to VSS VDD ~ 2.7 V Voltage on VDDQ supply relative to VSS VDDQ ~ 2.7 V Storage temperature T STG - 55 ~ + 50 C Power dissipation P D.0 W Short circuit current I OS 50 ma ) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. 2) Functional operation should be restricted to recommend operation condition. 3) Exposure to higher than recommended voltage for extended periods of time could affect device reliability. 5.0 DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS=0V, T C = -25 C to 85 C) Parameter Symbol Min Max Unit Note Supply voltage (for device with a nominal VDD of.8v) VDD.7.95 V I/O Supply voltage VDDQ.7.95 V Input logic high voltage Input logic low voltage Address V IH (DC) 0.8 x VDDQ VDDQ V Data 0.7 x VDDQ VDDQ V Address V IL (DC) x VDDQ V Data x VDDQ V 2 2 Output logic high voltage V OH (DC) 0.9 x VDDQ - V I OH = - 0.mA Output logic low voltage V OL (DC) - 0. x VDDQ V I OL = 0.mA Input leakage current I I -2 2 ua 3 Output leakage current I OZ -5 5 ua ) Under all conditions, VDDQ must be less than or equal to VDD. 2) These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. 3) Any input 0V VIN VDDQ. Input leakage currents include output leakage for all bi-directional buffers with tri-state outputs. - -

52 6.0 DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, T C = -25 to 85 C) Parameter Symbol Test Condition DDR400 Unit Note Operating Current (One Bank Active) Precharge Standby Current in power-down mode Precharge Standby Current in non power-down mode Active Standby Current in power-down mode Active Standby Current in non power-down mode (One Bank Active) Operating Current (Burst Mode) Refresh Current Self Refresh Current IDD0 IDD2P IDD2PS IDD2N IDD2NS IDD3P IDD3PS IDD3N IDD3NS IDD4R IDD4W IDD5 IDD6 ) IDD5 is measured in the below test condition. Density 28Mb 256Mb 52Mb Gb 2Gb Unit t RFC ns trc=trcmin; t=tmin; E is HIGH; CS is HIGH between valid commands; address inputs are SWITCHING; data bus inputs are STABLE all banks idle, E is LOW; CS is HIGH, t = tmin; address and control inputs are SWITCHING; data bus inputs are STABLE 60 ma all banks idle, E is LOW; CS is HIGH, = LOW, = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 0.5 all banks idle, E is HIGH; CS is HIGH, t = tmin; 8 address and control inputs are SWITCHING; data bus inputs are STABLE ma all banks idle, E is HIGH; CS is HIGH, = LOW, = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 4 one bank active, E is LOW; CS is HIGH, t = tmin; 5 address and control inputs are SWITCHING; data bus inputs are STABLE ma one bank active, E is LOW; CS is HIGH, = LOW, = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 4 one bank active, E is HIGH; CS is HIGH, t = tmin; 2 address and control inputs are SWITCHING; data bus inputs are STABLE ma one bank active, E is HIGH; CS is HIGH, = LOW, = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 0 one bank active; BL=4; CL=3; t = tmin; continuous read bursts; I OUT =0 ma 70 address inputs are SWITCHING; 50% data change each burst transfer ma one bank active; BL = 4; t = tmin; continuous write bursts; address inputs are SWITCHING; 50% data change each burst transfer 50 trc trfc; t = tmin; burst refresh; E is HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 70 ma TCSR Range Values 85 C 900 Full Array E is LOW; t = t min; 45 C 200 ua Extended Mode Register set to all 0 s; 85 C 800 address and control inputs are STABLE; /2 Array data bus inputs are STABLE 45 C 50 ua 5 /4 Array 85 C C 20 ua 2) IDD specifications are tested after the device is properly initialized. 3) Input slew rate is V/ns. 4) Definitions for IDD: LOW is defined as V IN 0. * VDDQ; HIGH is defined as V IN 0.9 * VDDQ; STABLE is defined as inputs stable at a HIGH or LOW level; SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles; - data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE. 5) IDD6 85 C is guaranteed, IDD6 45 C is typical value. 0.5 ma - 2 -