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2 All Programmable Automotive SoC Comparison XA Zynq UltraScale+ MPSoC ZU2/3EG, ZU4/5EV Devices XA Zynq SoC Z-7010/7020/7030 Devices Application Processor Real-Time Processor Quad-core ARM Cortex -A53 MPCore up to 12GHz Dual-core ARM Cortex-R5 MPCore up to 500MHz Dual-core ARM Cortex-A9 MPCore up to 667MHz N/A Graphics Processor External Dynamic Memory Interface Mali -400 MP2 up to 600MHz x32/x64: DDR4, LPDDR4, DDR3, DDR3L, LPDDR3 w/ ECC N/A x16/x32: DDR3L, DDR3, DDR2, LPDDR2 w/ecc (supports 16-bit) Programmable Logic 103K 256K System Logic Cells 28K 125K Logic Cells DSP Slices 240 1, Speed Grades -1, -1L -1 Automotive Standards Power Management Page 2 AEC-Q100, Production Part Approval Process Separate Voltage on PS & PL, Full (PL+PS) / Full power domain / Low power domain / Battery Power Domains (PS) AEC-Q100, Production Part Approval Process Full (PS +PL), Separate Voltage on PS & PL
3 All Programmable Automotive FPGA Comparison XA Artix -7 XA Spartan -7 XA Spartan-6 Core Voltage 10V 10V 12V Logic Cell 12K 101K 6K 102K 3K 74K Total Block RAM (K) 720 4, , ,096 Clock Management Tiles DSP Slices PCIe Gen2 up to x4 0 0 Gen1 x1 GTP Transceivers Speed Grades -1, -2-1, -2-2, -3 Automotive Standards AEC-Q100, Production Part Approval Process AEC-Q100, Production Part Approval Process AEC-Q100, Production Part Approval Process Page 3
4 Programmable Logic (PL) Processing System (PS) XA Zynq UltraScale+ MPSoCs Device Name (1) ZU2EG ZU3EG ZU4EV ZU5EV Application Processor Core Quad-core ARM Cortex -A53 MPCore up to 12GHz Processor Unit Memory w/ecc L1 Cache 32KB I / D per core, L2 Cache 1MB, on-chip Memory 256KB Real-Time Processor Processor Core Dual-core ARM Cortex-R5 MPCore up to 500MHz Unit Memory w/ecc L1 Cache 32KB I / D per core, Tightly Coupled Memory 128KB per core Graphic & Video Graphics Processing Unit Mali -400 MP2 up to 600MHz Acceleration Memory L2 Cache 64KB External Memory Dynamic Memory Interface x32/x64: DDR4, LPDDR4, DDR3, DDR3L, LPDDR3 with ECC Static Memory Interfaces NAND, 2x Quad-SPI Connectivity High-Speed Connectivity PCIe Gen2 x4, 2x USB30, SATA 31, DisplayPort, 4x Tri-mode Gigabit Ethernet General Connectivity 2xUSB 20, 2x SD/SDIO/eMMC, 2x UART, 2x CAN 20B, 2x I2C, 2x SPI, 4x 32b GPIO Power Management Full / Low / PL / Battery Power Domains Integrated Block Security RSA, AES, and SHA Functionality AMS - System Monitor 10-bit, 1MSPS - Temperature, Voltage, and Current Monitor PS to PL Interface 12 x 32/64/128b AXI Ports System Logic Cells (K) Programmable CLB Flip-Flops (K) Functionality CLB LUTs (K) Max Distributed RAM (Mb) Memory Total Block RAM (Mb) UltraRAM (Mb) Clocking Clock Management Tiles (CMTs) DSP Slices ,248 VCU Integrated IP PCI Express Gen 3x16 / Gen4x G Interlaken G Ethernet MAC/PCS w/rs-fec AMS - System Monitor Transceivers GTH 125Gb/s Transceivers Speed Grades I-Grade -1 (085V), -L1 (072V) Q-Grade -1 (085V) Notes: 1 For full part number details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview Page 4
5 XA Zynq UltraScale+ MPSoCs PS I/Os (1), 33V High-Density (HD) I/O, 18V High-Performance (HP) I/Os PS-GTR 6Gb/s, GTH 125Gb/s Pkg Footprint (2) SBVA484 (3) SFVA625 (3) SFVC784 (3) Dimensions (mm) 19x19 21x21 23x23 XAZU2EG XAZU3EG XAZU4EV XAZU5EV 170, 24, 58 4, 0 170, 24, 156 4, 0 214, 96, 156 4, 0 Notes: 1 PS I/O is a combination of PS MIO and PS DDRIO 2 For full part number details, see the Ordering Information section in DS891, Zynq UltraScale+ MPSoC Overview 3 These packages are only offered in 08mm ballpitch 170, 24, 58 4, 0 170, 24, 156 4, 0 214, 96, 156 4, 0 214, 96, 156 4, 4 214, 96, 156 4, 4 Important: Verify all data in this document with the device data sheets found at wwwxilinxcom Page 5
6 Programmable Logic (PL) Processing System (PS) XA Zynq SoCs Device Name (1) XA7Z010 XA7Z020 XA7Z030 Application Processor Core Dual ARM Cortex -A9 MPCore up to 667MHz Processor Unit Processor Extension NEON SIMD Engine and Single/Double Precision Floating Point Unit per Processor L1 Cache 32KB I / D per Core Memory L2 Cache 512KB On-Chip Memory 256KB Dynamic Memory Interface x32/x64: DDR3, DDR3L, DDR2, LPDDR2 External Memory Static Memory Interfaces NAND, NOR, 2x Quad-SPI Connectivity High-Speed Connectivity 2x Tri-mode Gigabit Ethernet General Connectivity 2xUSB 20, 2x SD/SDIO/eMMC, 2x UART, 2x CAN 20B, 2x I2C, 2x SPI, 4x 32b GPIO Integrated Block Security RSA, AES, and SHA Functionality AMS - System Monitor 2x12-bit, 1MSPS - Temperature, Voltage, and Current Monitor PS to PL Interface 9 x 32/64 AXI Ports Xilinx 7 Series PL Equivalent Artix-7 Artix-7 Kintex-7 Programmable Logic Cells 28,160 85, ,760 Functionality CLB Flip-Flops 35, , ,200 CLB LUTs 17,600 53,300 78,600 Memory Total Block RAM (KB) ,060 (# 36 Kb Blocks) (60) (140) (265) DSP Slices Integrated IP Peak DSP Performance 100 GMACs 276 GMACs 593 GMACs PCI Express - - Gen2 x4 AMS / XADC Notes: 1 All packages listed are Pb-free 2 HR = High Range I/O with support for I/O voltage from 12V up to 33V 3 HP = High Performance I/O with support for I/O voltage from 12V to 18V 4 PS I/O includes user I/O and DDR I/O Page 6 AES and SHA 256b Decryption and Authentication for Secure Programmable Configuration Speed Grades I-Grade -1 Q-Grade -1 (1) Size (mm) Pitch (mm) HR I/O (2), HP I/O (3), PS I/O (4), GTX Transceiver CLG225 13x , 0, 84, 0 CLG400 17x , 0, 128, 0 125, 0, 128, 0 CLG484 19x , 0, 128, 0 FBV484 23x , 63, 128, 4
7 XA Artix -7 FPGAs Transceiver Optimization at the Lowest Cost and Highest DSP Bandwidth (10V, 095V, 09V) Part Number XA7A12T XA7A15T XA7A25T XA7A35T XA7A50T XA7A75T XA7A100T Logic Cells 12,800 16,640 23,360 33,280 52,160 75, ,440 Logic Slices 2,000 2,600 3,650 5,200 8,150 11,800 15,850 Resources CLB Flip-Flops 16,000 20,800 29,200 41,600 65,200 94, ,800 Maximum Distributed RAM (Kb) ,188 Memory Block RAM/FIFO w/ ECC (36 Kb each) Resources Total Block RAM (Kb) ,620 1,800 2,700 3,780 4,860 Clock Resources CMTs (1 MMCM + 1 PLL) I/O Resources Maximum Single-Ended I/O Maximum Differential I/O Pairs DSP Slices Embedded PCIe Gen2 (1) Hard IP Analog Mixed Signal (AMS) / XADC Resources Configuration AES / HMAC Blocks GTP Transceivers (625Gb/s Max Rate) (2) Speed Grades I-Grade -1, -2-1, -2-1, -2-1, -2-1, -2-1, -2-1, -2 Q-Grade (3) Dimensions Ball Pitch (mm) (mm) Available User I/O: 33V SelectIO HR I/O (GTP Transceivers) CPG x (2) 106 (2) 106 (2) 106 (2) 106 (2) CSG x (0) 210 (0) 210 (0) 210 (0) 210 (0) CSG x (2) 150 (4) 150 (4) 150 (4) 150 (4) FGG x (4) 250 (4) 250 (4) 285 (4) 285 (4) Notes: 1 Supports PCI Express Base 21 specification at Gen1 and Gen2 data rates 2 Represents the maximum number of transceivers available Note that the CSG324 devices are available without transceivers See the section of this table for details 3 Device migration is available within the Artix-7 family for like packages but is not supported between other 7 series families Page 7
8 XA Spartan -7 FPGAs I/O Optimization at the Lowest Cost and Highest Performance-per-Watt (10V) Part Number XA7S6 XA7S15 XA7S25 XA7S50 XA7S75 XA7S100 Logic Cells 6,000 12,800 23,360 52,160 76, ,400 Slices 938 2,000 3,650 8,151 12,000 16,000 CLB Flip-Flops 7,500 16,000 29,200 65,200 96, ,000 Max Distributed RAM (Kb) ,100 Block RAM/FIFO w/ ECC (36Kb each) Total Block RAM (Kb) ,620 2,700 3,240 4,320 Clock Mgmt Tiles (1 MMCM + 1 PLL) Max Single-Ended I/O Pins Max Differential I/O Pairs DSP Slices Analog Mixed Signal (AMS) / XADC Configuration AES / HMAC Blocks I-Grade -1,-2-1,-2-1,-2-1,-2-1,-2-1,-2 Q-Grade Dimensions Ball Pitch (mm) (mm) Available User I/O: 33V SelectIO HR I/O CPGA196 8x CSGA225 13x CSGA324 15x FTGB196 15x FGGA484 23x FGGA676 27x Page 8
9 XA Spartan -6 FPGAs Transceiver Optimization at the Lowest Cost (12V) Part Number XA6SLX4 XA6SLX9 XA6SLX16 XA6SLX25 XA6SLX45 XA6SLX75 XA6SLX100 XA6SLX25T XA6SLX45T XA6SLX75T Logic Cells 3,840 9,152 14,579 24,051 43,661 74, ,262 24,051 43,661 74,637 Logic Slices 600 1,430 2,278 3,758 6,822 11,662 15,822 3,758 6,822 11,662 Resources CLB Flip-Flops 4,800 11,440 18,224 30,064 54,576 93, ,576 30,064 54,576 93,296 Maximum Distributed RAM (Kb) Memory Block RAM (18Kb ea) Resources Total Block RAM (Kb) ,088 3,096 4, ,088 3,096 Clock Resources CMTs (2 DCM + 1 PLL) Memory Controller Blocks (Max) Embedded Endpoint Blocks PCIe Hard IP GTP Transceivers (32Gb/s Max Rate) Resources Total I/O Banks Max User I/O Speed Grades I-Grade -2, -3 Q-Grade -2, -3 Dimensions Ball Pitch (mm) (mm) Available User I/O: 33V SelectIO HR I/O (GTP Transceivers) CSG x (0) 160 (0) 160 (0) FTG x (0) 186 (0) 186 (0) CSG x (0) 232 (0) 226 (0) 218 (0) 190 (2) 190 (4) CSG x (0) 328 (0) FGG x (0) 316 (0) 280 (0) 326 (0) 250 (2) 296 (4) 268 (4) Page 9
10 Device Ordering Information XA ZU # E G -1 S B V A 484 I Xilinx Generation Automotive Value Index Processor System E: Dual RPU Quad APU Single GPU Engine Type G: General Purpose V: Video Speed Grade S: Flip-Chip -1 = Standard (8mm) -1L = Low Power F: Lid B: Lidless V: RoHS 6/6 Designator Pin Count Temperature Grade (I, Q) XA 7 Z ### -1 FB V 484 Q Xilinx Generation Automotive Family Value Index Speed Grade -1 = Standard CL: Wire-bond (8 mm) FB: Flip-Chip (1 mm) V: RoHS 6/6 G: RoHS 6/6 Pin Count Temperature Grade (I, Q) XA 7 S ### -1 FG G A 484 Q Xilinx Generation Automotive Family Logic Cells in 1K Units Speed Grade CP: Wire-bond (5 mm) -1 = Standard FT: Wire-bond (1mm) -2 = Medium CS: Wire-bond (8 mm) FG: Wire-bond (1 mm) G: RoHS 6/6 Designator Pin Count Temperature Grade (I, Q) XA 7 A ### -1 CP G 236 I Xilinx Generation Automotive Family Logic Cells In 1K units Speed Grade -1 = Standard -2 = Medium CP: Wire-bond (5mm) CS: Wire-bond (8mm) FG: Wire-bond (1mm) G: RoHS 6/6 Pin Count Temperature Grade (I, Q) XA 6 S Xilinx Generation Automotive I = Tj from 40 C to +100 C ; Q = Tj from 40 C to +125 C LX LXT ### Family Sub-families Logic Cells LX: Logic in 1K Units LXT: Logic + Transceivers -1 FG Speed Grade -2 = Mid -3 = Highest CS: Wire-bond (8 mm) FT: Wire-bond (1mm) FG: Wire-bond (1 mm) G G: RoHS 6/6 484 Pin Count Important: Verify all data in this document with the device data sheets found at wwwxilinxcom Q Temperature Grade (I, Q) Page 10
11 External Memory Controller Maximum Bandwidth (Mb/s) XA Zynq UltraScale+ XA Zynq-7000 XA Spartan -7 XA Artix -7 XA Spartan-6 Core Voltage -1I/Q (085V) -L1 (072V) -1I (10V) -1Q (10V) -1I (1V) -1Q (1V) -2I (1V) -1I (10V) -1Q (10V) -2I (10V) -2, -3 (12V) PL PS PL PS PL PS PL PS DDR DDR DDR3L N/A 800 DDR DDR LPDDR LPDDR LPDDR LPDDR 400 Important: Verify all data in this document with the device data sheets found at wwwxilinxcom Page 11
12 Internal Memory Block RAM Metrics Zynq UltraScale+ (Kb) XAZU2EG 5,300 XAZU3EG XAZU4EV 4,500 XAZU5EV 5,100 7,600 Block RAM UltraRAM Zynq-7000 (Kb) Spartan-7 (Kb) Artix-7 (Kb) XA7Z010 XA7Z020 XA7Z030 XA7A12T XA7A15T XA7A25T XA7A35T XA7A50T XA7A75T XA7A100T ,060 XA7S6 XA7S XA7S25 1,620 XA7S50 2,700 XA7S75 3,240 XA7S100 4, ,620 1,800 2,700 3,780 4,860 XA Zynq UltraScale+ Speed grade -1-1L True dual-port Block RAM F MAX [MHz] UltraRAM F MAX [MHz] XA Zynq-7000 Speed grade -1 True dual-port Block RAM F MAX [MHz] 458 XA Spartan-7 FPGAs Speed grade -1-2 True dual-port Block RAM F MAX [MHz] XA Artix-7 FPGAs Speed grade -1-2 True dual-port Block RAM F MAX [MHz] Spartan-6 (Kb) XA6SLX4 XA6SLX6 XA6SLX16 XA6SLX25 XA6SLX45 XA6SLX75 XA6SLX100 XA6SLX25T XA6SLX45T XA6SLX75T ,088 2,088 3,096 3,096 4,824 XA Spartan-6 FPGAs Speed grade -2-3 True dual-port Block RAM F MAX [MHz] Page 12
13 Digital Signal Processing Metrics XAZU2EG 240 XAZU3EG 360 XAZU4EV XAZU5EV 1,056 XA7Z010 XA7Z020 XA7Z030 XA7A12T XA7A15T XA7A25T XA7A35T XA7A50T XA7A75T XA7A100T XA6SLX4 XA6SLX6 XA6SLX16 XA6SLX25 XA6SLX45 XA6SLX75 XA6SLX100 XA6SLX25T XA6SLX45T XA6SLX75T 80 XA7S6 10 XA7S15 XA7S25 XA7S XA7S XA7S XA Zynq UltraScale+ MPSoC Speed grade -1-1L F MAX [MHz] Max GMAC/s 1,362 1,267 XA Zynq-7000 SoC Speed grade -1 F MAX [MHz] 547 Max GMAC/s 438 XA Spartan-7 FPGAs Speed grade -1-2 F MAX [MHz] Max GMAC/s XA Artix-7 FPGAs Speed grade -1-2 F MAX [MHz] Max GMAC/s XA Spartan-6 FPGAs Speed Grade -2-3 F MAX [MHz] Max GMAC/s (LX75) Page 13
14 References DS894, XA Zynq UltraScale+ MPSoC Data Sheet: Overview DS925, Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics DS180, 7 Series FPGAs Data Sheet: Overview DS197, XA Artix-7 FPGAs Data Sheet: Overview DS181, Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS188, XA Zynq-7000 All Programmable SoC Data Sheet: Overview DS187, Zynq-7000 SoC Data Sheet: DC and AC Switching Characteristics DS189, Spartan-7 FPGAs Data Sheet: DC and AC Switching Characteristics DS170, XA Spartan-6 Automotive FPGA Family Data Sheet: Overview DS162, Spartan-6 FPGAs Data Sheet: DC and AC Switching Characteristics UG1085, Zynq UltraScale+ MPSoC Technical Reference Manual UG1213, Zynq Migration Guide Zynq-7000 AP SoC to Zynq UltraScale+ MPSoC Devices For more information on Automotive products, go to XMP106 (v11) Page 14 Important: Verify all data in this document with the device data sheets found at wwwxilinxcom, Inc Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license All other trademarks are the property of their respective owners
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