Novel Methodology for Mid-Frequency Delta-I Noise Analysis of Complex Computer System Boards and Verification by Measurements

Transcription

1 Novel Methodology for Mid-Frequency Delta-I Noise Analysis of Complex Computer System Boards and Verification by Measurements Bernd Garben IBM Laboratory, 7032 Boeblingen, Germany, and Michael F. McAllister IBM Laboratory, Poughkeepsie, NY EPEP 2000, Scottsdale, 10/23/00 1 B.Garben, M.McAllister, IBM

2 2. Simulation methodology 3. Simulation results 4. Verification by measurements 5. Summary & conclusions EPEP 2000, Scottsdale, 10/23/00 2 B.Garben, M.McAllister, IBM

3 variations of the on-chip switching activity can cause >100A current variation on a multi-processor module with CMOS chips mid-frequency power delta-i noise must be contained within specified noise margins software tool used for noise simulations: SPEED97 from Sigrity Inc., San Jose, CA EPEP 2000, Scottsdale, 10/23/00 3 B.Garben, M.McAllister, IBM

4 1.2 SPEED input file (.spd) generation methods graphic interface: not practicable for a large number of vias and circuits design data import (CADENCE.brd): design date are not available at the beginning of the development of a new system not practicable for a complete system board with high complexity (computing resources) EPEP 2000, Scottsdale, 10/23/00 4 B.Garben, M.McAllister, IBM

5 problem: simulation time increases with number of planes plane size decreasing simulation grid (1mm via distance, <1mm grid, timesteps for 100ns) goal: less than 12 hours simulation time with the NT workstation (450MHz, PentiumII processor, 384MB RAM) reasonable accuracy EPEP 2000, Scottsdale, 10/23/00 5 B.Garben, M.McAllister, IBM

6 2. Simulation methodology 3. Simulation results 4. Verification by measurements 5. Summary & conclusions EPEP 2000, Scottsdale, 10/23/00 6 B.Garben, M.McAllister, IBM

7 2.1 New SPEED input file generation method complete input file generation with C-program: fast adaption to every system design phase & new system boards, faster than graphic input design data in Cadence BRD format (Allegro extract ) can be used high flexibility: package structure simplifications, start with design assumptions, e.g. preliminary locations of the module power/ground pins optimization of number and placement of board capacitors EPEP 2000, Scottsdale, 10/23/00 7 B.Garben, M.McAllister, IBM

8 2.2 One power&ground distribution system of a high-performance IBM system board and major simplifications for simulations PU-MCM (30 chips with on-chip decoupling capacitors, 700A nominal): 22 power/ground planes, 115mm x 115mm size ---> 4 power/ground planes (top and bottom plane pair) power/ground vias ---> 1647 & 3400 vias for design phase & verification model 1647 power/ground pins 275 decaps (each 220nF at 25C) System board with slots for memory cards & power supplies: 16 power/ground planes, 55cm x 45cm size ---> 4 power/ground planes (top and bottom plane pair) 3556 ceramic decaps (2886 x 1uF / 0805, 670 x 10uF / 1210) 320 electrolytic decaps on daughter cards (320 x 1.2mF) EPEP 2000, Scottsdale, 10/23/00 8 B.Garben, M.McAllister, IBM

9 I. Module simplifications: design phase & verification model with 504 & 1200 noise sources, 7 & 17 hours simulation time, 5% difference in mid-frequency noise amplitude 1. less power/ground vias (1647 & 3400) between planes, larger via distance, ratio via distance/diameter as in reality 2. smaller module thickness: ratio module thickness/number of via pairs as in reality 3. top and bottom power/ground plane pairs only (error < 3%) 4. planes are solid planes in SPEED97 simulations, but mesh planes in reality. Doubling the dielectric thickness for both power/ground plane pairs cause 2% increase of the mid-frequency noise amplitude. EPEP 2000, Scottsdale, 10/23/00 9 B.Garben, M.McAllister, IBM

10 II. Board simplification: approximation of the 16 power&ground planes by 4 planes (top and bottom plane pairs) dielectric thickness reduction by a factor 4 for both plane pairs plane conductivity increase by a factor 4 board thickness not changed verification: 16 planes approximated by 4 and by 8 planes: only 0.2% noise difference on top module planes board with 8 planes and board with 4 planes approximating 8 planes: only 1.4% noise difference EPEP 2000, Scottsdale, 10/23/00 10 B.Garben, M.McAllister, IBM

11 Fig.1: Board with 8 symmetric power/ground planes (right) and with 4 power/ground planes approximating 8 planes (left) board top surface power/ground planes 57um dielectric thickness 114um dielectric 114um dielectric 114um dielectric 114um dielectric board bottom surface vias EPEP 2000, Scottsdale, 10/23/00 11 B.Garben, M.McAllister, IBM

12 Mid-frequency delta-i noise simulation: schematics on-mcm decaps (259) L1_eff L E noise sources with on-chip decaps ( ) MCM vias ( ) MCM power supply L decaps L L MCM pins (1647) L2_eff board L decaps on board backside (1778) EPEP 2000, Scottsdale, 10/23/00 12 B.Garben, M.McAllister, IBM

13 2. Simulation methodology 3. Simulation results 4. Verification by measurements 5. Summary & conclusions EPEP 2000, Scottsdale, 10/23/00 13 B.Garben, M.McAllister, IBM

14 Fig.3: Noise voltage on top MCM thin film planes for delta-i = 140A, current sources at MCM surface start switching at time zero with 1ns cycle, 200nF module decap capacitance. 20 V o l t a g e (mv) T2 = 165ns T i m e (ns) EPEP 2000, Scottsdale, 10/23/00 14 B.Garben, M.McAllister, IBM

15 Fig.4: Square noise oscillation period versus series capacitance of total MCM (incl. source) capacitance and total board decoupling capacitance square of noise osc. period T2 (us square) 3,00E-2 2,50E-2 2,00E-2 1,50E-2 1,00E-2 5,00E-3 0,00E+0 L2_eff = 12.1pH (6.5pH MCM pins) capacitance C (uf) EPEP 2000, Scottsdale, 10/23/00 15 B.Garben, M.McAllister, IBM

16 2. Simulation methodology 3. Simulation results 4. Verification by measurements 5. Summary & conclusions EPEP 2000, Scottsdale, 10/23/00 16 B.Garben, M.McAllister, IBM

17 module capacitors: decap temperature range from 15C to 20C capacitance range from 200nF to 210nF delta-i = 237A, clocks on 975us - clocks off 10.7ms differential measurement of chip voltage at board backside EPEP 2000, Scottsdale, 10/23/00 17 B.Garben, M.McAllister, IBM

18 measured (chip in module center): 96mV mid-frequency noise amplitude, ns oscillation period simulated (SPEED97): 95mV with 169.0ns oscillation for 200nF decaps 92mV with 172.5ns oscillation for 210nF decaps excellent agreement within 5% for the mid frequency noise amplitude and oscillation period for the capacitance range. EPEP 2000, Scottsdale, 10/23/00 18 B.Garben, M.McAllister, IBM

19 bottom board planes below module corner, mid-frequency noise amplitude: measured: 14mV simulated: 14mV EPEP 2000, Scottsdale, 10/23/00 19 B.Garben, M.McAllister, IBM

20 A method has been developed to simulate the mid-frequency delta-i noise with SPEED97 on complex system boards with multi-processor module. Measurements and simulations agree within 5%. SPEED97 simulations provide a. early verification of mid-frequency noise margins b. early hardware design optimization, e.g. board decap placement, cost reductions EPEP 2000, Scottsdale, 10/23/00 20 B.Garben, M.McAllister, IBM