Nevis ADC Design. Jaroslav Bán. Columbia University. June 4, LAr ADC Review. LAr ADC Review. Jaroslav Bán

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1 Nevis ADC Design Columbia University June 4, 2014

2 Outline The goals of the project Introductory remarks The road toward the design Components developed in Nevis09, Nevis10 and Nevis12 Nevis13 chip Architecture block diagram Layout and features Reference voltage drivers PLL Clock generator Outputs Conclusion 2

3 The goals of the project Achieving 12-bit precision primary goal Visible margins in every aspect of the architecture Importance of system issues within radiation environment figure of merit type of things not a driving force for the ADC architecture See the measurement results in separate talk given by Tim Andeen 3

4 The road toward the design Nevis09 chip Operational trans-conductance amplifier (OTA) circuit developed o DC gain of > 80 db, UGB of >450MHz, power ~8mW, VDD=2.5V o The design (schematics and layout) stayed unchanged in all the next chips S/H circuit developed Confirmed understanding of the technology (IBM CMOS 8RF 130nm) Nevis09 layout Folded-cascode OTA 4

5 The road toward the design Nevis10 chip 2channels of 4MDACs working in pipeline mode Gain selection structure implemented to test high resolution ADC using gain selection algorithms o R&D for phase-2 MDAC circuit with 12 bit performance developed o Flip-around architecture o Bottom plate sampling to 1pF capacitors o subadc with separate sampling o Flash comparator sized to comfortably meet subadc offset requirements o 1.5 bits/stage, i.e. 3 possible codes to resolve one bit digital error correction to compensate for technology limitations (cap matching, gain, ) 5

6 The road toward the design Nevis10 layout MDAC block diagram (subadc not shown here) subadc unit (comparator and presampling) 6

7 The road toward the design Nevis12 chip : a big step toward the final design 2 channels of 12 bit ADC o four 1.5b MDACs followed by 8 bit SAR unit Two clock system (640MHz and 40MHz) with no PLL on the chip Output data serializer unit Foreground calibration constants computed outside the chip Digital data processing unit o Triple redundant calibration constants stored/used on chip o Digital correction on the chip 8 bit synchronous SAR unit o Synchronous operation at 640 MHz 7

8 The road toward the design SAR unit 8 bit synchronous SAR unit o Synchronous operation at 640 MHz o Very conservative approach o Total sampling capacitance of 18*56.6f = 1.072pF o Vcm translation (1.25V->0.6V) o Power ~3.8mW o Control part: Cern digital library components SAR switch principle 8

9 The road toward the design DDPU unit 80 MHz synchronous digital data processing unit o MDAC bit alignment o Storage for calibration constants o Performs digital correction o Binary adders to form final 12 bit ADC result o 87.5ns delay with respect to initial sampling o Power ~2mW o Fully synthesized design (Verilog, Cern scripts) 9

10 Nevis13 ADC design Architecture 10

11 Vref drivers Nevis13 ADC design Layout 3.6mmx3.6mm 120 die pins 48 GND down-bonds 72pin QFN package MDAC1 MDAC3 MDAC2 MDAC4 DDPU SAR SLVS drivers I2C Clock PLL Dose Serializers SLVS drivers 11

12 Nevis13 ADC design Nevis13 chip features 4 channels of 12bit ADC (4MDACs and 8bit SAR) Sampling information derived from the rising edge of differential input SLVS 40MHz clock Fast clock generated internally by PLL Differential signal input of 2.4V FS with 1.25V common mode voltage Reference voltages available on the I/O pins Band-gap circuit designed at Cern Power supply voltages: 1.2V and 2.5V Conversion result available 87.5ns after sampling Data sent out serially using 320MHz DDR SLVS clock signaling Special frame signal marks MSB of shifted data Calibration constants computed outside and applied inside the chip I2C interface (1.2V signaling) allows to control all internal functions of the chip Power dissipation of ~43mW/channel (preliminary measurement on few chips) 12

13 Nevis13 ADC design PLL unit PLL schematics 13

14 Nevis13 ADC design PLL unit Generates internal 40MHz and 640MHz clocks for SAR and serializer Low power (~6.5mW) Large filter (100pF) Design based on Cern work (P. Moreira, K. Poltorak, A. Kluge) Phase Detector unit taken from Cern design (schematics and layout) Charge Pump unit represents slightly modified Cern design Others sub-designs developed to meet a 640MHz frequency need Preliminary measured lock time < 10us 14

15 Nevis13 ADC design Clock generator 15

16 Nevis13 ADC design Clock generator Differential SLVS 40MHz clock at its input Clock termination (100 Ohm) inside Nevis13 chip Produces non-overlapping sampling clocks for MDAC pipeline (f1/f2) Sampling edge of f1/f2 comes from external 40MHz and other edge from internal PLL o Timing information in leading edge of 40MHz o Internal clock independent of input clock duty cycle Produces and distributes all other clocks (40MHz and 640MHz) needed in the system Guarantees that all internal clock relationships stay independent of technology (to a reasonable degree) 16

17 Nevis13 ADC design Clock system issue Two clock system (Nevis12 approach) Sampling (40MHz) and fast (640MHz) clocks distributed o Pros: No PLL is needed, less sensitivity to SEU o easy implemented programmable sampling delay o Cons: a need to distribute fast clock and extra hardware inside ADC to recover fast clock and to define slow/fast clock relationship System with PLL (Nevis13 approach) Sampling clock distribution only o Pros: no need to distribute a fast clock o Cons: PLL is needed with its sensitivity to SEU in a system with large number of ADCs o no easy programmable sampling delay Decision should be taken after we will have a radiation data from Nevis13 Good news: Nevis12 SEU tests indicate that capacitors > 0.7 pf have very low SEU sensitivity 17

18 Nevis13 ADC design Reference voltage generators (architecture) 1.1V 1.4V Input: 0.6V rom band-gap Digitally programmable 2x gain V ref s for MDACs and SAR (4 channels share 2 drivers) 1.25V V CM 0.6V V CM 18

19 Reference Voltage Drivers Reference voltage generators (buffers) Compensated with off-chip 10uF caps

20 Nevis13 ADC design Output data serializer and drivers SLVS drivers from Cern Fully synthesized serializer (using Cern macros) 320MHz clock using both edges of the clock Test functions implemented (test pattern, raw MDAC and SAR data, 12bit calibrated ADC data) Nevis13 frame and raw data Nevis13 clock and frame (received and translated to LVDS) 20

21 Nevis13 ADC design I2C interface module 1.2V SCL, SDA (open collector pulled up to 1.2V) signaling rstb line to reset PLL and band-gap ChipID[1:0] lines to create the I2C chain of up to 4 Nevis13 chips (ChipID[2] set inside the chip to 0 ) I2C interface allows to load all system and calibration bits of the ADC Calibration of the chip is controlled by this interface 7 and 10 bit addressing modes supported High speed mode supported I2C protocol is triple redundant Module is fully synthesized using standard Cern digital scripts 21

22 Conclusion Carefully planned step-by-step development led to the Nevis13 ADC design Nevis13 chip consist of 4 channels of 12 bit ADC Nevis13 just arrived and all functions foreseen are working Performance and radiation tolerance of the chip: testing has just started 22