Designing with Hitachi Flash Card

Transcription

1 Designing with Hitachi Flash Card Application Note ADE Rev.1.0 December 8,1997 Takeshi Furuno

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3 Notice When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. i

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5 Contents Introduction...1 Product line up...2 Features M Flash Memory...3 PC Card ATA mode and True-IDE mode...5 Card Pin Definition for PC Card ATA mode...5 Card Pin Definition for True-IDE mode V / 5V Interface Support...7 Attribute Memory Address Space...10 CIS 10 Function Configuration Registers...11 Task File Register and Protocol Definitions...12 PCMCIA Interface Task File Register Mapping...15 Memory Mapped Addressing...15 I/O Mapped Addressing...17 True-IDE Interface...18 Software Interface...19 Register Definition for Cylinder-Head-Sector Addressing...19 Register Definition for Logical Block Addressing...20 Supporting two Cards...21 PC Card Adapter for CompactFlash...21 Interoperability...23 Booting from a Hitachi Flash PC Card...24 PC Card Socket Controller...24 PC Card Software...27 Appendices...28 True-IDE Mode Interface Example...28 PC Card Socket Controller Set up Example...31 References and Resources...34 Glossary

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7 Introduction This document describes application information required to interface Hitachi s Flash PC-ATA and CompactFlash cards with a host system. The following sections describe key features of the Flash card, including specifications of the 64M AND type Flash Memory, the card pin definitions and functions in each interface mode of operations, register definitions, card configuration, CIS information, task files, software interface for sector data transfer and information regarding hardware and software interface between the card and a host system. Appendices includes examples of True- IDE interface circuitry and an example of PCIC setup. References and other resources as well as a glossary are included in the Appendices. Product line up The HB2860xxA3 PC-ATA card is available in 8 to 150 megabyte densities. The HB2860xxC3 CompactFlash is available in 8 to 45 megabyte densities. The table below shows the specific capacity for the various models and the default number of heads, sector/track and cylinders. Table 1. Capacity Specification Model Number Capacity Sectors/Card No. of Heads No. of Sectors/ Track HB286008A3 8,060,928 15, HB286015A3 16,121,856 31, HB286030A3 32,243,712 62, HB286045A3 48,365,568 94, HB286060A3 64,487, , HB286075A3 80,609, , HB286090A3 96,731, , HB286150A3 161,218, , HB286008C3 8,060,928 15, HB286015C3 16,121,856 31, HB286030C3 32,243,712 62, HB286045C3 48,365,568 94, No. of Cylinders Features The following list describes key features and specifications of Hitachi s PC-ATA card and CF card. For more detailed specifications, please refer to the current data sheet. 1

8 HB2860xxA3 PC-ATA card: PCMCIA type II form factor with 68 pin two pieces connector. 5.0mm thick, 54.0mm wide and 85.6mm long. Supports Memory Card Mode, I/O Card Mode and True-IDE Mode of operation Supports 3.3V/5V single power supply operation. Up to 150MB of capacity available with 20 pieces of Hitachi 64M AND Flash Memory(HN29W6411) 512 bytes sequential access in both Read and Write operation Sector Data Read/Write transfer rate to/from host is up to 8MB/sec in burst Automatic ECC function ensures data reliability less than 1 error in bits read Self-diagnostic function at power on Automatic wear leveling function ensures endurance up to 100,000 writes for each sector Automatic Sleep Function for power down HB2860xxC3 CompactFlash: CompactFlash Specification Compliant with 50 pin two pieces connector. 3.3mm thick, 42.8mm wide and 36.4mm long Supports Memory Card Mode, I/O Card Mode and True IDE Mode. Supports 3.3V or 5V single power supply operation Up to 45MB of capacity available with 6 pieces of Hitachi 64M AND Flash Memory(HN29W6411) 512 bytes sequential access in both Read and Write operation Sector Data Read/Write transfer rate to/from host is up to 8MB/sec in burst Automatic ECC function ensures data reliability less than 1 error in bits read Self-diagnostic function at power on Automatic wear leveling function ensures endurance up to 100,000 writes for each sector Automatic Sleep Function for power down 64M Flash Memory The following list describes features and specifications of Hitachi 64M CMOS Flash Memory HN29W6411. For more detailed specifications, please refer the HN29W6411 Series data sheet Features: Supports 3.3V or 5V single power supply operation Proprietary AND type memory cell with advanced CMOS process technology Memory array organized in (512+16) bytes x (more than sectors and less than sectors) 2

9 (512+16) byte of on chip data register Nominal 1ms automatic programming with internal verify function Nominal 1ms automatic erase with internal verify function Program / erase completion notification by RDY/Busy signal pin Supports Status Register Function Supports Single Sector Erase(528bytes) and Block Erase(8x528bytes) Very high performance in serial read access Very low power External Error Correction for more than 1bit error per sector read is required for data reliability Specifications: Package: 48-pin 0.8mm pitch TSOP II(TTP-48/40D) 30-pin 0.8mm pitch TCP Sector address is A0 to A13 Address is multiplexed with data Second and third bus cycles are used to write address for Read/Program/Erase/Erase Verify operation To utilize Mostly Good Memory, the Sector Valid Data is written in the control bytes 5 bus operation modes are defined: Deep Standby: Lowest power mode Standby: Idle mode after power on Output disable: I/O is in High impedance Status Register read: Default read mode after power on Command write: Commands are written into the on chip latch 12 commands are defined: Serial Read(1), Serial Read(2), Read ID code, Single Sector Erase, Block Erase, Program(1), Program(2), Program(3), Erase Verify, Reset, Read Status Register, Clear Status RegisterAbsolute Maximum Rating for Vcc, Vin and Vout is -0.6V to +7V Absolute Maximum Rating for Operating temperature range is 0 to 70 degrees Centigrade Critical electrical characteristics specifications are summarized in tables 2 and 3. 3

10 Table 2. DC Characteristics for HN29W6411 Mode Icc Unit Vcc Condition Read 50 ma, max 3.3V Read 70 ma, max 5V Standby 50 µa, max 3.3V Standby 100 µa, max 5V Erase/Program 40 ma, max 3.3V Erase/Program 60 ma, max 5V Deep standby 5 µa, max 3.3V Deep standby 10 µa, max 5V Table 3. AC Characteristics for HN29W6411 Mode Time Unit Vcc Condition Read, First access 5 µs, max 3.3V or 5V Read, Serial access 50 ns, max 3.3V or 5V Sector program 1 ms, typ 3.3V or 5V Sector erase 1 ms, typ 3.3V or 5V Block erase 1 ms, typ 3.3V or 5V PC Card ATA mode and True-IDE mode Both the PC-ATA and CF cards provide high capacity solid-state storage that electrically complies with Personal Computer Memory Card International Association ATA (PC Card ATA) standards. Both Flash cards can be used in True IDE mode that is electrically compatible with an IDE disk drive in standard PC applications. On power up, the card s internal controller monitors the -OE input. If -OE is low, it assumes that the card is in an True IDE environment and configures the interface accordingly. If -OE is high, it will configure itself as a PC Card ATA disk drive. Card Pin Definition for PC Card ATA mode All 16-bit PC cards must initially operate as a memory-only device since the socket controller has no way of knowing whether a PC card installed requires a specific interface other than memory. Therefore, when Hitachi PC-ATA card or CF card with PC Card Adapter are inserted into a PC Card socket, the pin definition is initially defined as a Memory card mode, allowing access to the Card Information Structure (CIS), which is mapped in attribute memory address space. Configuration software then reads the CIS, determines the card requires an I/O interface and programs the socket controller and the card to reconfigure the socket interface to the I/O card mode 4

11 pin definition. New signals are added to the socket when the socket interface is configured to I/O card mode. Some of the new signals replace pins that are reserved in the memory card mode, while others replace selected status pins used in the Memory card mode. The status-change events which are reported directly over the appropriate status change pins in the Memory card mode, will be reported via the Pin Replacement Register and the Card Configuration and Status Register. Table 4 shows pin definitions for memory card mode interface and I/O card mode interface in PC Card ATA mode of operation. For detailed specification of each signal, please refer to the data sheet. 5

12 Table 4. Card Pin Definition for PC Card ATA mode Pin NO. PC-ATA card CF card Signal Name 30,31,32,2,3,4,5, 6,64,65,66,37,38,39, 40,41 29,28,27,26,25, 24,23,22,12,11,8 21,22,23,2,3,4,5, 6,47,48,49,27,28,29,30,31 20,19,18,17,16,1 5,14,12,11,10,8 D0..D7 D8..D15 A0..A10 Memory card mode Data bus Address bus 1, 34, 35, 68 1, 50 GND Ground 17, 51 13, 38 VCC Power Supply 36, 67 26, 25 -CD1, -CD2 Card Detect I/O card mode 7, 42 7, 32 -CE1, -CE2 Card Enable 1, Card Enable OE Output Enable WE Write Enable RDY/-BSY, - IREQ Card ready Interrupt Request WP,-IOIS16 Write Protect I/O Port is 16 bits 43, 57 33, 40 VS1, VS2 Voltage Sense IORD reserved I/O Read IOWR reserved I/O Write RESET Reset WAIT Wait INPACK reserved Input Port Acknowledge REG Register Select I/O Enable BVD2, -SPKR Battery Voltage Detect BVD1, - STSCHG Battery Voltage Detect 1 Digital Audio Output Card Statuses Changed 6

13 Card Pin Definition for True-IDE mode In True-IDE mode, the PCMCIA protocol and configuration is disabled, Memory or Attribute Registers are not accessible to the host and only I/O operations to the Task File and Data Register are allowed. The True-IDE interface includes register select signals, three address lines, 16 data lines and control signals. Table 5 shows pin definitions for True-IDE mode of operation. Table 5. Card Pin Definition for True-IDE mode Pin NO. Signal Names I / O 30,31,32,2,3,4,5,6,64, 65,66,37,38,39,40,41 29,28,27,26,25,24,23,22, 12,11,8 D0..D7 D8..D15 I/O Data bus A0..A10 I Address bus, A0..A2: used A3..A10:should be grounded by host 1,34,35,68 GND Ground 17,51 VCC Power Supply 7, 42 -CE1, -CE2 I Card Enable 9 -ATASEL I True-IDE mode select 15 -WE I not used 16 INTRQ O Interrupt Request 33 -IOCS16 O 16-bit I/O 36, 67 -CD1,-CD2 O Card Detect 43, 57 -VS1, -VS2 O Voltage Sense 44 -IORD I I/O Read 45 -IOWR I I/O Write 58 -RESET I Reset 59 IORDY O may be used as I/O Ready 60 -INPACK O Input Acknowledge 61 -REG I not used 62 -DASP I/O Disk Active/Slave Present 63 -PDIAG I/O Pass Diagnostic Signal 3.3V / 5V Interface Support From the PC Card Standard 95 release, PC Card specifications define two additional pins and a mechanical key to support auto-sensing of the power-on voltage of the PC Card. Most of the newer socket controllers such as CL-PD6722 from Cirrus Logic support 3.3/5V operation. 7

14 There are two kinds of voltage keys for PCMCIA sockets and two for PC cards. The 5V key identifies sockets that can only support 5V Vcc. Cards that can support both 3.3V and 5V would be compatible with this socket. Card that can operate only at 3.3V or lower would have a low voltage key. This low voltage key would prevent insertion into a socket that have a 5V key. A socket with a low voltage key is a socket that can support operation at 3.3V. This socket would accept cards with either a low voltage key or 5V key. The newly defined voltage sense pins VS1 and VS2 allow the host controller to determine what type of card is inserted without having to apply power to the card. The value of VS1 and VS2 determine the initial Vcc voltage that is applied to the socket when a PC Card is installed. Both VS pins are pulled to 5 V by the host system. When a low voltage card is installed, it pulls one or both of the VS pins low to indicate the initial Vcc it requires. The following Table 6 illustrates the various possible situations that the host will see with Hitachi PC-ATA card and CF card. Table 6. Card and Socket Interaction Model Number V S 1 V S 2 Card Type Socket Type Compatibility HB2860xxA1 Open Open 5V key 5 volt key 5V only CIS Low Voltage key, 5V capable Low Voltage key, no 5V Rejected* HB2860xxC2 ground Open 5V key, 3.3V and 5V CIS 5 volt key HB2860xxAT Low Voltage key, 3.3V only HB2860xxC3 HB2860xxA3 Low Voltage key, 3.3/5V capable Low voltage key, no 3.3V or 5V available Rejected* * Will fit into slot, but power will not be applied. ** CF card is used with PC card Adapter Note: The voltage sense pins determine the initial operating voltage required to read the CIS. The host system can read the CIS to determine if the card supports any other operating voltage of the card. The rejected note in the table indicates that host software will not attempt to power-up the socket if this condition is detected. Newer socket controllers from Cirrus Logic CL-PD6710/22,Vadem VG-469 and Intel 82365SL DF and others support 3.3V/5V mixed voltage designs: 5V CPU/System Logic and 5V PC Card interface 3.3V CPU/System Logic and 5V PC Card interface 5V CPU/System Logic and 3.3V PC Card interface 8

15 3.3V CPU/System Logic and 3.3V PC Card interface The Vcc voltage for the PC Card interface must be software configured during card initialization. The Vcc control truth table for the Vadem VG-469 is as follows: Table 7. Vadem VG-469 VCC power control states VCCEN0 VCCEN1 Operating Voltage 0 0 No Power V Operation V Operation 1 1 Reserved, Future use Most of the newer socket controllers separate power planes. The standard implementation is that the Vcc enable signals control power not only to the socket but also to the socket interface circuitry in the controller ASIC. This insures that the power to the socket is slewed at the same rate as the interface signals. The Fig.1 below shows how the multiple power planes allow the socket controller to switch between 3.3V and 5V operating voltages. Fig /5V Support Block Diagram 9

16 Attribute Memory Address Space Hitachi s PC-ATA card / CF card have two kinds of attribute memory, Card Information Structure (CIS) and Function Configuration Registers. The CIS information is stored in the Flash Memory and is loaded on to the controller during the power up initialization of the card. Attribute memory data is mapped only to even addresses as shown in Fig.2. Information is returned only on the lower data path [D7:D0]. CIS is read only from the host. Four Function Configuration Registers are 8-bit read/write registers. Fig. 2 Attribute Memory Space CIS The purpose of CIS (Card Information Structure) is to provide a standard way to describe what kind of PC card it is and card characteristics such as speed, size, and the system resources required by the card. The information is read from the CIS during card initialization after power-on or hard reset, and the PCMCIA socket controller can be programmed to allow access to the PC card, and the card itself can be configured by writing to its configuration registers. The CIS is mapped into the attribute memory address space starting at address zero. The CIS is organized as linked list of data blocks, which are called tuples, that describes the function and 10

17 characteristics of the PC card. The CIS data is mapped only to even location within the attribute address space thus, information is returned only on the lower data path [D7:D0]. This simplifies card designs for accommodating 8-bit host systems that connect only to the lower data path. Function Configuration Registers The PC-ATA and CF cards have four Function Configuration Registers which are summarized in Table 8. Table 8. Function Configuration Register specifications Name Length Access Configuration 8-bit read/ Option Registers write Configuration and Status Registers Pin Replacement Registers Socket and Copy Registers 8-bit 8-bit 8-bit read*/ write read/ write read/ write Initial Value** 00H 00H 0CH 00H * bit 1 (INTR) and bit 7 (CHGED) of this register are read only. ** Initial value of the register after power up. Description This register is used to select card s interface such as Task File Register mapping configuration, interrupt mode and to issue a soft reset to the card. This register contains information about cards condition. It returns status on the interrupt and status change bits of the card. This register provides current internal status and change status of READY signal This register is used by the host to assign each card a unique Drive Number. This register is always written by the host before writing the card s Configuration Option Register In the actual configuration process after the card is inserted to the PCMCIA socket, the four Function Configuration Registers are accessed by the host software in the following order: (1)Card Configuration and Status Register (Address: 202H) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 CHGED SIGCHG IOIS8 0 0 PWD INTR 0 (2)Pin Replacement Register (Address: 204H) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 CRDY/-BSY RRDY/-BSY 0 11

18 (3)Socket and Copy Register (Address:206H) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit DRV# (4)Configuration Option Register (Address: 200H) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SRESET LevlREQ Configuration INDEX Task File Register and Protocol Definitions Hitachi PC-ATA card / CF card can be configured as a Memory Mapped device or as a high performance I/O device through standard I/O address space: 1F0H-1F7H, 3F6H-3F7H (primary); 170H-177H, 376H-377H (secondary) and IRQ14 (or other available IRQ) or as a 16 contiguous block of registers which are I/O mapped with any available IRQ. The communications to and from the card is performed using the twelve Task File registers which provides all the necessary control and status information. Under the PCMCIA environment, the PC-ATA and CF cards can be connected to the host using four register mapping methods. The four register mapping methods as shown in Table 6 are controlled by the values in the Configuration Index field of the Configuration Option Register and the value in the Socket and Copy Register. By default the Configuration Index is cleared on power-on reset, forcing the interface into the Memory Mapped mode of operation. Recently, the name ATA Command Block Registers is now used to refer the first ten registers. The name ATA Control Block Registers is used to refer the Device control and the Alternate Status Registers. Table 9. Standard Configurations Configuration Index[b5:b0] I/O or Memory Task File Register Address A[10:0] Drive Number Socket & Copy Description Memory 0H - FH, 400H - 7FFH 0 x000xxxx Memory Mapped I/O xx0h - xxfh 0 x000xxxx I/O Mapped 16 Contiguous Registers I/O 1F0H-1F7H, 3F6H-3F7H 0 x000xxxx Primary I/O Mapped Drive I/O 1F0H-1F7H, 3F6H-3F7H 1 x001xxxx Primary I/O Mapped Drive I/O 170H-177H, 376H-377H 0 x000xxxx Secondary I/O Mapped Drive I/O 170H-177H, 376H-377H 1 x001xxxx Secondary I/O Mapped Drive 1 The host selects the card s register mapping configuration by writing the Configuration Index value to the least significant 6 bits of the Configuration Option Register. The configuration index values of the card are reported to the host using the Configuration Table Entry tuples in the CIS. 12

19 I/O address 1F0H-1F7H, 3F6H-3F7H, 170H-177H, 376H-377H contain the standard command block registers of IDE-ATA interface. When the registers are mapped into memory locations, a contiguous 2KB block of memory locations are used. The command and control registers are mapped into the first 16 bytes of the 2kB memory block, while the last 1KB of the block is used as a high speed buffer to transfer data to and from the PC card. Hitachi PC-ATA card / CF card have 13 Task File registers as shown in the Table

20 Table 10. Task File Register specifications Name Length Access Data Register 16-bit read/ write 14 Initial Value Description - This register is used to transferred sector data by either a series of word accesses or a series of byte accesses. Error Register 8-bit read 01H This register contains either additional information about the source of an error from the last executed command or it contains a diagnostic code. At the completion of any command except Execute Drive Diagnostic, the contents of this register are valid when ERR=1 and BSY=0 in the Status Register. Feature Register 8-bit write - This register provides command specific information to the card. Information written to this register becomes a command parameter for subsequent commands written to the Command Register. Sector Count Register Sector Number Register Cylinder Low Register Cylinder High Register 8-bit 8-bit 8-bit 8-bit read/ write read/ write read/ write read/ write Drive Head Register 8-bit read/ write 01H 01H 00H 00H 00H This register is written by the host with number of sectors to be processed in the subsequent command. If the value in this register is zero, a count of 256 sectors is specified. This register is written by the host with the starting sector number to be used in the subsequent CHS command. When LBA is used, this register is written by the host with bits 7 to 0 of the starting logical block number. This register is written by the host with the low-order byte of the starting cylinder address to be used in the subsequent CHS command. When LBA is used, this register is written by the host with bits 15 to 8 of the starting logical block number. This register is written by the host with the high-order byte of the starting cylinder address to be used in the subsequent CHS command. When LBA is used, this register is written by the host with bits 23 to 16 of the starting logical block number. This register is used to specify the selected drive of a pair of drives sharing a set of registers. The LBA bit defines the address translation as CHS or LBA, and provides the head address if CHS mode is selected or LBA bits 27 to 24 if the LBA bit is set to one. Status Register 8-bit read 50H This register return the card status when read by the host. Reading this register clears a pending interrupt request. The contents of this register, except for BSY, shall be ignored when BSY bit is set equal to one. Alternate Status Register 8-bit read 50H This register return the card status when read by the host. Reading this register does not clear a pending interrupt request. Command Register 8-bit write - This register contains the command code being sent to the card. Command execution begins immediately after this register is written. Device Control Register Device Address Register 8-bit write 00 This register is used to control the card interrupt request and to issue a soft reset to the card. 8-bit read 3Dh This register is implemented for compatibility with the AT disk drive interface. It is recommended that this register not be mapped into the host s I/O space because of potential conflicts on bit 7.

21 PCMCIA Interface Task File Register Mapping The ATA specification defines that the Data register is 2 bytes wide and is located at offset 0H while the Error and Feature registers are 1 byte wide and are located at offset 1H within the ATA registers. This results in an overlap of address spaces between the Data register and Error - Feature register combination. The PC-ATA and CF cards provide a non-overlapping, duplicate copy of each of these registers in the Memory Mapped and Contiguous I/O Mapped configurations. Within the 16 byte space occupied by the ATA registers in these configurations, the duplicate data register is located at offset 8H while the duplicate Error and Feature registers are located at offset DH. Because of the overlapped registers, access to the Error or Feature registers at 1F1H, 171H and 1H are not possible when word accesses with -CE1 and -CE2 both asserted are performed. The duplicate registers at relative addresses 8H, 9H and DH have no restrictions on the operation which can be performed by the socket used to access the registers. Memory Mapped Addressing When Memory Mapped Addressing is selected by the value in the card s Configuration Option Register, the Hitachi PC-ATA card and CF card will respond at the address indicated within the range of 0H - 0FH and 400H - 7FFH from the start of the address space allocated to the PC Card ATA memory mapped registers as indicated by the CIS Device ID and JEDEC ID tuples. The Task File registers are accessed via memory reference and appear in the common memory space window from 0-2k bytes as shown in Table

22 Table 11. Memory Mapped Address Map -REG A10 A[9:4] A3 A2 A1 A0 Offset -OE =L -WE = L Note 1 0 x H Data register Data register x H Error register Feature register x H Sector count register 1 0 x H Sector number register 1 0 x H Cylinder low register 1 0 x H Cylinder high register 1 0 x H Drive Head register Sector count register Sector number register Cylinder low register Cylinder high register Drive Head register 1 0 x H Status register Command register 1 0 x H Dup. Even Data register 1 0 x H Dup. Odd Data register 1 0 x DH Dup. Error register 1 0 x EH Alternate Status register 1 0 x FH Drive Address register 1 1 x x x x 0 8H Even Data register Dup. Even Data register Dup. Odd Data register Dup. Feature register Device Control register Reserved Even Data register 1,3 1,3 1, x x x x 1 9H Odd Data register Odd Data register NOTES: 1. This register supports word or byte accesses. The Data Register at 0H is accessed with both - CE1 and -CE2 asserted as a word register on the combined data bus (D[15:0]). This register may also be accessed by a pair of byte accesses to the location at offset 0H with -CE1 asserted and -CE2 negated. When accessed twice as a byte register with - CE1 asserted and -CE2 negated, the first byte to be accessed is the Even byte of the Word and the second byte accessed is the Odd byte of the equivalent Word. If -CE1 is negated and -CE2 is asserted, then A0 is don t care and an access to either offset 0H or 1H will access the Error(read) or Feature(write) register. The data for these accesses will always be on the high byte of the data path (D[15:8]). 2. This register overlaps the address space of the Data register. 4 16

23 3. This register address is a duplicate address assignment for another register. A duplicate address is not available in the Primary I/O and Secondary I/O register decodings. Register 8H is equivalent to register 0H, while register 9H accesses only the Odd byte of the Data register. If the Data register is byte accessed in the order of 9H and then 8H, the data will be transferred as Odd byte then Even byte. As in note 1, repeated byte access to register 8H will access consecutive (even and odd) bytes from the data buffer. Repeated access to register 9 are not supported. Repeated alternating byte access to registers 8H and 9H will access consecutive (even and odd) bytes from the data buffer. Repeated word accesses to register 0H or 8H will access consecutive words from the data buffer. 4.Memory access to even addresses at offsets between 400H and 7FFH access register 8H. Access to odd addresses at offsets between 400H and 7FFH access register 9H. I/O Mapped Addressing The mapping of the Task File registers for the Primary I/O, Secondary I/O, and Contiguous I/O address maps as selected by the Configuration Index field of the Configuration Option Register is shown in Table below. Address lines which are not indicated in the decoding below are ignored by the card for accessing these registers. The primary and secondary modes decode 10 address lines while the contiguous decoding decodes only 4 address lines on the 17

24 Table 12. I/O Mapped Address Map REG Primary A[9:0] Secondary A[9:0] Contiguous A[3:0] IORD = L IOWR = L Note 0 1F0H 170H 0H Data register Data register 1 0 1F1H 171H 1H Error register Feature register 2 0 1F2H 172H 2H Sector count register Sector count register 0 1F3H 173H 3H Sector number register Sector number register 0 1F4H 174H 4H Cylinder low register Cylinder low register 0 1F5H 175H 5H Cylinder high register Cylinder high register 0 1F6H 176H 6H Drive Head register Drive Head register 0 1F7H 177H 7H Status register Command register H Dup. Even Data register Dup. Even Data 1, H Dup. Odd Data register Dup. Odd Data register 1, DH Dup. Error register Dup. Feature register 3 0 3F6H 376H EH Alternate Status register Device Control register 0 3F7H 377H FH Drive Address register Reserved Notes: 1. This register supports word or byte accesses. See note 1 for Table Memory Mapped Address Map. 2. This register overlaps the address space of the Data register. See note 1 for Table Memory Mapped Address Map. 3. This register address is a duplicate address assignment for another register. A duplicate address is not available in the Primary I/O and Secondary I/O decodings. See note 2 for Table Memory Mapped Address Map. True-IDE Interface I/O decoding for True-IDE mode to access the Task File registers is shown in the Table. When the host asserts -IORD low, the host reads the contents of the selected Task File registers, and when -IOWR is asserted low, the host data is written into the addressed Task File register. Reads of the Task File registers are qualified by the BSY bit in the Status register. The BSY bit indicates, among other things, the ownership of the Task File registers. When BSY bit is set, the card owns the Task File registers and a write to a Task File register by the host will be ignored. When the BSY bit is clear, the host owns the Task File registers and can modify them. If the host attempts to read any register when the BSY bit is set, the contents of the register are not valid. 18

25 Table 13. True-IDE Mode I/O Decoding -CE2 -CE1 A2 A1 A0 -IORD = L -IOWR = L Data register Data register Error register Feature register Sector count register Sector count register Sector number register Sector number register Cylinder low register Cylinder low register Cylinder high register Cylinder high register Drive Head register Drive Head register Status register Command register Alternate Status register Device Control register Drive Address register Reserved Software Interface The Task File region includes the Data register and the group of seven registers which are used to issue commands using the ATA command protocol. The interpretation of the contents of these registers is a function of the addressing mode which is used to address the Flash memory in the card. The PC-ATA and CF card support a Cylinder-Head-Sector addressing (CHS) mode and a Logical Block addressing (LBA) mode. Register Definition for Cylinder-Head-Sector Addressing To perform a function the host writes up to seven bytes to the card. These bytes specify the command to be executed and its associated parameters. The following figure shows the general content of the Task File registers. The first sector processed uses the unmodified values placed into the Task File registers by the host. After a sector is processed the card will modify the appropriate registers. The Sector Count register is decremented after each sector is transferred. If the Sector Count register value is 0x01 and the end of the sector occurs, the register is decremented to 0x00 but the Sector Number Register is not incremented. The Sector Identification of the last sector transferred remains in the Task File register at the completion of the transfer command. 19

26 Table 14. Commands with Cylinder-Head-Sector Encoding Bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Byte offset 1 Feature Byte offset 2 Sector Count Byte offset 3 Sector Number Byte offset 4 Cylinder Low Byte offset 5 Cylinder High Byte offset 6 1 LBA 1 DRV Head Byte offset 7 Command Register Definition for Logical Block Addressing To perform a function using Logical Block Addressing, the host writes to the same seven registers as for Cylinder-Head-Sector Addressing. However, the LBA bit is set and the Sector Number, Cylinder Low, Cylinder High and Head field of the Task Files provide a starting logical block address on the card. These registers are treated as a 28-bit counter containing the Logical Block Address of the sector being transferred and is incremented at the end of the transfer of each sector. The Sector Count register is decremented at the end of the transfer of each sector. If the Sector Count register value is 1 and the end of sector occurs, the Sector Count register is decremented to 0 but the LBA is not incremented. The Sector Identification of the last sector transferred remains in the Task Files at the completion of the transfer command. Table 15. Commands with Logical Block Addressing Encoding Bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Byte offset 1 Feature Byte offset 2 Sector Count Byte offset 3 Logical Block Number A7-A0 Byte offset 4 Byte offset 5 Logical Block Number A15-A8 Logical Block Number A23-A16 Byte offset 6 1 LBA 1 DRV Logical Block Number A27-A24 Byte offset 7 20

27 CHS to LBA translation formula: LBA to CHS translation formula: LBA = (C*HpC+H)*SpH+S-1 C=LBA/(HpC*SpH) H=(LBA/SpH)modHpC S=(LBAmodSpH)+1 where LBA is Logical Block Address C is Cylinder Number H is Head Number S is Sector Number HpC is Heads per Cylinder SpH is Sectors per Head (Track) Supporting two Cards It is possible for two Hitachi PC-ATA or CF cards to be simultaneously installed into PCMCIA sockets of the same socket controller. This is accomplished in True-IDE mode via the daisychained cable with the proper setting of Cable-Select Signal (-CSEL) at the socket side. When the Cable Select signal is grounded, the card is configured as a Master. When the pin is open, the card is configured as a Slave. Data written to the Task File registers by the host are written into the registers of both Master and Slave if both cards are present on the interface. A read of the Task File registers by the host is responded by the Master only if the DRV bit in the Drive Head register is equal to 0. If the DRV bit is equal to 1, then the Slave will respond to host s read access to the Task File registers. In the PCMCIA environment, a configuration register, called the Socket and Copy Register, can be used to identify two PC ATA cards or CF cards mapped to the same space. The copy number programmed into the Socket and Copy Registers is used by the PCMCIA socket controller to differentiate drive 0 from drive 1. PC Card Adapter for CompactFlash The PC Card Adapter for CompactFlash uses a 68 pin connector and converts 50 pin CompactFlash card into 68 pin PCMCIA PC card which is compatible with PC card slot(typeii). Both connectors use less than 50 signals. Table 10 shows the pin out differences between the CompactFlash card and the PC Card Adapter. 21

28 Table 16. Pinout Differences Between CF Card and PC Card Adapter Pins PC Card Adapter CF Card Pins PC Card Adapter CF Card 1 GND GND 35 GND -IOWR 2 D03 D CD1 -WE 3 D04 D04 37 D11 -RDY/-BSY/-IREQ 4 D05 D05 38 D12 VCC 5 D06 D06 39 D13 -CSEL 6 D07 D07 40 D14 -VS2 7 -CE1 -CE1 41 D15 RESET 8 A10 A CE2 -WAIT 9 -OE -OE 43 -VS1 -INPACK 10 A11 A IORD -REG 11 A09 A IOWR BVD2 12 A08 A07 46 A17 BVD1 13 A13 VCC 47 A18 D08 14 A14 A06 48 A19 D WE A05 49 A20 D RDY/-BSY/-IREQ A04 50 A21 GND 17 VCC A03 51 VCC 18 VPP1 A02 52 VPP2 19 A16 A01 53 A22 20 A15 A00 54 A23 21 A12 D00 55 A24 22 A07 D01 56 A25 23 A06 D Vs2 24 A05 WP/-IOIS16 58 RESET 25 A04 -CD2 59 -WAIT 26 A03 -CD1 60 -INPACK 27 A02 D REG 28 A01 D12 62 BVD2 29 A00 D STSCHG 30 D00 D14 64 D08 31 D01 D15 65 D09 32 D02 -CE2 66 D10 33 WP/-IOIS16 -VS1 67 -CD2 34 GND -IORD 68 GND 22

29 Interoperability The PC-ATA and CF cards incorporate configuration option information in non-volatile memory within the card. Configuration data is kept in an area within the card known as the CIS. PC Card enabler software installs each time the system is powered up. This software checks for the presence of PC Cards that are installed. If a PC card is detected, the software reads the contents of its CIS to determine the type of device it is, the system resources that it requires, and the configuration options that are possible. The enabler is then responsible for configuring the PC card so it can be accessed. Hardware notifies when a new card is installed so that it can be properly configured into the system. When a card is removed, hardware detects the card s removal and notifies software that the device is no longer installed. PCMCIA sockets can be designed into a various kind of PC bus architecture including ISA, PCI and CardBus as well as non-pc designs. The connection between a given host bus and a PCMCIA socket is provided through a PCMCIA host bus adapter(hba). The adapter acts as a bridge to pass host transactions to PC cards installed in PCMCIA sockets. PCMCIA host bus adapter is often called PCMCIA socket controller or PC Card Interface Controller(PCIC). The host bus adapter must be programmed by the system in the manner which is determined by the requirements written in the CIS in order to gain access to PC cards. Each PCMCIA socket has its own dedicated signal interface provided by the HBA. That is, signals are not bussed between sockets as in most expansion bus architectures. Access to each socket is controlled through separate sets of socket interface circuitry, each of which must be initialized in order to gain access to a PC Card installed in a given socket. There are several manufacturers of ISA to PC Card host bus adapters including: Cirrus Logic, DataBook, Intel, Texas Instruments, Vadem, VLSI Technology, and others. Each of these designs to some extent implement different registers and initialization algorithms. Due to the variation of the implementations, the programmers have to write their software to interface to each type of host bus adapter in order to ensure proper operation in all system platforms. To hide the details of the hardware interface from the programmer, the PC Card specification defines a common software interface called Socket Service which provides a low-level software interface that gives programmers access to a common set of functions that will permit initialization of any HBA. There are several software vendors who have developed Socket Services for each of the major PCMCIA host adapters. These vendors include: America Megatrends, Award Software, Phoenix Technology, SystemSoft, Ventura Micro Inc., and others. The software called Card Service provides a software layer consisting of high-level functions that programmers can call to gain access to a card, determine its configuration requirements, and request the system resources it requires. The primary function Card Service does for PC Card enablers is system resource allocation. However, it also notifies enablers of card insertion and removal and other status change events. 23

30 Once having been detected and configured, a Hitachi PC card behaves like any other device that exists on the expansion (PCMCIA host) bus. This allows applications to access PC Cards directly through the normal methods used in a given operating environment. This access can be done without using the PCMCIA software interface (i.e. Card and Socket Services) once the proper configuration is established. Booting from a Hitachi Flash PC Card Booting an OS from Hitachi s Flash PC-ATA or CF card requires a system which has been designed or updated to know how to initialize, search for, and boot from a boot-image on the PC card. The ROM-based PCMCIA initialization code must be included with the system to support initial program load from the PC card. The firmware code must be able to program socket controller to open an attribute memory window to permit access to the CIS. Then the PCMCIA initialization firmware recognizes Hitachi PC-ATA or CF card by evaluating the function identification tuple within the CIS. The Hitachi PC-ATA and CF cards have the Function Identification Byte = 04H which correspond to Fixed Disk. The Disk Function Extension tuple 01H defines the Disk interface type. The interface type code 01H indicates PC Card-ATA interface. The PC Card ATA Function Extension tuple defines additional ATA card features. The system initialization byte specifies that the ATA card should be configured during Power-On Self Test but the card does not contain BIOS ROM. In order to boot from a Hitachi PC-ATA or CF card, some system firmware must initialize the socket controller and configure the PC-ATA or CF card. Once the ATA card is configured, the operating system can boot directly from the card. For actual PCMCIA software support, please contact following major system software vendors: American Megatrends, Award Software, Phoenix Technology, SystemSoft and others. PC Card Socket Controller The PC Card socket controller provides the interface between the host bus and the PC Card sockets. A socket controller is an adapter implemented in large scale integration (LSI) integrated circuits. The socket controllers currently available interface to one or more PC card sockets. The socket controller supports the following specific functions: Power switching Card detection Address translation Socket data buffering and control Socket data transfer timing and control Host bus transfer control PC Card interrupt steering Socket status reporting 24

31 Status change interrupt generation and steering Power Conservation (Power Management) Most socket controllers interface directly to the host's ISA bus. The host address bus SA[0..16] and LA[17..23] and data bus SD[0..15] connect directly to the corresponding socket controller's pins. I/O strobes, -MEMR, -MEMW, -IORD, -IOWR, -IOIS16, IOCHRDY, ALE, AEN, - MEMCS16, SBHE, -ZEROWS connects to the corresponding pin on the socket controller. Since the PCMCIA socket interfaces are not bussed together, separate signal lines are required for each sockets, that is, 68 pins must be included for each socket supported by an PC Card socket controller. In order that card can be inserted and removed with the power on, the buffers (usually transceivers) to isolate the PC card bus from the host system s or another PC card s bus are required. The Intel 82365SL, Vadem VG-365 and Databook DB86081 socket controllers require external buffers to safely isolate the PC card from the host system s bus during card insertion/removal. Vadem VG-465/468/469, Cirrus Logic CL-PD6710/22, Databook DB86082 integrates the buffers inside of the controller so that no external buffers are necessary. The example interface figure shows the interface between the Vadem VG-465 socket controller and the 68-pin PC Card socket. 25

32 Fig. 3 Socket Controller Interface For internal wait state and other timing generation, most controllers require a clock signal of between 8 to 14MHz. Access to the socket controller's internal configuration registers is through an index/data register scheme. This allows a large number of configuration registers without taking too much I/O space. Each socket should have its own set of addressable registers at its own I/O address or separate region of the index address range. To assure the most flexibility, connect all available IRQs to the corresponding socket controller's IRQs. To prevent Card Services from allocating those interrupts which are already in use for peripherals, the CS resource database must be initialized to reflect the available system interrupts. The socket controller generates the status change interrupt on various state changes, including card insertion/removal and activity detection. 26

33 PC Card Software CompactFlash Software: US Software Corp. is supporting a file system software USFiles TM which provides PC compatible file system for Hitachi CompactFlash card to transfer data/program files between cards and the host system. USFiles TM supports US Software s real time OS MUltiTask as well as other vendors real time OS. USFiles TM has the following features: 100% C language. Support ROM & Reentrant Structure: Runs under multitask environment Source code available ANSI functions are used in API. Code size is compact: about 14kB (11.5kB except print) AI Corporation is providing CompactFlash drive software which supports True-IDE mode of operation. The CF drive software has the following feature: 100% C language Source code available Support card insertion/removal with the help of hardware detection mechanism for the card s existence and for the card change event notification Less components for system interface design with True IDE mode 27

34 Appendices True-IDE Mode Interface Example The following figures and tables show the example of the True-IDE Mode Interface implementation. 28

35 MPU PC-ATA/CF Card A0-3 A0-2 Add. Bus A0-2 A3 -CS WR/RD Interface Logic -CE1 7 -CE2 32 -IORD 34 -IOWR 35 -CE1 -CE2 -IORD -IOWR Bus CLK RESET -WAIT -INTRQ -IOIS16 DO-7/15 DO-7/15 A3-10 GND 1k 1,50 GND 0.1uF + 1.0uF 1k 1k CSEL -ATASEL Vcc 13,38 Vcc 1k 1k WE -REG *Master Mode Fig. 4 Interface Block Diagram 29

36 Table 17. True-IDE Mode I/O Decoding Fig. 5 Interface Logic Circuitry Offset Register Mode WR/RD A3 A2 A1 A0 Access 0 Data Read H R/W Write L 1 Error Read H Read only Feature Write L Write only 2 Sector Count Read H R/W Write L 3 Sector Number Read H R/W Write L 4 Cylinder Low Read H R/W Write L 5 Cylinder High Read H R/W Write L 6 Drive/Head Read H R/W Write L 7 Status Read H Read only Command Write L Write only 8 Alt Status Read H Read only Drive Control Write L Write only 9 Drive Address Read H Read only Reserved Write L Write only 30

37 Fig. 6 True-IDE Interface Timing Waveform PC Card Socket Controller Set up Example The following example is a PC Card socket controller setup for use with Hitachi s Flash PC Card. The PC-ATA and CF Card has four possible configurations for address space assignments. They are Memory mapped, I/O mapped AT Primary addresses, I/O mapped AT Secondary addresses and I/O mapped contiguous addresses. The PC Card socket controller is first setup for PC Card Register Memory Access which enable the host to read the card s CIS, and then select the configuration for the interface from the four possible address space assignments. Some values shown in the following example may not be applicable to all systems. The name of the PC Card socket controller s Registers are based on Intel s PCIC 82365SL. 1. Setup of PCIC Registers for PC Card Register Memory Access Register Name Register Index 1. Power and RESETDRV Control 02h 2. System Memory Address 0 Mapping Start Low Byte 10h 31

38 3. System Memory Address 0 Mapping Start High Byte 11h 4. System Memory Address 0 Mapping Stop Low Byte 12h 5. System Memory Address 0 Mapping Stop High Byte 13h 6. Card Memory Offset Address 0 Low Byte 14h 7. Card Memory Offset Address 0 High Byte 15h 8. Address Window Enable 06h The above Registers are used to setup an interface for PC Card Register Memory Access as follows: Register Index Value Comment 02h FAh Enable Vcc:5V, Vpp:12 Disable RESETDRV 10h C8h 0C8000 system start page for Register Memory 11h 80h 0C8000 system start page, 16bit, with wait state 12h C8h 0C8000 system end page for Register Memory 13h 80h 0C8000 system end page, 2 wait states 14h 38h 00C8000 card base page=0 15h 43h 00C8000 card base page=0, Register space access 06h 21h Enable memory window 0 2.Setup of PCIC Registers for Memory mapped configuration Register Name Register Index 1. System Memory Address 1 Mapping Start Low Byte 18h 2. System Memory Address 1 Mapping Start High Byte 19h 3. System Memory Address 1 Mapping Stop Low Byte 1Ah 4. System Memory Address 1 Mapping Stop HIGH Byte 1Bh 5. Card Memory Offset Address 0 Low Byte 14h 6. Card Memory Offset Address 0 High Byte 15h 7. Address Window Enable 06h The above Registers are used to set up an interface for PC Card Common Memory Access as follows: 32

39 Register Index Value Comment 18h C9h 0C9000 system start page for Common Memory 19h 80h 0C9000 system start page, 16bit, with wait state 1Ah C9h 0C9000 system end page for Common Memory 1Bh 80h 0C9000 system end page, 2 wait states 14h 37h 00C9000 card base page=0 15h 03h 00C9000 card base page=0, Common space access 06h 23h Enable memory windows 0,1 3.Setup of PCIC Registers for I/O mapped configuration Register Name Register Index 1. I/O Address 0 Start Low Byte 08h 2. I/O Address 0 Start High Byte 09h 3. I/O Address 0 Stop Low Byte 0Ah 4. I/O Address 0 Stop High Byte 0Bh 5. I/O Address 1 Start Low Byte 0Ch 6. I/O Address 1 Start High Byte 0Dh 7. I/O Address 1 Stop Low Byte 0Eh 8. I/O Address 1 Stop High Byte 0Fh 9. I/O Control 07h 10 Address Window Enable 06h 11. Configuration and Status C800:202h 12. Pin Placement C800:204h 13. Socket and Copy C800:206h 14. Configuration Option C800:200h 15. Interrupt and General Control 03h The above Registers are used to setup an interface for PC Card Common Memory Access as follows: 33