SST CompactFlash Card SST48CF008 / SST48CF016 / SST48CF024 / SST48CF032 / SST48CF048 / SST48CF064 / SST48CF096

Transcription

1 FEATURES: CompactFlash Association specification standard,,,,, and MByte densities Small Form Factor:. mm x. mm x. mm Supports.0-Volt and.-volt Read and Write V ± 0%,.V ± % for commercial PC Card ATA and True IDE interface Bytes sector ATA command set compatible Low Power Consumption: Active mode: 0 ma/0 ma (.V/.0V) Sleep mode: 0 µa/0 µa (.V/.0V) Data Transfer Rate to/from Host 0 MB/s burst at.0v. MB/s burst at.v High Performance Up to. MByte/sec sustained write transfer rate (host to flash) Controller Overhead Command to DRQ Less than 0. ms Zero Data Retention Power Batteries not required for data storage Product Description SST s CompactFlash (CF) card is an ultra-small, low cost, high performance, removable flash memory data storage system. This technology is well suited for solid state mass storage portable applications offering new and expanded functionality while enabling smaller and lighter designs. CompactFlash technology is widely used in a variety of consumer products such as portable computers, digital cameras, handheld data collection scanners, Personal Digital Assistants (PDAs), handy terminals, audio players, monitoring devices and set-top boxes. Start Up Time Sleep to Read: 00 ns Sleep to Write: 00 ns Reset to Ready: 0 ms typical, 00 ms Max. Support for Commercial Temperature Range 0 C to +0 C for operating commercial - C to + C non-operating (storage) commercial Extremely Rugged and Reliable Built-in ECC support corrects random Bytes error per Byte sector Up to,000,000 Sector Program/Erase cycles 000 G operating and non-operating shock Greater than,000,000 hours MTBF Intelligent ATA/IDE Controller Built-in microcontroller with intelligent firmware Bytes of attribute memory for storing CIS information Supports multiple-sector Read/Write operation to enhance system performance - Up to sectors per transfer block Power Management Unit Immediate disabling of unused circuitry SST s CompactFlash products provide complete PCMCIA-ATA functionality and compatibility. This is achieved because the 0-pin CF card can be easily slipped into a passive pin Type II adapter card that fully meets PCMCIA electrical and mechanical interface specifications. SST s CompactFlash products are also fully compliant with CFA standards. The SST High Density CF card is read and written to using a single power supply of.0-volts or.-volts and is available in to MByte densities. SST s CompactFlash cards contain additional attribute memory of Bytes for storing the Card Information Structure (CIS) information. SST s CompactFlash card has built in microcontroller and file management firmware that communicates with ATA standard interfaces; therefore, the SST s CompactFlash cards do not require additional software for the host, such as Flash File System (FFS) and Memory Technology Driver (MTD). 0 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. SST is an authorized licensee of the CompactFlash and CF[logo] -0 / trademarks. Some data and tables are reproduced from the CompactFlash Specification by permission of the CompactFlash Association. These specifications are subject to change without notice.

2 Contents SST CompactFlash Card Product Description... Contents....0 General Description.... Optimized for performance ATA Controller..... Microcontroller Unit (MCU)..... KBxx Dual Port SRAM..... Direct Memory Access (DMA) Control..... Power Management Unit (PMU).... SST s CompactFlash Card Product Offering....0 Electrical Interface Pin Assignment and Pin Type.... Electrical Description.... Card Pin Assignment.... Electrical Specification..... Input Leakage Current..... Input Characteristics..... Output Drive Characteristics..... Output Drive Type..... Interface/Bus Timing..... Attribute Memory Read Timing Specification..... Configuration Register (Attribute Memory) Write Timing Specification..... Common Memory Read Timing Specification..... Common Memory Write Timing Specification I/O Input (Read) Timing Specification..... I/O Output (Write) Timing Specification True IDE Mode I/O Input (Read) Timing Specification..... True IDE Mode I/O Output (Write) Timing Specification.... Card Configuration..... Attribute Memory Function..... Configuration Option Register (Address 00h in Attribute Memory)..... Card Configuration and Status Register (Address 0h in Attribute Memory)..... Pin Replacement Register (Address 0h in Attribute Memory)..... Socket and Copy Register (Address 0h in Attribute Memory).... I/O Transfer Function..... I/O Function.... Common Memory Transfer Function..... Common Memory Function.... True IDE Mode I/O Transfer Function..... True IDE Mode I/O Function....0 Software Interface...0. CF-ATA Drive Register Set Definition and Protocol I/O Primary and Secondary Address Configurations..... Contiguous I/O Mapped Addressing..... Memory Mapped Addressing...

3 .. True IDE Mode Addressing..... CF-ATA Registers Data Register (Address - F0h[0h];Offset 0,,) Error Register (Address - Fh[h]; Offset, 0Dh Read Only) Feature Register (Address - Fh[h]; Offset, 0Dh Write Only) Sector Count Register (Address - Fh[h]; Offset ) Sector Number (LBA -0) Register (Address - Fh[h]; Offset ) Cylinder Low (LBA -) Register (Address - Fh[h]; Offset ) Cylinder High (LBA -) Register (Address - Fh[h]; Offset ) Drive/Head (LBA -) Register (Address Fh[h]; Offset ) Status & Alternate Status Registers (Address Fh[h]&Fh[h]; Offsets & Eh) Device Control Register (Address - Fh[h]; Offset Eh) Card (Drive) Address Register (Address Fh[h]; Offset Fh).... CF-ATA Command Description..... CF-ATA Command Set Check Power Mode - h or Eh Execute Drive Diagnostic - 0h Erase Sector(s) - C0h Format Track - 0h Identify Drive - ECh General Configuration Default Number of Cylinders Default Number of Heads Number of Unformatted Bytes per Track Number of Unformatted Bytes per Sector Default Number of Sectors per Track Number of Sectors per Card Memory Card Serial Number Buffer Type Buffer Size ECC Count Firmware Revision Model Number Read/Write Multiple Sector Count Double Word Support Capabilities PIO Data Transfer Cycle Timing Mode DMA Data Transfer Cycle Timing Mode Translation Parameters Valid Current Number of Cylinders, Heads, Sectors/Track Current Capacity Multiple Sector Setting Total Sectors Addressable in LBA Mode Idle - h or Eh Idle Immediate - h or Eh Initialize Drive Parameters - h Read Buffer - Eh... 0

4 ...0 Read Multiple - Ch Read Long Sector - h or h Read Sector(s) - 0h or h Read Verify Sector(s) - 0h or h Recalibrate - h Request Sense - 0h Seek - h Set Features - EFh Set Multiple Mode - Ch Set Sleep Mode- h or Eh Standby - h or Eh Standby Immediate - h or E0h Translate Sector - h Wear Level - Fh Write Buffer - Eh Write Long Sector - h or h Write Multiple Command - Ch Write Multiple without Erase - CDh Write Sector(s) - 0h or h Write Sector(s) without Erase - h Write Verify - Ch..... Error Posting....0 Appendix.... Differences between CF-ATA and PC Card-ATA/True IDE..... Electrical Differences TTL Compatibility Pull Up Resistor Input Leakage Current..... Functional Differences Set Features Codes not Supported Additional Set Features Codes in CF-ATA Additional Commands in CF-ATA Idle Timer Recovery from Sleep Mode....0 Physical Dimensions... Ordering Information... Valid combinations... Limited Warranty... Life Support Policy... Patent Protection... PCMCIA Standard... CompactFlash Specification... Related Documents... Sales Offices...

5 .0 General Description The SST s CompactFlash card contains a controller, firmware storage and flash media in a matchbook sized package with a 0-pin connector consisting of two rows of female contacts each on 0 mil (. mm) centers. Refer to Figure - for SST s CompactFlash card block diagram. The controller interfaces with the host system allowing data to be written to and read from the flash media.. Optimized for performance ATA Controller The heart of a CompactFlash card is the ATA controller which translates standard IDE/ATA signals into Flash media data and controls. SST s CompactFlash card contains a proprietary ATA controller that was specifically designed to attain high data throughput from host to Flash. The following components contribute to the ATA controller s performance... Microcontroller Unit (MCU) The MCU translates IDE/ATA commands into data and control signals required for flash memory operation... xx Dual Port SRAM A key contributor to the ATA controller performance is a dual port SRAM buffer. It permits the host to simultaneously transfer data to the CompactFlash card while the buffer is writing to flash memory... Direct Memory Access (DMA) Control The ATA controller inside SST s CompactFlash card uses DMA allowing instant data transfer to memory. This implementation eliminates controller overhead associated with traditional, firmware based, memory control... Power Management Unit (PMU) Power Management Unit controls the power consumption of the CompactFlash card. The PMU dramatically extends product battery life by putting the part of the circuitry that is not in operation into sleep mode. ATA Controller HOST xx SRAM Buffer MCU Firmware Storage 0 DMA Control Flash Media PMU ILL-. FIGURE -: SST COMPACTFLASH CARD BLOCK DIAGRAM

6 . SST s High Density CompactFlash Card Product Offering The SSTCFxxx High Density CompactFlash product family is available in to MByte densities. The following table shows the specific capacity, default number of cylinder heads, sectors and cylinders for each product line. Model Number Density Total Bytes Cylinders Heads Sectors CF00 MB,0,0 CF0 MB,0, CF0 MB,0, CF0 MB,0,0 CF0 MB,0, CF0 MB,0, CF0 MB,0,.0 Electrical Interface.0. Pin Assignment and Pin Type The signal/pin assignments are listed in Table -. Low active signals have a - prefix. Pin types are Input, Output or Input/Output. Section. defines the DC characteristics for all input and output type structures.. Electrical Description The CompactFlash card functions in three basic modes: ) PC Card ATA using I/O Mode, ) PC Card ATA using Memory Mode and ) True IDE Mode, which is compatible with most disk drives. The configuration of the CompactFlash card will be controlled using the standard PCMCIA configuration registers starting at address 00h in the Attribute Memory space of the storage card or for True IDE Mode, pin being grounded. Table - describes the I/O signals. Signals whose source is the host are designated as inputs while signals that the CompactFlash card sources are outputs. The CompactFlash card logic levels conform to those specified in the PCMCIA Release. and CFA Specification Rev... As shown in Table -, each signal has three possible operating modes: ) PC Card Memory, ) PC Card I/O and ) True IDE. All outputs from the card are totempole except the data bus signals which are bidirectional tri-state. Refer to section. for definitions of Input and Output type.

7 . Card Pin Assignment TABLE -: CARD PIN ASSIGNMENT Memory card mode I/O card mode True IDE mode Pin NO. Signal Pin I/O Signal Pin I/O Signal Pin I/O Name Type Type* Name Type Type* Name Type Type* GND GND GND GND GND GND D I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O -CE I IU -CE I IU -CS0 I IU A0 I ID A0 I ID A0 I ID -OE I IU -OE I IU -ATASEL I IU 0 A I ID A I ID A I ID A I ID A I ID A I ID A I ID A I ID A I ID V CC V CC V CC A I ID A I ID A I ID A I ID A I ID A I ID A I ID A I ID A I ID A I ID A I ID A I ID A I ID A I ID A I ID A I ID A I ID A I ID 0 A0 I ID A0 I ID A0 I ID D0 I/O ID, O D0 I/O ID, O D0 I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O WP O O -IOIS O O -IOIS O O -CD O Ground -CD O Ground -CD O Ground -CD O Ground -CD O Ground -CD O Ground D I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O 0 D I/O ID, O D I/O ID, O D I/O ID, O * Please refer to Sections.. to.. for detail. 0

8 TABLE -: CARD PIN ASSIGNMENT (CONTINUED) Memory card mode I/O card mode True IDE mode Pin NO. Signal Pin I/O Signal Pin I/O Signal Pin I/O Name Type Type* Name Type Type* Name Type Type* D I/O ID, O D I/O ID, O D I/O ID, O -CE I IU -CE I IU -CS I IU -VS O Ground -VS O Ground -VS O Ground -IORD I IU -IORD I IU -IORD I IU -IOWR I IU -IOWR I IU -IOWR I IU -WE I IU -WE I IU -WE I IU RDY/-BSY O O -IREQ O O INTRQ O O V CC V CC V CC -CSEL I IU -CSEL I IU -CSEL I IU 0 -VS O open -VS O open -VS O open RESET I IU RESET I IU -RESET I IU -WAIT O O -WAIT O O IORDY O O -INPACK O O -INPACK O O -INPACK O O -REG I IU -REG I IU -REG I IU BVD O IU, O -SPKR O IU, O -DASP O IU, O BVD O IU, O -STSCHG O IU, O -PDIAG O IU, O D I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O D I/O ID, O D0 I/O ID, O D0 I/O ID, O D0 I/O ID, O 0 GND GND GND GND GND GND * Please refer to Sections.. to.. for detail.

9 TABLE -: SIGNAL DESCRIPTION Symbol Type* Pin Name and Functions A0 - A0 I,0,,, These address lines along with the -REG signal are used to (PC Card Memory Mode),,,, select the following: The I/O port address registers within the,,0 CompactFlash card, the memory mapped port address registers within the CompactFlash card, a byte in the card s information structure and its configuration control and status registers. A0 - A0 This signal is the same as the PC Card Memory Mode signal. (PC Card I/O Mode) A - A0 I,,0 In True IDE Mode only A[:0] are used to select the one of eight (True IDE Mode) registers in the Task File, the remaining address lines should be grounded by the host. BVD I/O This signal is asserted high as the BVD signal since a battery (PC Card Memory Mode) is not used with this product. -STSCHG This signal is asserted low to alert the host to changes in the (PC Card I/O Mode) RDY/-BSY and Write Protect states, while the I/O interface is Status Changed configured. Its use is controlled by the Card Config and Status Register. -PDIAG In the True IDE Mode, this input/output is the Pass Diagnostic (True IDE Mode) signal in the Master/Slave handshake protocol. BVD I/O This output line is always driven to a high state in Memory Mode (PC Card Memory Mode) since a battery is not required for this product. -SPKR This output line is always driven to a high state in I/O Mode (PC Card I/O Mode) since this product does not support the audio function. -DASP In the True IDE Mode, this input/output is the Disk Active/Slave (True IDE Mode) Present signal in the Master/Slave handshake protocol. -CD, -CD O, These Card Detect pins are connected to ground on the (PC Card Memory Mode) CompactFlash card. They are used by the host to determine that the CompactFlash card is fully inserted into its socket. -CD, -CD This signal is the same for all modes. (PC Card I/O Mode) -CD, -CD This signal is the same for all modes. (True IDE Mode) -CE, -CE I, These input signals are used both to select the card and to (PC Card Memory Mode) indicate to the card whether a byte or a word operation is being Card Enable performed. -CE always accesses the Odd Byte of the word. -CE accesses the Even Byte or the Odd Byte of the word depending on A0 and -CE. A multi-plexing scheme based on A0, -CE, -CE allows bit hosts to access all data on D0-D. See Tables -, -, -, - and -. -CE, -CE This signal is the same as the PC Card Memory Mode signal. (PC Card I/O Mode) Card Enable -CS0, -CS In the True IDE Mode CS0 is the chip select for the task file (True IDE Mode) registers while CS is used to select the Alternate Status Register and the Device Control Register. 0

10 TABLE -: SIGNAL DESCRIPTION (CONTINUED) Symbol Type* Pin Name and Functions -CSEL I This signal is not used for this mode. (PC Card Memory Mode) -CSEL This signal is not used for this mode. (PC Card I/O Mode) -CSEL This internally pulled up signal is used to configure this device (True IDE Mode) as a Master or a Slave when configured in the True IDE Mode. When this pin is grounded, this device is configured as a Master. When the pin is open, this device is configured as a Slave. D - D00 I/O,0,,, These lines carry the Data, Commands and Status information (PC Card Memory Mode),,,, between the host and the controller. D00 is the LSB of the Even,,,,, Byte of the Word. D0 is the LSB of the Odd Byte of the Word.,, D - D00 This signal is the same as the PC Card Memory Mode signal. (PC Card I/O Mode) D - D00 In True IDE Mode, all Task File operations occur in Byte-Mode (True IDE Mode) on the low order bus D00-D0 while all data transfers are bit using D00-D. GND,0 Ground. (PC Card Memory Mode) GND This signal is the same for all modes. (PC Card I/O Mode) GND This signal is the same for all modes. (True IDE Mode) -INPACK O This signal is not used in this mode. ( PC Card Memory Mode) -INPACK The Input Acknowledge signal is asserted by the CompactFlash ( PC Card I/O Mode) Card when the card is selected and responding to an Input Acknowledge I/O read cycle at the address that is on the address bus. This signal is used by the host to control the enable of any input data buffers between the CompactFlash card and the CPU. -INPACK In True IDE Mode this output signal is not used and should not (True IDE Mode) be connected at the host. -IORD I This signal is not used in this mode. (PC Card Memory Mode) -IORD This is an I/O Read strobe generated by the host. This signal (PC Card I/O Mode) gates I/O data onto the bus from the CompactFlash Card when the card is configured to use the I/O interface. -IORD In True IDE Mode, this signal has the same function as in PC (True IDE Mode) Card I/O Mode. -IOWR I This signal is not used in this mode. (PC Card Memory Mode) -IOWR The I/O Write strobe pulse is used to clock I/O data on the Card (PC Card I/O Mode) Data bus into the CompactFlash card controller registers when the CompactFlash card is configured to use the I/O interface. The clocking will occur on the negative to positive edge of the signal (trailing edge). -IOWR In True IDE Mode, this signal has the same function as in PC (True IDE Mode) Card I/O Mode. 0

11 TABLE -: SIGNAL DESCRIPTION (CONTINUED) Symbol Type* Pin Name and Functions -OE I This is an Output Enable strobe generated by the host interface. (PC Card Memory Mode) It is used to read data from the CompactFlash card in Memory Mode and to read the CIS and configuration registers. -OE In PC Card I/O Mode, this signal is used to read the CIS and (PC Card I/O Mode) configuration registers. -ATA SEL To enable True IDE Mode this input should be grounded by the (True IDE Mode) host. RDY/-BSY O In Memory Mode this signal is set high when the CompactFlash (PC Card Memory Mode) Card is ready to accept a new data transfer operation and held low when the card is busy. The Host memory card socket must provide a pull-up resistor. At power up and at Reset, the RDY/-BSY signal is held low (busy) until the CompactFlash card has completed its power up or reset function. No access of any type should be made to the CompactFlash card during this time. The RDY/-BSY signal is held high (disabled from being busy) whenever the following condition is true: The CompactFlash Card has been powered up with +RESET continuously disconnected or asserted. -IREQ I/O Operation - After the CompactFlash card has been ( PC Card I/O Mode) configured for I/O operation, this signal is used as Interrupt Request. This line is strobed low to generate a pulse mode interrupt or held low for a level mode interrupt. INTRQ In True IDE Mode signal is the active high Interrupt Request to (True IDE Mode) the host. -REG I This signal is used during Memory Cycles to distinguish (PC Card Memory Mode) between Common Memory and Register (Attribute) Memory Attribute Memory Select accesses. High for Common Memory, Low for Attribute Memory. -REG The signal must also be active (low) during I/O Cycles when the (PC Card I/O Mode) I/O address is on the Bus. -REG In True IDE Mode this input signal is not used and should be (True IDE Mode) connected to V CC by the host. RESET I When the pin is high, this signal Resets the CompactFlash (PC Card Memory Mode) Card. The CompactFlash card is Reset only at power up if this pin is left high or open from power-up. The CompactFlash card is also Reset when the Soft Reset bit in the Card Configuration Option Register is set. RESET This signal is the same as the PC Card Memory Mode signal. (PC Card I/O Mode) -RESET In the True IDE Mode this input pin is the active low hardware (True IDE Mode) reset from the host. VCC, +.0V, +.V power. (PC Card Memory Mode) VCC This signal is the same for all modes. (PC Card I/O Mode) VCC This signal is the same for all modes. (True IDE Mode) 0

12 TABLE -: SIGNAL DESCRIPTION (CONTINUED) Symbol Type* Pin Name and Functions -VS O Voltage Sense Signals. -VS is grounded so that the -VS 0 CompactFlash card CIS can be read at. volts and (PC Card Memory Mode) -VS is reserved by PCMCIA for a secondary voltage. -VS This signal is the same for all modes. -VS (PC Card I/O Mode) -VS This signal is the same for all modes. -VS (True IDE Mode) -WAIT O The -WAIT signal is driven low by the CompactFlash (PC Card Memory Mode) Card to signal the host to delay completion of a memory or I/O cycle that is in progress. -WAIT This signal is the same as the PC Card Memory Mode signal. (PC Card I/O Mode) IORDY In True IDE Mode this output signal may be used as IORDY. (True IDE Mode) -WE I This is a signal driven by the host and used for strobing memory (PC Card Memory Mode) write data to the registers of the CompactFlash card when the card is configured in the memory interface mode. It is also used for writing the configuration registers. -WE In PC Card I/O Mode, this signal is used for writing the (PC Card I/O Mode) configuration registers. -WE In True IDE Mode this input signal is not used and should be (True IDE Mode) connected to V CC by the host. WP O Memory Mode - The CompactFlash card does not have (PC Card Memory Mode) a write protect switch. This signal is held low after the completion Write Protect of the reset initialization sequence. -IOIS I/O Operation - When the CompactFlash card is PC Card I/O Mode) configured for I/O Operation Pin is used for the -I/O Selected is Bit Port (-IOIS) function. A Low signal indicates that a bit or Odd Byte only operation can be performed at the addressed port. -IOIS In True IDE Mode this output signal is asserted low when this (True IDE Mode) device is expecting a word data transfer cycle. * I = Input O = Output

13 . Electrical Specification The following table defines all D.C. Characteristics for the SST CompactFlash card product family. Unless otherwise stated, conditions are: V CC =.0V ±0% Non operating (storage) temperature range - C to + C V CC =.V ± % T A = 0 C to 0 C ABSOLUTE MAIMUM CONDITIONS INPUT POWER Parameter Symbol Conditions Input Power V CC -0.V min. to.v max. Voltage on any pin except Vcc with respect to GND. V -0.V min. to V CC + 0.V max. Voltage Maximum Average RMS Current Measurement Method.V ± % ma.v at C.0V ± 0% 00 ma.0v at C Note : Current measurement is accomplished by connecting an amp meter (set to the amp scale range) in series with the Vcc supply to the CompactFlash card. Current measurements are to be taken while looping on a data transfer command with a sector count of. Current consumption values for both read and write commands are not to exceed the Maximum Average RMS Current specified in the above table. CompactFlash products shall operate correctly in both voltage ranges as shown in the table above. To comply with this specification, current requirements must not exceed the maximum limit... Input Leakage Current Note: In the table below, x refers to the characteristics described in section... For example, IU indicates a pull up resistor with a type input characteristic. Type Parameter Symbol Conditions MIN TYP MA Units IxZ Input Leakage Current IL Vih = Vcc / Vil = Gnd - µa IxU Pull Up Resistor RPU Vcc =.0V 0k 00k Ohm IxD Pull Down Resistor RPD Vcc =.0V 0k 00k Ohm.. INPUT CHARACTERISTICS Type Parameter Symbol MIN TYP MA MIN TYP MA Units V CC =.V V CC =.0V Input Voltage Vih..0 Volts CMOS Vil Input Voltage Vih..0 Volts TTL (compatible) Vil Input Voltage Vth..0 Volts CMOS Vtl.0.0 Schmitt Trigger Note : Per PCMCIA Electrical Specification Signal Interface Table - note, the host must provide a logic output high voltage for a CMOS load of. x VCC. For a volt product, this translates to. x. =.0 volts minimum Voh. 0

14 .. Output Drive Type All output drive type are CMOS level... OUTPUT DRIVE CHARACTERISTICS Type Parameter Symbol Conditions MIN TYP MA Units O Output Voltage Voh Ioh = - ma Vcc Volts -0.V Vol Iol = ma Gnd +0.V O Output Voltage Voh Ioh = - ma Vcc Volts -0.V Vol Iol = ma Gnd +0.V

15 .. Interface/Bus Timing There are two types of bus cycles and timing sequences that occur in the PCMCIA type interface, a direct mapped I/O transfer and a memory access. The two timing sequences are explained in detail in the PCMCIA PC Card Standard. SST s CompactFlash card conforms to the timing in that reference document... Attribute Memory Read Timing Specification The Attribute Memory access time is defined as 00 ns. Detailed timing specifications are shown in Table -. TABLE -: ATTRIBUTE MEMORY READ TIMING Speed Version 00 ns Item Symbol IEEE Symbol Min ns Max ns Read Cycle Time tc(r) tavav 00 Address Access Time ta(a) tavqv 00 Card Enable Access Time ta(ce) telqv 00 Output Enable Access Time ta(oe) tglqv 0 Output Disable Time from CE tdis(ce) tehqz 0 Output Disable Time from OE tdis(oe) tghqz 0 Address Setup Time tsu (A) tavgl 0 Output Enable Time from CE ten(ce) telqnz Output Enable Time from OE ten(oe) tglqnz Data Valid from Address Change tv(a) taq 0 Notes: All times are in nanoseconds. Dout signifies data provided by the CompactFlash card to the system. The -CE signal or both the - OE signal and the -WE signal must be de-asserted between consecutive cycle operations. tc(r) 0 An -REG ta(a) -CE ten(ce) tsu(a) ta(ce) tv(a) tdis(ce) -OE Dout ten(oe) ta(oe) Dout tdis(oe) ILL-.0 FIGURE -: ATTRIBUTE MEMORY READ TIMING DIAGRAM

16 .. Configuration Register (Attribute Memory) Write Timing Specification The Card Configuration write access time is defined as 00 ns. Detailed timing specifications are shown in Table -. TABLE - CONFIGURATION REGISTER (ATTRIBUTE MEMORY) WRITE TIMING Speed Version 00 ns Item Symbol IEEE Symbol Min ns Max ns Write Cycle Time tc(w) tavav 00 Write Pulse Width tw(we) twlwh 0 Address Setup Time tsu(a) tavwl 0 Write Recovery Time trec(we) twma Data Setup Time for WE tsu(d-weh) tdvwh 0 Data Hold Time th(d) twmd Notes: All times are in nanoseconds. Din signifies data provided by the system to the CompactFlash card. -Reg tc(w) An -WE tsu(a) tw(we) trec(we) -CE tsu(d-weh) th(d) -OE Din Din Valid ILL-.0 FIGURE -: CONFIGURATION REGISTER (ATTRIBUTE MEMORY) WRITE TIMING DIAGRAM

17 .. Common Memory Read Timing Specification TABLE -: COMMON MEMORY READ TIMING Item Symbol IEEE Symbol Min ns Max ns Output Enable Access Time ta(oe) tglqv 0 Output Disable Time from OE tdis(oe) tghqz 0 Address Setup Time tsu(a) tavgl 0 Address Hold Time th(a) tgha CE Setup before OE tsu(ce) telgl 0 CE Hold following OE th(ce) tgheh An -REG tsu(a) th(a) -CE tsu(ce) th(ce) -OE ta(oe) Dout Dout tdis(oe) 0 ILL-.0 FIGURE -: COMMON MEMORY READ TIMING DIAGRAM

18 .. Common Memory Write Timing Specification TABLE -: COMMON MEMORY WRITE TIMING Item Symbol IEEE Symbol Min ns Max ns Data Setup before WE tsu(d-weh) tdvwh 0 Data Hold following WE th(d) twmd WE Pulse Width tw(we) twlwh 0 Address Setup Time tsu(a) tavwl 0 CE Setup before WE tsu(ce) telwl 0 Write Recovery Time trec(we) twma Address Hold Time th(a) tgha CE Hold following WE th(ce) tgheh An tsu(a) th(a) -REG -CE tsu(ce) th(ce) -WE tw(we) trec(we) Din tsu(d-weh) Din Valid th(d) ILL-.0 FIGURE -: COMMON MEMORY WRITE TIMING DIAGRAM

19 ..0 I/O Input (Read) Timing Specification TABLE -: I/O READ TIMING Item Symbol IEEE Symbol Min ns Max ns Data Delay after IORD td(iord) tlglqv 00 Data Hold following IORD th(iord) tlghq 0 IORD Width Time tw(iord) tlgligh Address Setup before IORD tsua(iord) tavigl 0 Address Hold following IORD tha(iord) tlgha 0 CE Setup before IORD tsuce(iord) teligl CE Hold following IORD thce(iord) tlgheh 0 REG Setup before IORD tsureg(iord) trgligl REG Hold following IORD threg(iord) tlghrgh 0 INPACK Delay Falling from IORD tdfinpack(iord) tlglial 0 INPACK Delay Rising from IORD tdrinpack(iord) tlghiah IOIS Delay Falling from Address tdfiois(adr) tavisl IOIS Delay Rising from Address tdriois(adr) tavish Notes: The maximum load on -INPACK and -IOIS is LSTTL with 0pF total load. All times are in nanoseconds. An -REG tsua(iord) tsureg(iord) tha(iord) threg(iord) 0 -CE -IORD -INPACK -IOIS Dout tdfiois(adr) tsuce(iord) tw(iord) tdfinpack(iord) td(iord) Dout thce(iord) tdrinpack(iord) tdriois(adr) th(iord) ILL-.0 FIGURE -: I/O READ TIMING DIAGRAM

20 .. I/O Output (Write) Timing Specification TABLE -: I/O WRITE TIMING Item Symbol IEEE Symbol Min ns Max ns Data Setup before IOWR tsu(iowr) tdviwh 0 Data Hold following IOWR th(iowr) tlwhd 0 IOWR Width Time tw(iowr) tlwliwh Address Setup before IOWR tsua(iowr) taviwl 0 Address Hold following IOWR tha(iowr) tlwha 0 CE Setup before IOWR tsuce(iowr) teliwl CE Hold following IOWR thce(iowr) tlwheh 0 REG Setup before IOWR tsureg(iowr) trgliwl REG Hold following IOWR threg(iowr) tlwhrgh 0 IOIS Delay Falling from Address tdfiois(adr) tavisl IOIS Delay Rising from Address tdriois(adr) tavish Notes: The maximum load on -INPACK, and -IOIS is LSTTL with 0pF total load. All times are in nanoseconds. An -REG tsua(iowr) tsureg(iowr) tha(iowr) threg(iowr) -CE -IOWR tsuce(iowr) tw(iowr) thce(iowr) tdriois(adr) -IOIS Din tdfiois(adr) tsu(iowr) Din Valid th(iowr) ILL-.0 FIGURE -: I/O WRITE TIMING DIAGRAM 0

21 .. True IDE Mode I/O Input (Read) Timing Specification TABLE -: TRUE IDE MODE I/O READ TIMING Item Symbol IEEE Symbol Min ns Max ns Data Delay after IORD td(iord) tlglqv 00 Data Hold following IORD th(iord) tlghq 0 IORD Width Time tw(iord) tlgligh Address Setup before IORD tsua(iord) tavigl 0 Address Hold following IORD tha(iord) tlgha 0 CE Setup before IORD tsuce(iord) teligl CE Hold following IORD thce(iord) tlgheh 0 IOIS Delay Falling from Address tdfiois(adr) tavisl IOIS Delay Rising from Address tdriois(adr) tavish Notes: The maximum load on -IOIS is LSTTL with 0pF total load. All times are in nanoseconds. An -CE tsua(iord) tsuce(iord) tha(iord) thce(iord) -IORD tw(iord) tdriois(adr) 0 -IOIS tdfiois(adr) td(iord) th(iord) Dout Dout ILL-.0 FIGURE -: TRUE IDE MODE I/O READ TIMING DIAGRAM

22 .. True IDE Mode I/O Output (Write) Timing Specification TABLE -0 TRUE IDE MODE I/O WRITE TIMING Item Symbol IEEE Symbol Min ns Max ns Data Setup before IOWR tsu(iowr) tdviwh 0 Data Hold following IOWR th(iowr) tlwhd 0 IOWR Width Time tw(iowr) tlwliwh Address Setup before IOWR tsua(iowr) taviwl 0 Address Hold following IOWR tha(iowr) tlwha 0 CE Setup before IOWR tsuce(iowr) teliwl CE Hold following IOWR thce(iowr) tlwheh 0 IOIS Delay Falling from Address tdfiois(adr) tavisl IOIS Delay Rising from Address tdriois(adr) tavish Notes: The maximum load on -IOIS is LSTTL with 0pF total load. All times are in nanoseconds. An -CE -IORD tsua(iowr) tsuce(iowr) tw(iowr) tha(iowr) thce(iowr) tdriois(adr) -IOIS tdfiois(adr) tsu(iowr) th(iowr) Din Din Valid ILL-.0 FIGURE -: TRUE IDE MODE I/O WRITE TIMING DIAGRAM

23 . Card Configuration The CompactFlash cards are identified by appropriate information in the Card Information Structure (CIS). The following configuration registers are used to coordinate the I/O spaces and the Interrupt level of cards that are located in the system. In addition, these registers provide a method for accessing status information about the CompactFlash card that may be used to arbitrate between multiple interrupt sources on the same interrupt level or to replace status information that appears on dedicated pins in memory cards that have alternate use in I/O cards. TABLE -: REGISTERS AND MEMORY SPACE DECODING -CE -CE -REG -OE -WE A0 A A-A A A A A0 SELECTED SPACE Standby Configuration Registers Read 0 0 Common Memory Read ( bit D-D0) 0 0 Common Memory Read ( bit D-D) Common Memory Read ( bit D-D0) Configuration Registers Write 0 0 Common Memory Write ( bit D-D0) 0 0 Common Memory Write ( bit D-D) Common Memory Write ( bit D-D0) Card Information Structure Read Invalid Access (CIS Write) Invalid Access (Odd Attribute Read) Invalid Access (Odd Attribute Write) Invalid Access (Odd Attribute Read) Invalid Access (Odd Attribute Write) CONFIGURATION REGISTERS DECODING -CE -CE -REG -OE -WE A0 A A-A A A A A0 SELECTED REGISTER Configuration Option Reg Read Configuration Option Reg Write Card Status Register Read Card Status Register Write Pin Replacement Register Read Pin Replacement Register Write Socket and Copy Register Read Socket and Copy Register Write Note: The location of the card configuration registers should always be read from the CIS locations 0000h to 0h. No writes should be performed to the CompactFlash card attribute memory except to the card configuration register addresses. All other attribute memory locations are reserved. 0

24 .. Attribute Memory Function Attribute memory is a space where CompactFlash card identification and configuration information are stored, and is limited to -bit wide accesses only at even addresses. The card configuration registers are also located here. For the Attribute Memory Read function, signals -REG and -OE must be active and -WE inactive during the cycle. As in the Main Memory Read functions, the signals -CE and -CE control the Even Byte and Odd Byte address, but only the Even Byte data is valid during the Attribute Memory access. Refer to Table - below for signal states and bus validity for the Attribute Memory function. TABLE -: ATTRIBUTE MEMORY FUNCTION Function Mode -REG -CE -CE A0 A A0 -OE -WE D-D D-D0 Standby Mode H H High Z High Z Read Byte Access L H L L L L L H High Z Even Byte CIS ROM ( bits) Write Byte Access L H L L L L H L Don t Even Byte CIS ( bits) (Invalid) Care Read Byte Access L H L L H L L H High Z Even Byte Configuration ( bits) Write Byte Access L H L L H L H L Don t Even Byte Configuration ( bits) Care Read Word Access L L L L L L H Not Valid Even Byte CIS ( bits) Write Word Access L L L L L H L Don t Even Byte CIS ( bits) (Invalid) Care Read Word Access L L L L H L H Not Valid Even Byte Configuration ( bits) Write Word Access L L L L H H L Don t Even Byte Configuration ( bits) Care Note: The -CE signal or both the -OE signal and the -WE signal must be de-asserted between consecutive cycle operations... Configuration Option Register (Address 00h in Attribute Memory) The Configuration Option Register is used to configure the cards interface, address decoding and interrupt and to issue a soft reset to the CompactFlash card. Operation D D D D D D D D0 R/W SRESET LevlREQ Conf Conf Conf Conf Conf Conf0 SRESET Soft Reset - Setting this bit to one (), waiting the minimum reset width time and returning to zero (0) places the CompactFlash card in the Reset state. Setting this bit to one () is equivalent to assertion of the +RESET signal except that the SRESET bit is not cleared. Returning this bit to zero (0) leaves the CompactFlash card in the same un-configured Reset state as following power-up and hardware reset. This bit is set to zero (0) by power-up and hardware reset. Using the PCMCIA Soft Reset is considered a hard Reset by the ATA Commands. Contrast with Soft Reset in the Device Control Register. LevlREQ This bit is set to one () when Level Mode Interrupt is selected, and zero (0) when Pulse Mode is selected. Set to zero (0) by Reset.

25 Conf - Conf0 Configuration Index. Set to zero (0) by reset. It s used to select operation mode of the CompactFlash card as shown below. Note: Conf and Conf are reserved and must be written as zero (0) TABLE -: CARD CONFIGURATIONS Conf Conf Conf Conf Conf Conf0 Disk Card Mode Memory Mapped I/O Mapped, any Byte system decoded boundary I/O Mapped, F0h-Fh/Fh-Fh I/O Mapped, 0h-h/h-h.. Card Configuration and Status Register (Address 0h in Attribute Memory) The Card Configuration and Status Register contains information about the card s condition. CARD CONFIGURATION AND STATUS REGISTER ORGANIZATION: Operation D D D D D D D D0 Read Changed SigChg IOis 0 0 PwrDwn Int 0 Write 0 SigChg IOis 0 0 PwrDwn 0 0 Changed Indicates that one or both of the Pin Replacement register CRdy or CWProt bits are set to one (). When the Changed bit is set, Pin (-STSCHG) is held low if the SigChg bit is a One () and the CompactFlash card is configured for the I/O interface. SigChg This bit is set and reset by the host to enable and disable a state-change signal from the Status Register, the Changed bit control pin the Changed Status signal. If no state change signal is desired, this bit should be set to zero (0) and pin (-STSCHG) signal will be held high while the CompactFlash card is configured for I/O IOis The host sets this bit to a one () if the CompactFlash card is to be configured in an -bit I/O Mode. The CompactFlash card is always configured for both - and -bit I/O, so this bit is ignored. PwrDwn This bit indicates whether the host requests the CompactFlash card to be in the power saving or active mode. When the bit is one (), the CompactFlash card enters a power down mode. When zero (0), the host is requesting the CompactFlash card to enter the active mode. The PCMCIA Rdy/-Bsy value becomes BUSY when this bit is changed. Rdy/-Bsy will not become Ready until the power state requested has been entered. The CompactFlash card automatically powers down when it is idle and powers back up when it receives a command. Int This bit represents the internal state of the interrupt request. This value is available whether or not I/O interface has been configured. This signal remains true until the condition which caused the interrupt request has been serviced. If interrupts are disabled by the -IEN bit in the Device Control Register, this bit is a zero (0). 0

26 .. Pin Replacement Register (Address 0h in Attribute Memory) Operation D D D D D D D D0 Read 0 0 CRdy/-Bsy CWProt Rdy/-Bsy 0 Write 0 0 CRdy/-Bsy CWProt 0 0 MRdy/-Bsy CRdy/-Bsy This bit is set to one () when the bit RRdy/-Bsy changes state. This bit can also be written by the host. CWProt This bit is set to one () when the RWprot changes state. This bit may also be written by the host. Rdy/-Bsy This bit is used to determine the internal state of the Rdy/-Bsy signal. This bit may be used to determine the state of the Ready/- Busy as this pin has been reallocated for use as Interrupt Request on an I/O card. When written, this bit acts as a mask for writing the corresponding bit CRdy/-Bsy. MRdy/-Bsy This bit acts as a mask for writing the corresponding bit CRdy/-Bsy. This bit is ignored by the CompactFlash card. TABLE -: PIN REPLACEMENT CHANGED BIT/MASK BIT VALUES Initial Value Written by Host Final Comments of (C) Status C Bit M Bit C Bit Unchanged 0 Unchanged 0 0 Cleared by Host Set by Host.. Socket and Copy Register (Address 0h in Attribute Memory) This register contains additional configuration information. This register is always written by the system before writing the card s Configuration Index Register. SOCKET AND COPY REGISTER ORGANIZATION: Operation D D D D D D D D0 Read Reserved 0 0 Drive # Write Drive # Reserved This bit is reserved for future standardization. This bit must be set to zero (0) by the software when the register is written. Drive # This bit indicates the drive number of the card for twin card configuration. Twin card configuration is currently not supported. The socket number is ignored by the CompactFlash card.

27 . I/O Transfer Function.. I/O Function The I/O transfer to or from the CompactFlash card can be either or bits. When a -bit accessible port is addressed, the signal -IOIS is asserted by the CompactFlash card. Otherwise, the -IOIS signal is de-asserted. When a bit transfer is attempted, and the -IOIS signal is not asserted by the CompactFlash card, the system must generate a pair of -bit references to access the word s Even Byte and Odd Byte. The CompactFlash card permits both and bit accesses to all of its I/O addresses, so -IOIS is asserted for all addresses to which the CompactFlash card responds. TABLE -: I/O FUNCTION Function Code -REG -CE -CE A0 -IORD -IOWR D-D D-D0 Standby Mode H H High Z High Z Byte Input Access L H L L L H High Z Even Byte ( bits) L H L H L H High Z Odd Byte Byte Output Access L H L L H L Don t Care Even Byte ( bits) L H L H H L Don t Care Odd Byte Word Input Access L L L L L H Odd Byte Even Byte ( bits) Word Output Access L L L L H L Odd Byte Even Byte ( bits) I/O Read Inhibit H L H Don t Care Don t Care I/O Write Inhibit H H L High Z High Z High Byte Input Only L L H L H Odd Byte High Z ( bits) High Byte Output L L H H L Odd Byte Don t Care Only ( bits) 0

28 . Common Memory Transfer Function.. Common Memory Function The Common Memory Transfer to or from the CompactFlash card can be either or bits. The CompactFlash card permits both and bit accesses to all of its Common Memory addresses. TABLE -: COMMON MEMORY FUNCTION Function Code -REG -CE -CE A0 -OE -WE D-D D-D0 Standby Mode H H High Z High Z Byte Read Access H H L L L H High Z Even Byte ( bits) H H L H L H High Z Odd Byte Byte-Write Access H H L L H L Don t Care Even Byte ( bits) H H L H H L Don t Care Odd Byte Word Read Access H L L L H Odd Byte Even Byte ( bits) Word-Write Access H L L H L Odd Byte Even Byte ( bits) Odd Byte Read Only H L H L H Odd Byte High Z ( bits) Odd Byte-Write Only H L H H L Odd Byte Don t Care ( bits)

29 . True IDE Mode I/O Transfer Function.. True IDE Mode I/O Function The CompactFlash card can be configured in a True IDE Mode of operation. The CompactFlash card is configured in this mode only when the -OE input signal is grounded by the host during the power off to power on cycle. In this True IDE Mode the PCMCIA protocol and configuration are disabled and only I/O operations to the Task File and Data Register are allowed. In this mode no Memory or Attribute Registers are accessible to the host. CompactFlash cards permit bit data accesses if the user issues a Set Feature Command to put the device in bit Mode. Note: Removing and reinserting the CompactFlash card while the host computer s power is on will reconfigure the CompactFlash to PC Card ATA mode from the original True IDE Mode. To configure the CompactFlash card in True IDE Mode, the 0-pin socket must be power cycled with the CompactFlash card inserted and -OE (output enable) asserted. The following table defines the function of the operations for the True IDE Mode. TABLE -: TRUE IDE MODE I/O FUNCTION Function Code -CE -CE A0-A -IORD -IOWR D-D D-D0 Invalid Mode L L High Z High Z Standby Mode H H High Z High Z Task File Write H L -h H L Don t Care Data In Task File Read H L -h L H High Z Data Out Data Register Write H L 0 H L Odd Byte Even Byte In In Data Register Read H L 0 L H Odd Byte Even Byte Out Out Control Register L H h H L Don t Care Control In Write Alt Status Read L H h L H High Z Status Out Drive Address L H h L H High Z Data Out 0

30 .0 Software Interface. CF-ATA Drive Register Set Definition and Protocol The CompactFlash card can be configured as a high performance I/O device through: a.) Standard PC-AT disk I/O address spaces F0h-Fh, Fh-Fh (primary); 0h-h, h-h (secondary) with IRQ (or other available IRQ). b.) Any system decoded Byte I/O block using any available IRQ. c.) Memory space. The communication to or from the CompactFlash card is done using the Task File registers which provide all the necessary registers for control and status information. The PCMCIA interface connects peripherals to the host using four register mapping methods. The following is a detailed description of these methods: TABLE -: I/O CONFIGURATIONS Standard Configurations Config I/O or Address Description Index Memory 0 Memory 0h-Fh, 00h-FFh Memory Mapped I/O 0h-Fh I/O Mapped Contiguous Registers I/O F0h-Fh, Primary I/O Mapped Fh-Fh I/O 0h-h, Secondary I/O Mapped h-h 0

31 .. I/O Primary and Secondary Address Configurations TABLE -: PRIMARY AND SECONDARY I/O DECODING -REG A-A A A A A0 -IORD=0 -IOWR=0 Note Notes: 0 F()h Even RD Data Even WR Data, 0 F()h Error Register Features, 0 F()h Sector Count Sector Count 0 F()h 0 0 Sector No. Sector No. 0 F()h Cylinder Low Cylinder Low 0 F()h 0 0 Cylinder High Cylinder High 0 F()h 0 0 Select Card/Head Select Card/Head 0 F()h 0 Status Command 0 F()h 0 0 Alt Status Device Control 0 F()h 0 Drive Address Reserved. Register 0 is accessed with -CE low and -CE low (and A0 = Don t Care) as a word register on the combined Odd Data Bus and Even Data Bus (D-D0). This register may also be accessed by a pair of byte accesses to the offset 0 with -CE low and - CE high. Note that the address space of this word register overlaps the address space of the Error and Feature byte-wide registers which lie at offset. When accessed twice as byte register with -CE low, the first byte to be accessed is the Even Byte of the word and the second byte accessed is the Odd Byte of the equivalent word access.. A byte access to register 0 with -CE high and -CE low accesses the error (read) or feature (write) register.. Address lines which are not indicated are ignored by the CompactFlash card for accessing all the registers in this table. 0

32 .. Contiguous I/O Mapped Addressing When the system decodes a contiguous block of I/O registers to select the CompactFlash card, the registers are accessed in the block of I/O space decoded by the system as follows: TABLE -: CONTIGUOUS I/O DECODING -REG A A A A0 Offset -IORD=0 -IOWR=0 Notes Even RD Data Even WR Data Error Features Sector Count Sector Count Sector No. Sector No Cylinder Low Cylinder Low Cylinder High Cylinder High Select Card/Head Select Card/Head 0 0 Status Command Dup. Even RD Data Dup. Even WR Data Dup. Odd RD Data Dup. Odd WR Data 0 0 D Dup. Error Dup. Features 0 0 E Alt Status Device Ctl 0 F Drive Address Reserved Notes:. Register 0 is accessed with -CE low and -CE low (and A0 = Don t Care) as a word register on the combined Odd Data Bus and Even Data Bus (D-D0). This register may also be accessed by a pair of byte accesses to the offset 0 with -CE low and - CE high. Note that the address space of this word register overlaps the address space of the Error and Feature byte-wide registers that lie at offset. When accessed twice as byte register with -CE low, the first byte to be accessed is the Even Byte of the word and the second byte accessed is the Odd Byte of the equivalent word access. A byte access to register 0 with -CE high and -CE low accesses the error (read) or feature (write) register.. Registers at offset, and D are non-overlapping duplicates of the registers at offset 0 and. Register is equivalent to register 0, while register accesses the Odd Byte. Therefore, if the registers are byte accessed in the order then the data will be transferred Odd Byte then Even Byte. Repeated byte accesses to register or 0 will access consecutive (Even then Odd) Bytes from the data buffer. Repeated word accesses to register, or 0 will access consecutive words from the data buffer. Repeated byte accesses to register are not supported. However, repeated alternating byte accesses to registers then will access consecutive (Even then Odd) Bytes from the data buffer. Byte accesses to register access only the Odd Byte of the data.. Address lines which are not indicated are ignored by the CompactFlash card for accessing all the registers in this table.

33 .. Memory Mapped Addressing When the CompactFlash card registers are accessed via memory references, the registers appear in the common memory space window: 0- KBytes as follows: TABLE -: MEMORY MAPPED DECODING -REG A0 A-A A A A A0 Offset -OE=0 -WE=0 Notes Even RD Data Even WR Data, Error Features, Sector Count Sector Count Sector No. Sector No Cylinder Low Cylinder Low Cylinder High Cylinder High Select Card/Head Select Card/Head 0 0 Status Command Dup. Even RD Data Dup. Even WR Data Dup. Odd RD Data Dup. Odd WR Data 0 0 D Dup. Error Dup. Features 0 0 E Alt Status Device Ctl 0 F Drive Address Reserved 0 Even RD Data Even WR Data Odd RD Data Odd WR Data Notes:. Register 0 is accessed with -CE low and -CE low as a word register on the combined Odd Data Bus and Even Data Bus (D-D0). This register may also be accessed by a pair of byte accesses to the offset 0 with -CE low and -CE high. Note that the address space of this word register overlaps the address space of the Error and Feature byte-wide registers that lie at offset. When accessed twice as byte register with -CE low, the first byte to be accessed is the Even Byte of the word and the second byte accessed is the Odd Byte of the equivalent word access. A byte access to address 0 with -CE high and -CE low accesses the error (read) or feature (write) register.. Registers at offset, and D are non-overlapping duplicates of the registers at offset 0 and. Register is equivalent to register 0, while register accesses the Odd Byte. Therefore, if the registers are byte accessed in the order then the data will be transferred Odd Byte then Even Byte. Repeated byte accesses to register or 0 will access consecutive (Even then Odd) Bytes from the data buffer. Repeated word accesses to register, or 0 will access consecutive words from the data buffer. Repeated byte accesses to register are not supported. However, repeated alternating byte accesses to registers then will access consecutive (Even then Odd) Bytes from the data buffer. Byte accesses to register access only the Odd Byte of the data.. Accesses to even addresses between 00h and FFh access register. Accesses to odd addresses between 00h and FFh access register. This KByte memory window to the data register is provided so that hosts can perform memory to memory block moves to the data register when the register lies in memory space. Some hosts, such as the processors, must increment both the source and destination addresses when executing the memory to memory block move instruction. Some PCMCIA socket adapters also have auto incrementing address logic embedded within them. This address window allows these hosts and adapters to function efficiently. Note that this entire window accesses the Data Register FIFO and does not allow random access to the data buffer within the CompactFlash card. 0 A word access to address at offset will provide even data on the low-order byte of the data bus, along with odd data at offset on the high-order byte of the data bus.