Zefeer EVB-H. Hardware Manual

Transcription

1 DATE CREATION: Mar 2005 DATE LAST MODIFIED: May 2007 DAVE s.r.l. VERSION: FILE NAME: Zefeer-evb-h-hm Zefeer EVB-H Hardware Manual

2 History Rev. Date EVB-H Hw Rev. DZQ Hw Rev. Details CS010305A CS034304A Initial Release CS010305A CS034304A Small corrections about S1 switch CS010305A CS034304A Updated PCMCIA section. Changed default boot configuration. Removed Zefeer connectors pinout. Small corrections CS010305B CS034304A, CS034304B Added info about new zefeer modules provided with Zefeer-EVB. New section added about PCB history.

3 Contents Cap. 1 - Block Scheme... 5 Cap. 2 - Board layout and Physical... 7 Cap. 3 - Zefeer module provided with Zefeer EVB... 8 Cap. 4 - Bootstrap Settings... 9 Cap. 5 - Providing Power to the board: ATX Power Supply Connector (JP10)... 9 Cap. 6 - LEDs Reset LED Boot LEDs : Green LED and Red LED Cap. 7 - Reset and Bootstrapping Cap. 8 - Interfaces and Connectors RS232 Serial Ports (P0,P1,P2) /100BaseT LAN (JPF1) USB-A Host Ports (JP4,JP5,JP11) IDE connector (JP8) PCMCIA Connector (J3) LCD Connectors (JZIF1, JP9) JTAG Interface Connector (JP2) Expansion Connectors (JP1,JP7) Zefeer Socket Connectors (J1, J2) Cap. 9 - NAND Cap RTC Cap LCD module Cap Support Cap Schematics Cap PCB History page 3 of 23

4 Zefeer EVB-H Hardware Manual Printed in Italy Trademarks Ethernet is a registered trademark of XEROX Corporation Copyright All rights reserved. Specifications may change any time without notification. Life Support Applications Zefeer EVB-H Embedded Computer Board are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. DAVE Srl customers who using or selling these products for use in such applications do so at their own risk and agree to fully indemnify DAVE Srl for any damages resulting from such improper use or sale. Company Address DAVE S.r.L. Via Forniz Porcia (PN) Italy Phone: info@dave.eu URL: Technical Support support-zefeer@dave.eu ease, refer to Naming and Order Codes, Section at page.

5 ATTENTION! FOR ALL USER IN POSSES OF Zefeer Embedded Linux kit: Zefeer Embedded Linux Kit supports two new modules (DZQ3610x3 or DZQ3610x4). It is strongly recommended the reading of AN-ZELK-009 Migrating to ZELK that details the differences with respect to the previous modules. ATTENTION! Starting Zefeer-hm version 1.1.0, new Zefeer modules are available. Such models have new features: RTC/WDT device integrated, new type of flash memories as P30, etc. It's stronlgy recommended to read sections 10, 3, and [1]. Cap. 1 - Block Scheme Zefeer EVB-H Evaluation Board is the target board where the Zefeer DZQ modules powered with an EP9315 Cirrus microprocessor can be fitted and rapidly tested. Zefeer module comes with all essential features needed in order to quickly set up a customized system based on this processor. As an example, module comes with its flash NOR memory and SDRAM memory as well as reset logic, in order to provide proper power-on reset sequence and power monitor. Nevertheless Zefeer module provide autonomously to generate the core power supply at 1.8V voltage that microprocessor requires from 3.3V on input. All interface and power signals are passed through two 140 pin 0.6mm pitch stacking connectors, therefore users should complete hardware interfaces and connectors when they want to use them through the host board 1. A quick overview of the board is given, both from mechanical and electrical point of view. Nevertheless, for detailed information, user should refer to components manufacturer s data sheet. 1 Please, for further details about Zefeer module, refer to [1] page5 of 23

6 Zefeer EVB-H Socket Connector JTAG ETH0 UART0 Full RS232 UART1 UART2 USB0 USB1 USB2 Rx/Tx-ETH0 RS232 Drivers RS232 Drivers RS232 Drivers Current Limiter Current Limiter Current Limiter JTAG Interface D B 9 D B 9 ETH0 RJ45 D B 9 DCE DTE DCE HOST USB0 HOST USB1 HOST USB2 LCD PCMCIA 3.5 TFT LCD P C M C I A IIC BUS DIGITAL I/O PERIPHERAL BUS ADC Input USER RESET Power Supply RTC Reset Button NAND FLASH E X P C O N N ATX Power Fig. 1 Zefeer EVB-H Block Scheme

7 Cap. 2 - Board layout and Physical Zefeer EVB-H layout board is depicted below in Fig. 2. Fig. 2 Zefeer EVB-H board layout page7 of 23

8 Cap. 3 - Zefeer module provided with Zefeer EVB A DZQ module is provided with EVB-H. It must be located as indicated in the picture below. No particular care must be taken in insertion of the module. When you unplug the module, you should maintain CPU board and Host board coplanar as much as possible, in order to prevent connector from damages. Fig. 3- Zefeer EVB-H photo WARNING: Zefeer EVB-H can accommodate the DZQ Zefeer model type ONLY. (See for more information about models family). Inserting different Zefeer model hardware may be damaged permanently the Zefeer EVB. Please, contact our suport service prior to use it with different type models. Starting ZELK-1.5.0, Zefeer-EVB can be provided with different type of modules: DZQ3600I3R, DZQ3610C3R, DZQ3610C4R. Main differences about modules regards flash memory type (Intel flash P30 supported), presence of RTC&WDG Dallas DS1374, slight changes on pinout. For what concern zefeer-evb, the main difference is that EVB that mounts DZQ3610C4R (that integrated an RTC) don't mount RTC. For further details about presence of RTC in Zefeer-EVB please refer to section 10 at page 20. For further information about various differences of zefeer modules, please refer to [1].

9 Cap. 4 - Bootstrap Settings When users plugs Zefeer module onto Zefeer EVB-H, they have to trim some settings. Settings are performed via dip switch S2 whose functions are described in Tab. 1. PIN Function ON OFF DEFAULT 1 Serial Boot or Normal Boot SERIAL NORMAL OFF 2 External Boot or Internal Boot EXTERNAL INTERNAL ON Tab. 1 S2 (pin1, 2 and 4) settings As shown above, Pin 1 selects Serial Boot or Normal Boot option. Pin 2 selects the boot from Internal BootROM (OFF) or from an external memory device. Default configuration sets NORMAL and EXTERNAL mode. Cap. 5 - Providing Power to the board: ATX Power Supply Connector (JP10) Connector JP10 is a conventional ATX Minifit 20 poles connector [e.g. Molex ]. It allows to plug a comon and unexpensive complete ATX Power Supply Unit, able to supply EVB, but also USB, PCMCIA, TFT-LCD and Expansion Connector, nevertheless an IDE hard DISK through its proper power connector. Usually ATX is sold in several versions: 150W version is enough for all purposes. When user plugs ATX PSU, red led related to stand-by voltage (+5V_SB) switches on. By pushing S3 button, we turn on and off ATX PSU. ATX Power Source supplies two Power Voltages: +3V3_ATX and +5V_ATX. From this last one an LDO Regulator generates +3V3 that powers the DZQ module and other simple logic, while PCMCIA, LCD take power from +3V3_ATX and USB from +5V_ATX. Zefeer EVB-H provides one led (+3V3) close to the each Power Source. Zefeer EVB-H can take a typical current of 900 ma 2. We remember that EVB provide onboard current limiter devices for each USB Port with a fix current limit of 500mA. It s worthwhile to remember that some settings are needed before turning on board (see Chapter 4). 2 This value is been measured in the following working conditions: Serial Ports 0,1,2 working, Ethernet working, USB Port 0,1,2 working with three keyboard devices, LCD turned-on, and Signals of Expansion Connector JP1 not utilized. Current Supply could be subject to large changes in function of external USB interconnected and in function of external peripherals interconnected. page9 of 23

10 Cap. 6 - LEDs Some leds are available on the board other than those tha indicate Power Voltage. Their meaning is described below. 6.1 Reset LED This is the red led close to S1 reset button with RST silkscreen. When system is on and microprocessor is running, it should be turned-off. When the system stuck in reset this leds will turn on (red light). 6.2 Boot LEDs : Green LED and Red LED These are the leds used by microprocessor during Boot phase. They are placed near S1 reset button. The green one is the Green LED and is driven directly by GLED microprocessor signal, while the red one is the Red Led and is driven directly by RLED signal. For further details about such signal, refer to [1] and [2]. Cap. 7 - Reset and Bootstrapping On EVB there is no reset CPU supervisor nor power-monitoring. Thus, reset signal RST that comes out from the module, is generated at power-up by a CPU supervisor that monitors +3V3. Furthermore user can give a Manual Reset thorugh S1 button. This reset button is strightly connected to MRSTn pin (J2.102) that is a Master Reset Input of the same CPU supervisor device mounted on Zefeer module. When such pin goes low global system will be reset (for further details see reference [1]). Pushing reset button user should see the RST LED turning-on.

11 Cap. 8 - Interfaces and Connectors 8.1 RS232 Serial Ports (P0,P1,P2) P0 is a DB9 male connector featuring a full RS232 (except for RI signal) from UART0 of microprocessor. In Tab. 2 are listed signal carried over it. PIN SIGNAL 1 UART0_CD (EGPIO15) 2 UART0_RX 3 UART0_TX 4 UART0_DTR 5 GND 6 UART0_DSR 7 UART0_RTS 8 UART0_CTS 9 UART0_RI (EGPIO0) Tab. 2 P0 Connector pinout (DTE) Since P0 is a DTE connector type, user must use a null-modem serial cable to connect with a PC. Using a normal serial cable user may damage the board. P1 and P2 are DB9 female connectors featuring an RS232(not full). These serial ports don t provide all signals as P0 serial port. Signals available are listed in Tab. 3. PIN SIGNAL 1 n.c. 2 UART1_TX (P1) UART2_TX(P2) 3 UART1_RX(P1) UART2_RX(P2) 4 n.c. 5 GND 6 n.c. 7 n.c. 8 n.c. 9 n.c. Tab. 3 P1, P2 Connectors pinout (DCE) Since P1 and P2 are a DCE connector type, user must use a normal serial cable (not null-modem) to connect it with a PC. page11 of 23

12 8.2 10/100BaseT LAN (JPF1) JPF1 is the LAN 10/100BASE-T connector for ethernet interface, related to ethernet chip mounted on Zefeer module. There is two type of connectors that EVB can provide: TYPE A that incorporates Link Led and Tx Led TYPE B that doesn t incorporate any LEDs In both cases, the pinout of connector, for what concern foundamental signals, is explained in Tab. 4 and in Fig. 4. PIN SIGNAL 1 TX+ 2 TX- 3 RX+ 4 N.C. 5 N.C. 6 RX- 7 N.C. 8 N.C. Tab. 4 - JPF1 - RJ45 LAN Connector - pinout Pin2: Tx- Pin1: Tx+ Pin3: Rx+ Pin6: Rx- Fig. 4 JPF1 - RJ45 LAN Connector

13 8.3 USB-A Host Ports (JP4,JP5,JP11) Zefeer EVB provide three USB-Host Ports on JP4(USB0), JP5(USB1), JP11(USB2). These Ports are functionally identical. JP4,JP5 and JP11 are standard USB-A-connector Molex , so user can connect a large variety of USB devices like keyboard mouse etc. EVB provides on-board current limiter device for current sink from external USB devices and protection diodes on each USB signals. For further details about USB section refer to EVB schematics [3]. 8.4 IDE connector (JP8) JP8 is a normal IDC header 20x2x2.54mm connector for IDE Hard-disk cable interconnection. For further details about JP8 pinout, please refer to [3]. Hard disk devices can take power sullpy from ATX power through its separate power supply connector. 8.5 PCMCIA Connector (J3) J3 is a standard 68-pin PCMCIA connector conforming to JEIDA ver.3 3. User can insert PC cards operating at +3V3 or +5V Voltage. EVB provides on-board PC CardBus Power Controller chip that identifies card type and provides proper power supplies (Vcc and Vpp) automatically by setting P_VCC3EN signal (see table 5 for more details). It also performs current limiting. Such device provides over 1A for Vcc and over 200mA for Vpp. PC Cards that require +12V Voltage are not supported. PCMCIA Bus and Control Signals from microprocessor to J3 connector are buffered. P_VCC3EN Vcc [V] Vpp [V] Tab. 5 - PCMCIA supported power configurations 8.6 LCD Connectors (JZIF1, JP9) JZIF1 is a 40 pins, 0.6mm pitch FPC connector 4 for 0.5mm ZIF Flat Cable. JZIF1 pinout is conforming to LCD panel provided with KIT. All LCD and Touchscreen signals coming out from Zefeer module are buffered before to coming out by JZIF1 connector. For further details about LCD panel refer to JP9 is a standard pin strip 20x2x2.54 connector where main LCD signals set and Touchscreen signals set come out directly from microprocessor without buffering operation. This allows to interface Zefeer module with another LCD panel. JP9 Pinout is described in Tab. 6. Other than RGB signals and standard-tft control 3 For example: HIROSE ICIFA-68PD-1.27DS 4 As example :Omron XF2H-4015 page13 of 23

14 signals, there are two signals that allows to turn-on/off LCD Digital Logic [LCD_PCI] and Backlight [LCD_LIGHT_ON]. LCD_PCI is implemented by EGPIO3 I/O signal and LCD_LIGHT_ON by EGPIO8 I/O signal. Power Supply 3V3_ATX from ATX present at pins 2 and 3, can be utilized to provide power supply to others LCD Panels. Two PWM signals, BRIGHT and PWMOUT can be utilized for brightness control. PIN SIGNAL PIN SIGNAL 1 TOUCH_XP 2 +3V3_ATX 3 TOUCH_Xm 4 GND 5 TOUCH_Yp 6 TOUCH_SXp 7 TOUCH_Ym 8 TOUCH_SXm 9 P12 10 TOUCH_SYm 11 P14 12 TOUCH_SYp 13 P16 14 P13 15 P6 16 P15 17 P8 18 P17 19 P10 20 P7 21 P0 22 P9 23 P2 24 P11 25 P4 26 P1 27 VSYNCFP 28 P3 29 GND 30 P5 31 SPCLK 32 BALNK 33 GND 34 HSYNCLP 35 BRIGHT 36 LCD_PCI (EGPIO3) 37 +3V3_ATX 38 LCD_LIGHT_ON (EGPIO8) 39 GND 40 PWMOUT Tab. 6 JP9-LCD Interface connector pinout 8.7 JTAG Interface Connector (JP2) In Tab. 7 pinout of JP2 connector are described. JP2 make available JTAG signals of the microprocessor in order to connect a JTAG Hardware Interface. Signals are pulled up internally to Zefeer module with a 10KΩ resistor. PIN SIGNAL PIN SIGNAL 1 VCC 2 n.c. 3 TRSTn 4 GND 5 TDI 6 GND 7 TMS 8 GND 9 TCK 10 GND 11 n.c. 12 GND 13 TDO 14 GND 15 RSTn 16 GND 17 n.c. 18 GND 19 n.c. 20 GND Tab. 7 JP2-JTAG connector pinout

15 8.8 Expansion Connectors (JP1,JP7) In the next table are shown signal of JP1 and JP7 Expansion Connector. It can be used by users in order to set-up their own boards and to quickly develop their own interfaces. Only main function is indicated in the table, under column name, being several pins available for multiple purposes. The column Alt.function indicates if the pin have some alternatives function other than the primary one. Furthermore each pins also marked with * have a digital I/O port function. In order to know in detail which functions each pins provides, user should refer to the Data Sheet of the microprocessor manufacturer. Also detailed electrical specifications (levels, tolerances, timings and so on) must be verified on official document released by manufacturer (See [2]). Notice that pins marked with pin (1) are connected directly to the microcontroller. Please, take note that Addresses and Data relative to the Peripheral Bus are annotated with the convention that the zeroed bit is always the Least Significant Bit. That is D0 is the LSB of the Data and A0 is the LSB of the Addresses. page15 of 23

16 Pin Name Alt.function Description 1 GND Ground reference 3 GND Ground reference 5 CSn0 Chip select out NOT FREE used by Zefeer module for its Intenal FLASH 7 CSn1 Chip select out 9 CSn2 Chip select out NOT FREE used for NAND FLASH 11 CSn3 Chip select out 13 CSn6 Chip select out 15 CSn7 Chip select out 17 D0 Shared Data bus in/out 19 D2 Shared Data bus in/out 21 D4 Shared Data bus in/out 23 D6 Shared Data bus in/out 25 D8 Shared Data bus in/out 27 D10 Shared Data bus in/out 29 D12 Shared Data bus in/out 31 D14 Shared Data bus in/out 33 D16 Shared Data bus in/out 35 D18 Shared Data bus in/out 37 D20 Shared Data bus in/out 39 D22 Shared Data bus in/out 41 D24 Shared Data bus in/out 43 D26 Shared Data bus in/out 45 D28 Shared Data bus in/out 47 D30 Shared Data bus in/out 49 A0 Shared Address bus out 51 A2 Shared Address bus out 53 A4 Shared Address bus out 55 A6 Shared Address bus out 57 A8 Shared Address bus out 59 A10 Shared Address bus out 61 A12 Shared Address bus out 63 A14 Shared Address bus out 65 A16 Shared Address bus out 67 A18 Shared Address bus out 69 A20 Shared Address bus out 71 A22 Shared Address bus out 73 A24 Shared Address bus out 75 n.c. 77 3V3 Power Supply 79 GND Ground reference Tab. 8 Summary of JP1 odd pins D0 = LSB, D15 = MSB page 16 of 23

17 Pin Name Alt.function(TBD) Description 2 GND Ground reference 4 GND Ground reference 6 WAITn SRAM Wait In 8 WEn Write Enable out 10 RDn SRAM Read/OE strobe out 12 DQMn0 Shared data mask out 14 DQMn1 Shared data mask out 16 DQMn2 Shared data mask out 18 DQMn3 Shared data mask out 20 D1 Shared Data bus in/out 22 D3 Shared Data bus in/out 24 D5 Shared Data bus in/out 26 D7 Shared Data bus in/out 28 D9 Shared Data bus in/out 30 D11 Shared Data bus in/out 32 D13 Shared Data bus in/out 34 D15 Shared Data bus in/out 36 D17 Shared Data bus in/out 38 D19 Shared Data bus in/out 40 D21 Shared Data bus in/out 42 D23 Shared Data bus in/out 44 D25 Shared Data bus in/out 46 D27 Shared Data bus in/out 48 D29 Shared Data bus in/out 50 D31 Shared Data bus in/out 52 A1 Shared Address bus out 54 A3 Shared Address bus out 56 A5 Shared Address bus out 58 A7 Shared Address bus out 60 A9 Shared Address bus out 62 A11 Shared Address bus out 64 A13 Shared Address bus out 66 A15 Shared Address bus out 68 A17 Shared Address bus out 70 A19 Shared Address bus out 72 A21 Shared Address bus out 74 A23 Shared Address bus out 76 A25 Shared Address bus out 78 3V3 Power Supply 80 GND Ground reference Tab. 9 Summary of JP1 even pins A0 = LSB, A15 = MSB page 17 of 23

18 Pin Name Alt.function Description 1 PORSTn Power On Reset 3 MRSTn Master Reset 5 RSTn System Reset 7 INT0 Interrupt Request 0 9 INT2 Interrupt Request 2 11 SDCSn0 SDRAM chip selects out 13 SDCSn2 SDRAM chip selects out 15 GND Ground reference 17 SDCLK SDRAM clock out 19 GND Ground reference 21 SDCLKEN SDRAM clock enable out 23 SDWEn SDRAM write enable out 25 EGPIO0 General Purpose I/O (not available USED for UART0_RI) 27 EGPIO2 General Purpose I/O 29 EGPIO4 General Purpose I/O (not available USED for External NAND) 31 EGPIO6 General Purpose I/O (not available USED for External NAND) 33 EGPIO8 General Purpose I/O (not available USED for LCD_LIGHT_ON) 35 EGPIO10 General Purpose I/O 37 EGPIO12 General Purpose I/O 39 EGPIO14 General Purpose I/O 41 ROW6 Key matrix row outputs 43 ROW4 Key matrix row outputs 45 ROW2 Key matrix row outputs 47 ROW0 Key matrix row outputs 49 COL6 Key matrix column inputs 51 COL4 Key matrix column inputs 53 COL2 Key matrix column inputs 55 COL0 Key matrix column inputs 57 ASDI AC97 primary input 59 ASDO AC97 output 61 RXD1 Receive / IrDA input 63 TXD1 Transmit / IrDA output 65 RXD2 Receive 67 TXD2 Transmit 69 3V3 +3V3 Power Supply 71 3V3 +3V3 Power Supply 73 +5V +5V Power Supply 75 +5V +5V Power Supply 77 GND Ground reference 79 GND Ground reference Tab. 10 Summary of JP7 odd pins D0 = LSB, D15 = MSB page 18 of 23

19 Pin Name Alt.function(TBD) Description 2 INT1 Interrupt Request 1 4 INT3 Interrupt Request 3 6 CASn SDRAM CAS out 8 GND Ground reference 10 RASn SDRAM RAS out 12 n.c. 14 EGPIO1 General Purpose I/O 16 EGPIO3 General Purpose I/O (not available USED for LCD_PCI) 18 EGPIO5 General Purpose I/O (not available USED for External NAND) 20 EGPIO7 General Purpose I/O (not available USED for External NAND) 22 EGPIO9 General Purpose I/O 24 EGPIO11 General Purpose I/O 26 EGPIO13 General Purpose I/O 28 EGPIO15 General Purpose I/O (not available USED for UART0_CD) 30 ROW7 Key matrix row outputs 32 ROW5 Key matrix row outputs 34 ROW3 Key matrix row outputs 36 ROW1 Key matrix row outputs 38 COL7 Key matrix column inputs 40 COL5 Key matrix column inputs 42 COL3 Key matrix column inputs 44 COL1 Key matrix column inputs 46 ASYNC AC 97 frame sync 48 ARSTn AC97 reset output 50 SFRM1 SPI frame clock output 52 ABITCLK AC97 bit clock 54 SCLK1 SPI bit clock 56 SSPRX1 SPI Input 58 SSPTX1 SPI output 60 SLA1 Flash programming voltage control. Leave open 62 SLA0 Flash programming voltage control. Leave open 64 EECLK EEPROM / Two-wire Interface clock 66 EEDAT EEPROM / Two-wire Interface data 68 nwc Write protection signal (active low) of the EEPROM. Normally it is pulled low and writing is allowed. Pull it high to protect data. 70 3V3_ATX +3V3_ATX Power Supply 72 3V3_ATX +3V3_ATX Power Supply 74 +5V +5V Power Supply 76 +5V +5V Power Supply 78 GND Ground reference 80 GND Ground reference Tab. 11 Summary of JP7 even pins A0 = LSB, A15 = MSB page 19 of 23

20 8.9 Zefeer Socket Connectors (J1, J2) J1 and J2 are socket connectors where Zefeer module is plugged-in. These connectors mate with the connectors of Zefeer DZG/DZN/DZQ modules 5 described in chapter 4 of Zefeer Hardware Manual ([1]). Please see this reference for the detailed pinouts. Please, take note that Addresses and Data relative to the Peripheral Bus are annotated with the convention that the zeroed bit is always the Least Significant Bit. That is D0 is the LSB of the Data and A0 is the LSB of the Addresses. Cap. 9 - NAND A NAND Flash memory is mounted On the Evaluation Board. Since Zefeer module doesn t provide a similar type on-board, users may experiment the advantage to have a filing system on-board. Electronic schematics attached with the kit show how NAND is electrically connected to microprocessor bus. As far as software drivers, please refer to source code included in the Kits. Some GPIO pins available at J2 are used in order to access to NAND device : GPIO4,GPIO5,GPIO6,GPIO7, CSn2 so user can not use such pins on JP1 expansion connector. Chip select utilized for NAND access is CSn2, so user must not use it. Cap RTC Zefeer EVB that mount zefeer module with marking code as the following type: DZQxxxxx1 or DZQxxxxx3, provide an IIC RTC-device with backup-lithium-battery type CR1220. Microprocessor communicates through IIC protocol (EECLK,EEDATA signals) with RTC device. All Zefeer-EVB that mounts zefeer module with marking code similar to DZQxxxxC4, don't mount RTC, since this zefeer modules integrates Dallas DS1374 as RTC device on-module. WARNING: in case of Zefeer-EVB that mounts modules type DZQxxxxC4, battery CR1220 is not connected to RTC DS1374. So, when user switch-off the EVB, RTC DS1374 will lose all data data. For further information about DS1374, please refer to [1]. Please, remember that modules DZQ3610C3R, DZQ3610C4R can be mount only in Zefeer-EVB that don't mount RTC device. 5 Connector J1 of the ZefeerEVB-H will mate with connector J1 of the processor module. Connector J2 of the ZefeerEVB-H will mate with connector J2 of the processor module.

21 Cap LCD module Zefeer EVB-H is provided with a 240x320 portrait 3,5 TFT- LCD module (262k colors, -R,G,B 6bit digital each) connected by a ZIF Cable. LCD module is a Hitachi TX09D50VM1CCA that integrates a Timing Controller that generate timing to be interfaced with a standard LCD Graphic Controller, a Power Unit for logic and LED Backlight. A resistive 4-wire Touch Panel is also integrated. Power Supply is +3V3_ATX and maximum input current is 1A. For further details about LCD Module please refer to [4]. WARNING: PRECAUTIONS AGAINST ELECTROSTATIC DISCHARGE. As this module contains CMOS LSIs, it is not strong against electrostatic discharge. Make certain that the operator's body is connected to the ground through a list band. Furthermore it's recommended that I/F pins will not be touch directly. page21 of 23

22 Cap Support To contact technical support, please send an to address support-zefeer@dave.eu indications of the codes. with the Cap Schematics ZefeerEVB-H Schematics in PDF format are included in Zefeer Development Kits. Please contact our sales deparment for more details at sales@dave.eu. HISTORY Kit Date Modifies First version Silkscreen of BOOT OPTIONS TABLE, modified on column DEFAULT Cap PCB History HISTORY Kit Date PCB Version Schematics Version Modifies CS010305A First Version CS010305B Silkscreen of BOOT OPTIONS TABLE, modified on column DEFAULT

23 References [1] Dave Srl, Zefeer Hardware Manual, 2004 [2] Cirrus Logic, EP9315 Data Sheet, 2004 [3] DAVE Srl, Zefeer EVB-H Schematics, 2004 [4] Hitachi, Hitachi TX09D50VM1CCA Datasheet, 2005 page23 of 23