logibayer.ucf Core Facts

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1 logibayer Color Camera Sensor Bayer Decoder March 6, 2009 Product Specification Core Facts Provided with Core Xylon d.o.o. Documentation User s Guide Design File Formats Encrypted VHDL Fallerovo setaliste 22 Constraints Files logibayer.ucf Zagreb, Croatia Verification VHDL test bench Phone: Instantiation Templates Fax: VHDL info@logicbricks.com Reference Designs & Reference EDK design URL: Application Notes Features Available under terms of the SignOnce IP License Converts camera sensor video from Bayer Additional Items Xylon Evaluation platforms logicraft2 and logicraft3 Xilinx XtremeDSP Video Starter Kit Spartan-3A DSP Edition Simulation Tool Used color space to the RGB color space ModelTech s Modelsim Supports all possible Bayer pattern Support combinations (first two pixels GB, GR, BG or Support Provided by Xylon BR) Automatically recognizes camera resolution Unlimited vertical resolution; horizontal resolution up to 1024 pixels Optional built-in LVDS receiver compatible with Micron MT9V022 CMOS image sensor for automotive applications Configurable memory interface (32 or 64 bits) designed for Xylon logimem memory controller and CoreConnect TM PLBv46. Other bus types can be supported on request. Fixed or variable LVDS pixel clock Parametrizable VHDL design that allows tuning of slice consumption and features set Prepared for Xilinx Platform Studio (XPS) and the EDK Plug and Play with other Xylon logicbricks TM IP cores like the logiwin Versatile Video Input or the logilens Camera Lens Distortion Corrector Table 1: Example Implementation Statistics for Xilinx FPGAs Fmax Family Example Device Slices 1 IOB 2 GCLK BRAM (MHz) MULT/ DSP48/E DCM / Design CMT MGT Tools Spartan -3E XC3S N/A ISE i Spartan -3A XC3SD1800A N/A ISE i Virtex -4 XC4VFX N/A ISE i Notes: 1) Actual slice count dependent on percentage of unrelated logic see Mapping Report File for details 2) Assuming all core I/Os and clocks are routed off-chip March 6, 2009

2 logibayer Color Camera Sensor Bayer Decoder Applications Automotive rear-view camera Consumer digital cameras General Description Figure 1: logibayer Block Diagram The logibayer is an IP core, from Xylon logicbricks TM IP library, optimized for Xilinx FPGAs and designed for real-time Bayer pattern demosaicing (decoding). Today most common single-chip cameras use Bayer pattern sensors, which have specific physical pixel positions and assign a single color value (Red, Green, or Blue) to each pixel. This Bayer encoding (mosaicing) enables further approximation of the other two primary colors for all sensor pixels. The logibayer IP converts input camera sensor video from Bayer color space into the RGB color space. It supports all possible Bayer pattern combinations (Figure 2). The color space conversion includes realtime approximations of missing primary colors and generation of the output RGB888 video output. The core can be used as an input into a camera processor IP chain designed by the Xylon logicbricks TM IP cores. 0 = BG 1 = RG 2 = GB 3 = GR Figure 2: Bayer Pattern Combinations: BG, RG, GB and GR 2 March 6, 2009

3 Xylon The logibayer consume modest FPGA resources and multiple logibayer IP instances can be implemented in a single low-cost FPGA capable to simultaneously process video streams from multiple cameras. Such applications are gaining popularity; i.e. in automotive Driver Assistance Systems (DAS). The logibayer is highly configurable IP core and users can setup its configuration prior to FPGA implementation. The IP consists of an optional built-in LVDS receiver compatible to Micron MT9V022 CMOS image sensor and the Bayer decoder. Both blocks can be independently switched on and off by VHDL generics. The IP core automatically recognizes camera resolution and supports input synchronization signals (Vertical Sync and Data Valid) with an arbitrary polarity. The processed video (RGB888) can be passed over to other IPs for further video processing, or stored into frame buffers implemented in SRAM or SDRAM memories out of the Xilnx FPGA chip. The Figure 3 presents a block diagram of demo FPGA design for Xylon Evaluation/Development platform logicraft2, based on several Xylon logicbricks TM and Xilinx IP cores. Xylon s logicvc-ml multilayered versatile video controller displays video input as a layer on the LCD display. This layer can be overlaid (blended, color keyed, etc.) by other display s layers showing computer generated graphics, animations, or even multiple video streams from different cameras. Functional Description Figure 3: logibayer Reference Design The Figure 1 presents the logibayer internal architecture. The major logibayer s functional blocks are: LVDS RECEIVER Sampler Shift register Decoder Output register March 6,

4 logibayer Color Camera Sensor Bayer Decoder BAYER Video Input Block Bayer decoding Interface to XMB (Xylon memory bus) Universal FIFO PLB wrapper logibayer Registers LVDS RECEIVER The receiver compatible with the Micron MT9V022 samples 2-wire LVDS input serial data selects and extracts synchronization signals and data. The synchronization signals and the data are grouped into an output parallel bus. By mean of the VHDL generic, the receiver can be excluded from the logibayer IP if there is a parallel camera bus at IP s inputs. BAYER BLOCK Video demosaicing takes place within this block. The Bayer block is also optional and can be controlled by a VHDL generic. An exception of the Bayer block from the IP architecture converts the logibayer into LVDS converter from 2-wire into 8- or 10-wire parallel LVDS bus. The Bayer block approximates all primary colors values and takes care of picture s marginal pixels. The marginal pixels do not have surrounding pixels necessary for correct algorithm executions and must be cropped out. An integrated FIFO buffers calculated RGB pixels and packs them for higher speed transfer into memory or further video processing IPs. Core Modifications The core is supplied in an encrypted VHDL format, with simulation vectors. Many logibayer configuration parameters are selectable prior to VHDL synthesis, and the following table presents the most important parameters: Table 2: logibayer VHDL configuration parameters Parameter C_CONFIGURATION_MODE C_REGS_INTERFACE C_LVDS_DATA_OUT_WIDTH C_CLK_PERIOD_FIXED C_VMEM_INTERFACE C_FIRST_TWO_PIX Description 0 - use LVDS only 1 - use both LVDS and Bayer 2 - use Bayer only Register interface enabled or disabled Variable LVDS output data width: 8 or 10 bits Fixed or variable LVDS clock period XMB or PLB interface to memory Determines the Bayer pattern The logibayer has been constructed with regard to adaptability to various cameras. However, there may be instances where source code modification is necessary. If you wish to reach the optimal use of the logibayer core or to supplement some of your specific functions allow Xylon to tailor the logibayer to your requirements. Core I/O Signals The core signal I/O have not been fixed to specific device pins to provide flexibility for interfacing with user logic. Descriptions of all signal I/O are provided in Table 3. 4 March 6, 2009

5 Table 3: Core I/O Signals. Xylon Signal Signal Direction Global signals RST Input Global synchronous set/reset VCLK Input Video Input Clock MCLK Input Video Memory Clock Memory interface Description XMB Interface Bus Xylon Memory Bus. Refer to Xylon logimem specification PLBV46 Master Interface Bus Refer to Xilinx-IBM Core connect specification Register interface PLBV46 Slave Interface Bus Refer to Xilinx-IBM Core connect specification Auxiliary signals - BAYER VSYNC Input Vertical synchronization DE Input Data enable (line valid) DIN Input Input data VSYNC_OUT Output Output Vertical synchronization DE_OUT Output Output Data enable (line valid) D_OUT Output Output data when Bayer implemented DATA_OUT Output Output data when LVDS only implemented HRES Output Horizontal resolution VRES Output Vertical resolution Auxiliary signals - LVDS CLK Input LVDS deserializer clock = 12*pixel clock CLK_90 Input LVDS deserializer clock phase shifted 90 degrees CLK27_IN Input Pixel clock when FIXED pixel clock period is used CLK27_OUT Output Pixel clock when VARIABLE pixel clock period is used LVDS_DATA_P Input LVDS input data pair LVDS_DATA_N Input LVDS input data pair Verification Methods The logibayer is fully supported by the Xilinx Platform Studio and the EDK integrated software solution. This tight integration tremendously shortens IP integration and verification. A full logibayer implementation does not require any particular skills beyond general Xilinx tools knowledge. Recommended Design Experience The user should have experience in the following areas: - Xilinx design tools - ModelSim Available Support Products Xylon logicbricks TM IP cores can be evaluated on logicraft2 and logicraft3 Xylon development platforms, which are designed especially for developers working in the fields of multimedia and infotainment. Both platforms demonstrate modularity on all levels: software, board, FPGA, and IP cores. The platforms make excellent development tools particularly appropriate for the development of embedded systems with strong graphics capabilities. March 6,

6 logibayer Color Camera Sensor Bayer Decoder To learn more about the Xylon development platforms, contact Xylon or visit the web: URL: Ordering Information This product is available directly from Xylon under the terms of the SignOnce IP License. Please contact Xylon for pricing and additional information about this product using the contact information on the front page of this datasheet. To learn more about the SignOnce IP License program, contact Xylon or visit the web: URL: This publication has been carefully checked for accuracy. However, Xylon does not assume any responsibility for the contents or use of any product described herein. Xylon reserves the right to make any changes to product without further notice. Our customers should ensure that they take appropriate action so that their use of our products does not infringe upon any patents. Xylon products are not intended for use in the life support applications. Use of the Xylon products in such appliances is prohibited without written Xylon approval. Related Information Xilinx Programmable Logic For information on Xilinx programmable logic or development system software, contact your local Xilinx sales office, or: Xilinx, Inc Logic Drive San Jose, CA Phone: Fax: URL: Revision History Version Date Note New doc template 6 March 6, 2009