PS2 VGA Peripheral Based Arithmetic Application Using Micro Blaze Processor

Transcription

1 PS2 VGA Peripheral Based Arithmetic Application Using Micro Blaze Processor K.Rani Rudramma 1, B.Murali Krihna 2 1 Assosiate Professor,Dept of E.C.E, Lakireddy Bali Reddy Engineering College, Mylavaram , Krishna 2 Assistent Professor,Dept of E.C.E, K.L.University, Abstract: Reconfigurable computer architectures are becoming increasingly popular for many applications. The evaluation of design methods and concepts of one particular reconfigurable architecture: soft-core processors. Soft-core processors provide a lot of options for system designers. Due to Reconfigurability nature of FPGA s, have been very effective to implement peripheral based Applications. In this paper a new peripheral based arithmetic application is designed, the keyboard module is a custom hardware module that accepts input from a PS/2 serial keyboard and outputs character data to the VGA input memory. The Embedded Development Kit (EDK) provides an arsenal in the field of FPGA's and is a suite of design tools which are based on a common framework that enable you to design a complete embedded processor system for implementation in a FPGA device. This paper specifies a different alternative to increase the performance, of peripheral based Arithmetic application in embedded systems based on MicroBlaze, a soft-core processor designed for Field Programmable Gate Arrays. These platforms not only enable system architects to design and develop complex custom systems using embedded processor and interoperable IP cores. Synthesis & Simulation were done using Xilinx Platform Studio Tool and Implementation of design using Spartan FPGA board Keywords: Xilinx Platform Studio, Embedded Development Kit, MicroBlaze Processor, PS2 controller, VGA Peripheral 1. INTRODUCTION The reprogrammable nature of FPGAs presents one of its strongest advantages as well as one of its most significant limitations as compared to an Application Specific Integrated Circuit (ASIC), which is a nonreprogrammable integrated circuit that is customized for a particular use. A Field Programmable Gate Array (FPGA) is a user-programmable logic device which can be programmed to interconnect arrays of switches to arrays of logic elements. FPGAs are very useful to developers because of their reprogrammable nature [2]. With an FPGA, companies have the freedom of modifying hardware designs since the device is reprogrammable. Devices such as Application Specific Integrated Circuits (ASICs) are chips that are built for a certain use and cannot modified after fabrication [4]. This paper is organized into seven different sections. In sec I & II describes Introduction and Architecture of MicroBlaze Processor. Software Development Tools used to develop the application was discussed in sec III. Hardware / Software Partioning required for developing the graphical interface to user with application for I/O Data manipulations listed in sec - IV. Design Methodology concepts were described in sec V. Implementation Results was displayed in sec VI. Finally Conclusion describes difficulty in configuring the IP cores, design time flexibility, Resource utilization concepts were discussed in sec VII. 2. HARDWARE ARCHITECTURE The MicroBlaze is a virtual microprocessor that is built by combining blocks of code called cores inside a Xilinx Field Programmable Gate Array (FPGA). The MicroBlaze processor is a 32-bit Harvard Reduced Instruction Set Computer (RISC) architecture optimized for implementation in Xilinx FPGAs with separate 32- bit instruction and data buses running at full speed to execute programs and access data from both on-chip and external memory at the same time [3]. The backbone of the architecture is a single-issue, 3-stage pipeline with 32 general-purpose registers, an Arithmetic Logic Unit (ALU), a shift unit, and two levels of interrupt [9]. This flexibility allows the user to balance the required performance of the target application against the logic area cost of the soft processor [10]. Fig.1.MicroBlaze Core Block Diagram Volume 2, Issue 4 July August 2013 Page 153

2 Figure 1 shows a view of a MicroBlaze system. The MicroBlaze core is organized as Harvard architecture with separate bus Interface units for data accesses and instruction accesses. MicroBlaze does not separate between data accesses to I/O and memory [1]. The processor has up to three interfaces for memory accesses: Local Memory Bus (LMB), IBM s On-chip Peripheral Bus (OPB), and Xilinx Cache Link (XCL). 3. SOFTWARE DEVELOPMENT TOOL The designer uses the EDK hardware tools to generate parameter files that specify which peripherals Ethernet, RS-232, SDRAM, custom core, etc.., are to be used and physical pinouts on the FPGA to which these peripherals are connected. The tools then synthesize net lists, and then call the Integrated Software Environment (ISE) to route the FPGA s configurable logic cells [5]. The EDK software tools take other parameter files and generate libraries to support each peripheral in the design. The designer specifies what the target Operating System (OS) will be, and the EDK will automatically generate a set of Board Support Package (BSP) files for that particular combination of peripherals. custom hardware module that accepts input from a PS/2 serial keyboard and outputs character data to the VGA input memory. Software Partioning include PS2 and VGA custom Peripheral Initializations. Developing software Algorithm either in C/C++ language, flexibility for user interface for application control with MicroBlaze processor [7]. Fig.2 Xilinx Platform Studio Design flow 3.1 Title Integrated Software Environment The Integrated Software Environment (ISE) is the foundation for Xilinx FPGA logic design. Various utilities, such as constraints entry, timing analysis, logic placement and routing, and device programming have all been integrated into ISE. 3.2 Xilinx Platform Studio XPS is a design tool suite which can be used to design a complete embedded processor system for implementation with a Xilinx FPGA device 3.3 Embedded Development Kit XPS is part of the Xilinx Embedded Development Kit (EDK) and includes all the tools required to process hardware and software system components. EDK includes hardware IP for the Xilinx embedded processors and their peripherals, drivers and libraries [6]. 3.4 Software Development Kit The tool compliments XPS by allowing the user to develop software application projects in a very intuitive software development environment which is based on the Eclipse open source standard. 4.HARDWARE / SOFTWARE PARTIONING There are some tasks that are needed to implement in hardware, such as I/O that is routed to physical connectors on the board. In an analogous manner there are tasks that are meant to be implemented in software. The final partitioning of the system is divided into two partitions. They are Hardware and Software Partitions. Hardware Partioning includes the keyboard module is a Fig.3. PS/2 Connector Location and Signals 4.1 PS/2 Interface The Spartan-3E Starter board includes a PS/2 mouse/keyboard port and the standard 6-pin mini-din connector, labeled J14 on the board. Figure 3 shows the PS/2 connector. The PS/2 interface is a bit serial interface with two signals Data and Clock [3]. Whenever the Data and Clock line is not used, i.e. is idle, both the Data and Clock lines are left floating, that is the host and the device both set the outputs in high impedance. When the FPGA reads the Data or Clock inputs both PS2Data_out and PS2Clk_out are kept low which puts the tri-state buffers in high impedance mode. 4.2 Protocol for receiving data from the keyboard Fig.4. PS/2 Protocol Fig.5. PS/2 Timing Volume 2, Issue 4 July August 2013 Page 154

3 A transfer may be initiated by the keyboard if the Clock line is high. The host (FPGA in this case) may force the Clock low in order to prevent the keyboard from sending data to the host may inhibit communication. 4.3 PS/2 Timing Data is sent in bit serially. The first bit is always a start bit, logic 0 [10]. Then 8 bits are sent with the least significant bit first. The data is padded with a parity bit (odd parity). The parity bit is set if there is an even number of 1's in the data bits and reset (logic 0) if there is an odd number of 1's in the data bits. The number of 1's in the data bits plus the parity bit always add up to an odd number (odd parity.) This is used for error detection. A stop bit (logic 1) indicates the end of the data stream. 4.4 Keyboard scan-codes The keyboard sends packets of data, scan codes, to the host indicating which key has been pressed. When a key is pressed or held down a make code is transmitted. When a key is released a break code is transmitted. Every key is assigned a unique make and break code so that the host can determine exactly what has happened. There are three different scan code sets, but all PC keyboards use Scan Code Set 2. A sample of this scan code set is listed in figure 7. Keyboard scan-codes. 4.5 VGA Interface To display the images on CRT and LCD monitors, the VGA port of the starter board can be connected to the monitor using the standard monitor cable. The VGA port has five signals three of which are the video signals and remaining two are the synchronization signals [8]. Each pixel is represented using three bits; hence this board can display only eight colors on the monitor at 25 MHz pixel rate; while the clock oscillator of the Spartan 3E starter board runs at frequency of 50 MHz. The VGA port of Spartan 3E Starter Board is shown in the fig 6. The VGA output signal consists of three analogue channels, one for each colour red, green and blue. In addition to these there are two signals named vertical sync (Vsync) and horizontal sync (Hsync). 5. DESIGN METHODOLOGY The hardware developed for this project has been under the Xilinx EDK environment. Within this environment, the system developed contains a MicroBlaze soft-core processor connected to local memory bus (LMB) lines to Block RAM (BRAM) for the systems memory. The processor takes inputs and sends outputs to the general purpose input/output (GPIO) devices via the on-chip peripheral bus (OPB) line. This is the general MicroBlaze soft-core processor set-up for the system. Beyond this is adding the necessary components for the PS/2 keyboard port, VGA, and RS-232 serial port. 5.1 PS2 Peripheral Initialization Xilinx PS2 IP core can be configured to control keyboard or mouse. In this project it is configured to read data from the keyboard [11]. The slave PS2 controller is connected to the MicroBlaze processor using PLB bus. The data is read from keyboard in polling mode Fig.6. VGA port of Spartan 3E Starter Fig.7. Keyboard scan-codes Board Fig.8.Adding PS2 IP Fig.9.No Bus Connection using Bus Interface Volume 2, Issue 4 July August 2013 Page 155

4 Fig.10.Bus Connection using Bus Interface Fig.11.Making Ports External 5.2VGA Peripheral Initialization The VGA was done as a custom IP core, which is then connected to the MicroBlaze processor using FSL bus. Fig.15. Multiplication of Given HyperTerminal Result in Fig.12.Create Import Peripheral Fig.13.VGA Peripheral Wizard 6.IMPLEMENTATION RESULTS This Paper is implemented in Spartan3E Starter Kit (XC3S500E-Device Family, FG320-Package, and 4- Speed Grade).General Purpose Input Outputs (GPIOs) Peripheral Devices like, PS/2, VGA, are controlled through Serial Communication (UART) via RS-232 interface using MicroBlaze Processor shown in figure 14. Fig.16. Addition of Given Numbers Result in HyperTerminal Fig.14. PS2 VGA Communication Through MicroBlaze Processor Fig.17 Device Utilization Summary Volume 2, Issue 4 July August 2013 Page 156

5 Fig.18. XPS Generated Block Diagram 7. CONCLUSION Micro Blaze Soft core processor can be configured to the targeted application using Xilinx EDK software tool in which Base System Builder wizard is used to create a simple Hardware processor system. VGA custom IP, TFT IP Core and PS2 IP core is initialized in XPS and the necessary PLB Bus connections and ports are configured. Able to learn interfacing most of the important hardware components. Configuring the IP cores, reduces the design time of the project. References [1] K.Lund, PLB vs. OCM Comparison Using the Packet Processor Software [2] R. J. Ou and V. K. Prasanna, A methodology for energy efficient application synthesis using platform FPGAs, in Proc. Eng. Reconfigurable Systems and Algorithms (ERSA 04), T. P. Plaks, Ed. Athens, GA: CSREA Press, 2004, pp [3]. Programmable Gate Array Data Book, Xilinx, Inc., San Jose, CA, [4] PowerPC and MicroBlaze Development Kit Virtex- 4 FX12 Edition. Xilinx-Corporation. [5] MicroBlaze Processor Reference Guide. Xilinx Corporation, sw_manuals/edk92i_mb_ref_guide.pdf [6] ML40x EDK Processor Reference Design. Xilinx Corporation [7] S. Brown, R. J. Francis, J. Rose, and Z. G. Vranesic, Field Programmable Gate Arrays. Boston, MA: Kluwer Academic, [8] Cofer, R. Harding, B. Rapid System Prototyping with FPGAs. Elsevier Science and Technology Books, Inc [9] Kuon, I. Rose, J. Measuring the Gap Between FPGAs and ASICs. [10] Input / Output Peripheral Devices Control Through Serial Communication Using MicroBlaze Processor. Devices, Circuits and Systems (ICDCS), 2012 International Conference on Date of Conference: 15-16,March,2012. Volume 2, Issue 4 July August 2013 Page 157