Hello and welcome to this Renesas Interactive module that provides an overview of the RX DMA Controller

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1 Hello and welcome to this Renesas Interactive module that provides an overview of the RX DMA Controller 1

2 The purpose of this Renesas Interactive module is to give you a basic understanding of the RX Direct Memory Access Controller or DMA. For a general overview of data movement peripherals like DMA s and DTC s, please see the Data Movement Peripherals overview module. This module provides: - An overview of the RX DMA controller - A brief discussion of the transfer modes the DMAC supports - An overview of the DMAC register set - and a short explanation of how the DMA controller works with the Interrupt Controller in the RX This module should take about 20 minutes to complete. Let s get started. 2

3 Here is a diagram of the RX Direct Memory Access Controller, or DMAC. The DMAC sits on Internal Main bus 2, and can act as a master on this bus, giving the DMAC access to on-chip RAM and flash as well as on-board peripherals. The DMAC is tightly coupled to the Interrupt Control Unit or ICU, allowing the ICU the trigger DMA transfers and the DMAC to generate interrupts to the CPU core. There are four independent channels in the RX DMAC, and each one has a dedicated set of control registers. 3

In normal mode, the DMAC transfers a single data item each time the DMAC is triggered. It can be triggered from a number of hardware sources or by a software request.

4 In normal mode, the DMAC transfers a single data item each time the DMAC is triggered. It can be triggered from a number of hardware sources or by a software request. During each transfer, a single 8-, 16-, or 32-bit data item is transferred from the source address to the destination address. Each time the DMAC is triggered, another data item is transferred from source to destination. The source & destination address registers keep track of where to move the data from and to. The DMAC can be configured to leave the source & destination addresses unchanged after a transfer, or to automatically increment or decrement one or both. Each address behavior can be configured independently allowing easy transfer to and from peripheral registers to memory buffers. Channel 0 has an additional mode that allows an offset to be added to an address rather than just a simple increment or decrement function. The transfer counter is decremented after each transfer, counting down to zero. It is 16-bits wide, allowing over 60,000 transfers to take place before the CPU has to intervene. Setting the transfer counter to zero puts the DMAC in free-run mode. Finally, the DMAC can generate an interrupt to the CPU at the end of each transfer. To restart the DMAC after the end of the transfer, you ll have to reset the source & destination addresses and the transfer counter. 4

Each time the DMAC is triggered, a data item is transferred from source to destination. The source & destination address registers keep track of where to move the data from and to.

5 The DMAC also supports Repeat Transfer Mode. As with normal mode, the DMAC transfers a single data item each time the DMAC is triggered. During each transfer, a single 8-, 16-, or 32-bit data item is transferred from the source address to the destination address. Each time the DMAC is triggered, a data item is transferred from source to destination. The source & destination address registers keep track of where to move the data from and to. As with normal mode, the DMAC can be configured to automatically increment or decrement one or both addresses. The source or the destination can be specified as the repeat area, and the size of the repeat area can be up to 1K. In this example, we ll use the source as the repeat area and a repeat area size of 4. At each trigger of the DMAC, a data item is transferred and the transfer count is decremented. A separate block count is decremented each time the end of the repeat area is reached. The block count can be a maximum of 1K. At this time, the address register for the repeat area is reset to its initial value. Since the source area is the repeat area in our example, the SAR register is reset to point to the start. The other address register continues to be updated, incrementing, decrementing, or remaining constant according to its configuration. Further triggers of the DMAC continue to transfer data, one item at a time. The repeat area is reset at the end of each scan, and the block counter is decremented. When the block counter reaches zero, the transfer ends and an interrupt can be generated to the CPU. An interrupt may also be generated at each repeat, although you ll need to be 5

6 aware that this suspends the DMA transfers for this channel and you ll need to re-arm it. 5

In Block Transfer Mode, the DMAC transfers an entire block of data from the source to the destination area. At each request, the DMAC transfers a block of data.

The updates to the source & destination addresses happen as each data item is moved during the block transfer, so if the source or destination address was set to increment, then at the end of the

7 In Block Transfer Mode, the DMAC transfers an entire block of data from the source to the destination area. At each request, the DMAC transfers a block of data. The data within the block can be 8-, 16-, or 32-bit values. As with the other modes, the source & destination address registers keep track of where to move the data from and to. The updates to the source & destination addresses happen as each data item is moved during the block transfer, so if the source or destination address was set to increment, then at the end of the block transfer it will point to the first data item after the block. The source or the destination can be specified as the block area, and the size of the block area can be up to 1K. In this example, the destination is the block area and the block size is 3. A transfer counter is used internally by the DMAC as it transfers each block; initialize it to the block size. A separate block count is decremented each time the DMAC is triggered and a block is transferred. The address register of the block area resets to the start of the block area after each transfer. When the block counter reaches zero, the transfer ends and an interrupt can be generated to the CPU. An interrupt may also be generated at each block transfer. 6

8 Now let s look at the registers that control the function of the DMAC There are a core set of four registers that control the transfers. These are the source & destination address registers, and the transfer and block count registers. We ll see more about these in a bit. Mode & control registers setup the DMAC controllera nd interrupt & status registers allow you to monitor the completion of DMAC transfers Finally, it s important to note that you may need to set registers in the Interrupt Control Unit and any peripherals that you will use to trigger the DMAC. 7

Here s the DMAC register set. Each of the four DMAC channels has one set of these registers, with the exception of the two registers noted. The registers fall into a handful of functional groups.

The source & destination addresses can each be fixed, incremented, or decremented. DMAC channel 0 also allows offset addition.

9 Here s the DMAC register set. Each of the four DMAC channels has one set of these registers, with the exception of the two registers noted. The registers fall into a handful of functional groups. The source & destination address registers specify the source & destination for the data. The address mode register allows you to optionally update the address registers with each transfer. The source & destination addresses can each be fixed, incremented, or decremented. DMAC channel 0 also allows offset addition. In this mode, the value in the DMA offset register is added to source or destination address at each transfer. During transfers, the two count registers DMCRA and DMCRB keep track of the number of transfers and blocks or repeats. The DMA transfer mode register configures the DMAC for normal, repeat, or block mode, the size of data operands, and other options. Interrupts from the DMAC are controlled through the DMA interrupt setting register and the DMA activation source flag control register. The remaining control and status registers control starting & stopping of the DMAC 8

10 During DMA transfers, the DMAC moves data from the location pointed to by the Source Address Registers to the location pointed to by the Destination Address Register. Each register contains a 32-bit address. Valid addresses are anywhere in the upper or lower 256 megabytes of the RX 32-bit address space. This covers all on-chip memory and peripherals. To transfer data to and from memory and devices external to the chip, use the External DMA controller, or ExDMAC. Based on settings in the DMAC Address Mode Register, each of these registers can be incremented or decremented after each transfer. This allows for transfers from a fixed memory location like a register to a buffer, or vice versa, as well other operation. DMAC channel 0 also supports an offset addition mode, which allows an address register to be updated by a fixed offset after each transfer. 9

11 The DMA transfer count register is a single register that takes on two different configurations based on the DMA transfer mode. In normal mode, it is a 16-bit transfer counter that allows up to transfers. Write the desired number of transfers into the low word of the register. In repeat and block modes, the upper word contains the repeat size or block size, and the lower word contains the repeat or block count. During the transfers, the DMAC updates the count in the lower word as it performs the data movement, reloading it with the value from the upper word at each repeat or block transfer. Be sure to initialize both the upper and lower words to the same value since the value in the lower word controls the initial repeat cycle or block transfer. 10

12 The DMAC Block Transfer Counter Register is only used in Repeat & Block transfers. This register sets the number repeats or block transfers. Up to 1,024 repeats or blocks can be specified. 11

13 While the DMA Controller can be triggered by software requests, typically it is started by a signal from the Interrupt Control Unit generated by a peripheral. Configuring a hardware interrupt source to trigger the DMAC is very similar to configuring the interrupt for normal use. You ll need to set the local enables in the peripheral, plus the interrupt priority level and interrupt enable registers for the source. In addition, each DMA channel has a DMA Activation Source Select Register in the ICU. Each register contains the vector number of the interrupt source that is to trigger the corresponding DMA channel. Check the hardware manual for specifics of which peripheral interrupts are capable of being routed to DMA requests. The DMAC can also generate interrupts to the ICU to signal DMA events and exceptions to the CPU core. Interrupts can fire at each transfer, at the completion of each repeat or block, or at the end of the DMA transfer. Interrupts generated by the DMAC are enable by bits in the DMINT register. See the hardware manual for complete details. 12

14 This concludes this Renesas Interactive module. In this session you ve learned about - the RX DMA Controller, - the three transfer modes it supports, - the register set that controls the DMAC, - and how the Interrupt Control unit to provide triggers to the DMAC, as well as interrupts the DMAC can send to the ICU. Thanks for watching! 13

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16 Thank You 15

Welcome to this presentation of the STM32 direct memory access controller (DMA). It covers the main features of this module, which is widely used to

Welcome to this presentation of the STM32 direct memory access controller (DMA). It covers the main features of this module, which is widely used to handle the STM32 peripheral data transfers. 1 The Direct