Hello and welcome to this Renesas Interactive module that covers the Independent watchdog timer found on RX MCUs.

Transcription

1 Hello and welcome to this Renesas Interactive module that covers the Independent watchdog timer found on RX MCUs. 1

2 This course covers specific features of the independent watchdog timer on RX MCUs. If you need basic information on watchdog timers please refer to the Watchdog Timer Overview Course. If you are looking for information that applies to a specific RX group please refer to that group's Technical Marketing Overview Course. In this course we will cover the watchdog timer s block diagram, the available clocking and timeout options, how to start and refresh the watchdog, what happens when a counter underflows, general usage notes, and how to use the independent watchdog timer with the RX s watchdog timer. 2

3 This figure shows the block diagram of a typical Independent watchdog timer on an RX MCU. First notice the independent watchdog timer s registers which include the IWDT refresh register, control register, and status register. Note that these registers are accessed using the peripheral clock as can be seen by the PCLK coming in from the left. To the right of the registers you will see the different clocks that can be selected for the independent watchdog. Notice that all of the clock options are based upon the on-chip oscillator. Next we can see the 14-bit down counter of the independent watchdog. If this counter underflows the IWDT control circuit can issue a reset command to the MCU. 3

4 As shown on the block diagram slide, all the independent watchdog's clocking options are based upon the on-chip oscillator or OCO. By setting the CKS bits in the IWDT's control register the user can select a divisor of between 1 and 256 for the on-chip oscillator. Different timeout values can also be chosen for the independent watchdog. Whatever value is chosen will be the value that is put into the watchdog's 14-bit counter when it is refreshed. Since the independent watchdog is a down counting timer, the larger the value chosen, the longer the timeout. With these options the user has a large timeout range to choose from. The shortest timeout would be to use the on-chip oscillator with no division and a timeout value of hex 3FF which is 1024 OCO cycles. With an on-chip oscillator frequency of 125kHz this gives the user a timeout value of 8.192ms. The longest timeout that could be achieved would be to use a 256 divisor on the on-chip oscillator and have the timeout value be hex 3FFF or 4,194,304 on-chip oscillator cycles. Using the 125kHz OCO frequency this would give the user a timeout value of around 33 and a half seconds. An important thing to note is that the IWDTCR register can only be written once per reset. Once the register has been written the MCU has an internal lock bit that prevents it from being written again until after a reset. This means that the clock and timeout values cannot be changed after the user has written their initial values. 4

5 Starting and refreshing the independent watchdog timer are done in the same manner, which is to write to the independent watchdog s refresh register. To write the refresh register hex 00 should first be written and then hex FF. If this sequence is not maintained then the watchdog will not be refreshed. Here are some examples of invalid write sequences. This first example is invalid because the first write was not hex 00, but hex 23h. In this case, the first write was correct but the second write was hex 54 when it should have been hex FF. Writing something other than hex FF after writing hex 00 also invalidates the sequence as shown here. Let s look at two valid write sequences. The first is the normal case where writing hex 00 is followed by writing hex FF. It is also valid to have multiple writes of hex 00 as long as hex FF follows one of them. When a valid write sequence is performed the counter will be refreshed with the value chosen by the TOPS bits in the independent watchdog s control register. 5

6 What happens when the independent watchdog underflows is a reset of the MCU. This figure shows an example of IWDT operation. The IWDT starts counting when the timer is refreshed. When a refresh occurs, the counters value is reset to the value chosen by the TOPS bits in the IWDT's control register. In the event that the IWDT is not refreshed, an underflow occurs and a reset signal is sent out from the IWDT to the MCU. At this point the MCU is reset. The user can check to see if the cause for the reset was due to an IWDT timeout by reading the value of the underflow flag in the IWDT's status register. In the event of an IWDT underflow, this flag is set. The user should make sure to clear the flag after reading so that proper checking can be done if there is another reset. After the reset has occurred the IWDT does not start counting again until the refresh register has once again been successfully written to with the correct byte sequence. 6

7 This slide covers some usage notes that users should be aware of when using the IWDT. The first note is that once the IWDT has begun counting, the only way to stop the timer is a reset. Refer to the Reset section of your specific RX group s hardware manual for more information on this topic. The user should also know that when using the IWDT, the MCU cannot transition into Software Standby Mode. Instead the MCU will transition into either sleep mode or all-module clock-stop mode depending on the MCU s configuration. In these modes the IWDT will still be operating and can cause a reset. 7

8 The RX has two watchdog timer units: the watchdog timer and the independent watchdog timer. While the independent watchdog timer only has the option of resetting the MCU when a timeout occurs, the watchdog timer can trigger an interrupt. Using these two together the watchdog timer could be used as a controlled shutdown mechanism while the independent watchdog would still offer the hard reset functionality. With this setup the standard watchdog could be used to detect errors in the user s system that would only be recreated after a hard reset has occurred. 8

9 In summary, in this module we covered: -the block diagram of the RX's independent watchdog timer, -The clock and timeout options available, -How to start and refresh the watchdog, -What happens when the watchdog s counter underflows, -Usage notes about stopping the timer and using the IWDT with low power modes, -And how you could use the watchdog timer along with the independent watchdog timer peripheral -We would like to thank for viewing this course. You may consider viewing the Technical Marketing Overview Course for more information on RX MCUs. 9

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11 Thank You 11