Tiger series CompactFlash Card

Transcription

1 Tiger series CompactFlash Card Product Specification December 2007 TCADO-SCF / V5

2 Document History Version Description Date Editor Approved by 1 Preliminary June 2007 David Wu William Wang 2 Modify CHS value November 2007 David Wu William Wang 3 Phrase adjustment November 2007 Matika Wang William Wang 4 Modify CHS(512MB) December 2007 David Wu William Wang 5 Add CHS(128MB) December 2007 David Wu William Wang 6 Add CHS(28GB) December 2007 David Wu William Wang This document provides information regarding to C-ONE s CompactFlash product specification and is subject to change without any prior notice. No part in this report shall be distributed, reproduced, or disclosed in whole or in part without prior written permission of C-ONE. All rights reserved. C-ONE Technology Corp. Ltd. TCADO-SCF / V5

3 Contents 1. INTRODUCTION GENERAL DESCRIPTION FEATURES PRODUCT SPECIFICATION OPERATION AND ENVIRONMENT DESCRIPTION PHYSICAL DESCRIPTION PRODUCT MODEL INDUSTRIAL PART NUMBER DEFINITION SUPPORT FLASH MEDIA INDUSTRIAL COMPACTFLASH CARD LOGICAL FORMAT PARAMETERS (CHS) BLOCK DIAGRAM CONTROLLER ARCHIVE FLASH CARD ARCHIVE SPECIFICATION AND FEATURES ELECTRICAL SPECIFICATION Absolute Maximum Ratings General DC Characteristic DC Electrical Characteristics for 5 Volts Operation DC Electrical Characteristics for 3.3 Volts Operation Attribute Memory Read Timing Specification Configuration Register(Attribute Memory)Write Timing Specification Common Memory Read Timing Specification Common Memory Write Timing Specification I/O Input (Read) Timing Specification I/O Input (Write) Timing Specification True IDE Mode I/O (Read/Write) Timing Specification True IDE Ultra DMA Mode I/O (Read/Write) Timing Specification Ultra DMA Data-In Burst Initiation Timing Sustained Ultra DMA Data-In Burst Timing Ultra DMA Data-In Burst Host Pause Timing Ultra DMA Data-In Burst Device Termination Timing Ultra DMA Data-In Burst Host Termination Timing Ultra DMA Data-In Burst Host Termination Timing Sustained Ultra DMA Data-Out Burst Timing TCADO-SCF / V5

4 Ultra DMA Data-Out Burst Device Pause Timing Ultra DMA Data-Out Burst Device Termination Timing Ultra DMA Data-Out Burst Host Termination Timing POWER MANAGEMENT Normal Mode Power down Mode PHYSICAL SPECIFICATION CompactFlash CF Type I CompactFlash CF Type II PIN ASSIGNMENT COMPACTFLASH PIN TYPE SIGNAL DESCRIPTION CIS AND FUNCTIONS CONFIGURATION REGISTERS CONFIGURATION OPTION REGISTER (200H) CARD CONFIGURATION AND STATUS REGISTER (ADDRESS 202H) PIN REPLACEMENT REGISTER (ADDRESS 204H) SOCKET AND COPY REGISTER (ADDRESS 206H) CARD INFORMATION STRUCTURE (CIS) ATA SPECIFIC REGISTER DEFINITIONS MEMORY MAPPED ADDRESSING CONTIGUOUS I/O MAPPING ADDRESSING OVERLAPPING I/O MAPPING ADDRESSING TRUE IDE MODE ATA REGISTERS Data Register Error Register Feature Register Sector Count Register Sector Number Register Cylinder Low Register Cylinder High Register Drive Head Register Status Register Alternate Status Register Device Control Register Drive Address Register ATA COMMANDS...65 TCADO-SCF / V5

5 10.1 CHECK POWER MODE - 98H OR E5H EXECUTE DRIVE DIAGNOSTIC - 90H ERASE SECTOR(S) - C0H FORMAT TRACK - 50H IDENTIFY DRIVE ECH IDLE - 97H OR E3H IDLE IMMEDIATE - 95H OR E1H INITIALIZE DRIVE PARAMETERS - 91H READ BUFFER - E4H READ LONG SECTOR(S) - 22H OR 23H READ MULTIPLE - C4H READ SECTORS(S) 20H OR 21H READ VERIFY SECTOR(S) 40H OR 41H RECALIBRATE - 1XH REQUEST SENSE - 03H SEEK - 7XH SET FEATURE - EFH SET MULTIPLE MODE - C6H SET SLEEP MODE - 99H OR E6H STANDBY - 96H OR E2H STANDBY IMMEDIATE 94H OR E0H TRANSLATE SECTOR - 87H WEAR LEVEL - F5H WRITE BUFFER - E8H WRITE LONG SECTOR(S) 32H OR 33H WRITE MULTIPLE - C5H WRITE MULTIPLE WITHOUT ERASE CDH WRITE SECTOR(S) - 30H OR 31H WRITE SECTOR(S) WITHOUT ERASE - 38H WRITE VERITY - 3CH ERROR POSTING IDENTIFY DRIVE INFORMATION ATA PROTOCOL OVERVIEW PIO DATA IN COMMANDS PIO DATA OUT COMMANDS NON DATA COMMANDS ULTRA DMA DATA-IN COMMANDS INITIATING AN ULTRA DMA DATA-IN BURST TCADO-SCF / V5

6 14.2. THE DATA-IN TRANSFER PAUSING AN ULTRA DMA DATA-IN BURST Device pausing an Ultra DMA data-in burst Host pausing an Ultra DMA data-in burst Terminating an Ultra DMA data-in burst Device terminating an Ultra DMA data-in burst Host terminating an Ultra DMA data-in burst ULTRA DMA DATA-OUT COMMANDS Initiating an Ultra DMA data-out burst The data-out transfer Pausing an Ultra DMA data-out burst Host pausing an Ultra DMA data-out burst Device pausing an Ultra DMA data-out burst Terminating an Ultra DMA data-out burst Host terminating an Ultra DMA data-out burst Device terminating an Ultra DMA data-out burst ULTRA DMA CRC RULES SYSTEM ENVIRONMENTAL SPECIFICATIONS TEMPERATURE TEST FLOW ALTITUDE TEST TCADO-SCF / V5

7 1. Introduction 1.1 General Description C-ONE s CompactFlash Card uses NAND-Type flash memory devices, which leads to its remarkable high performance and comes with capacities from 128MB to 28GB unformatted. Compliant with ISA (Industrial Standard Architecture) bus interface standard, the S-CM CompactFlash Card performs sequential read/write for each sector (512 bytes) count. It also conforms to CompactFlash Specification and is designed with precision mechanics to enable host devices to read/write from the CompactFlash interface into Flash Media. It can operate with a 3.3V or 5V single power from the host side. The card provides extraordinary memory medium for PC or other CF compatible electric equipments and digital still camera, and, in particular, C-ONE s CompactFlash Card has been approved through various compatibility tests to be used i n numerous portable desktop, notebook computers and personal handheld devices such as handheld video/audio recorders, PDAs, Palm sized PCs, Handheld PCs and Auto PCs under industrial environment. TCADO-SCF / V5

8 1.2 Features PC Card compliant Conforms to CompactFlash standard 3.1 Compatible with PCMCIA ATA specification Support CIS implemented with attribute memory Compatible with all PC Card Services and Socket Services PCMCIA ATA / IDE interface ATA command set compatible Support for 8-bit or 16-bit host data transfer Program and auto-wait-state initiation for compatibility with any IORDY supporting host Compatibility with host ATA disk I/O BIOS, DOS/Windows file system, utilities, and application software Extremely rugged and reliable Advanced defect block management Support background erased operation 3.3/5 Volt power supply, very low power consumption Internal self-diagnostic program operates at V CC power on Auto sleep mode Error Correcting of 4 bits random error per sector Automatic on-the-fly, in-buffer Error Correcting Zero-power data retention, no batteries required 3 variations of mode access Memory card mode I/O card mode True IDE mode - PIO Mode 4 - UDMA mode 4 - supported Multi word DMA Mode 2. TCADO-SCF / V5

9 2. Product Specification 2.1 Operation and environment description Operating Voltage Typical Power Consumptions: Environment conditions File system supported Compatibility DC Input Power 5V 3.3V Operating Temperature 5V ± 10% 3.3V ± 5% Read Mode: 40mA (Max) Write Mode: 60mA (Max) Standby Mode:6.5mA(Approach values) Read/ Write Peak: 100mA Read Mode: 20mA (Max) Write Mode: 35mA (Max) Standby Mode: 1mA (Approach values) Read/ Write Peak: 100mA Extended Temp. -20 C to +85 C Industrial Temp. -40 C to +85 C Extended Temp. -40 C to +90 C Storage Temperature Industrial Temp. -50 C to +90 C Humidity Operation 5% to 95% (Non-condensing ) Humidity Non-operation Shock Operation 5% to 95% (Non-condensing ) 3000-G (Max.) Shock Non-operation 3000-G (Max.) Vibration Operation Vibration Non-operation FAT16 30-G (Peak to peak to maximum) 30-G (Peak to peak to maximum) FAT FAT32 NTFS Ext2 Ext3 TCADO-SCF / V5

10 2.2 Physical description 1.Weight and Measures (unit: m) 2. Storage Capacities 3. Performance Weight: 15 g Type I Pin-Pitch: 1.27 mm Weight: 23 g Type II Pin-Pitch: 1.27 mm Capacity Data Transfer Rates (Industrial) MTBF L x W x H 36.4 x 42.8 x 3.3 (mm) L x W x H 36.4 x 42.8 x 5.0 (mm) 128MB 28GB (Industrial) (TypeII:12GB, 16GB, 24GB, 28GB) Read speed up to 35 Mbytes/sec (Max) Write speed up to 32 Mbytes/sec (Max) 3,000,000 hours 4. Reliability Error Correction R/W Test Error Correcting of 4 bits random error per sector Testdisk: 3,000,000 Read/Write cycles TCADO-SCF / V5

11 3. Product Model 3.1 Industrial Part Number Definition X 1 X 2 X 3 X 4 X 5 X 6 -X 7 X 8 Code Definition symbol Description CF CF-CF card type 1 X 1 X 2 Card Type CP CP-CF card type 2 X 3 Solution M Tiger Series MB* MB* MB 01G 1GB 02G 2GB X 4 X 5 X 6 Capacity 04G 4GB 08G 8GB 12G 12GB 16G 16GB 24G 24GB 28G 28GB* Commercial Grade C 0 ~ 70 Temperature Light Grade X 7 L Range -20 ~ 85 Heavy Grade H -40 ~ 85 P Plastic housing X 8 Housing R Metal housing TCADO-SCF / V5

12 Card Capacity *1 Unit: Bytes Tiger series CompactFlash Card 4. Support Flash Media 4.1 Industrial CompactFlash Card Logical Format Parameters (CHS) Card Density *4 128MB 256MB 512MB 1GB 2GB Cylinder Heads Sectors/Track * Total Sectors/Card *3 253, ,024 1,005,984 2,013,984 4,027,968 Capacity *5 129,540, ,596, ,708,672 1,031,159,808 2,062,319,616 Unit: Bytes Card Density *4 4GB 8GB 12GB 16GB 24GB 28GB Cylinder Heads Sectors/Track * Total Sectors/Card *3 7,991,424 15,984,675 23,985,045 31,310,685 47,970,090 55,633,095 Capacity *5 4,091,609,088 8,184,153,600 12,280,343,040 16,031,070,720 24,560,686,080 28,484,144,640 Notes: 1. These data are written in Identify table. 2. Total tracks =number of head x number of cylinder. 3. Total sector/card = sector/track x number of head x number of cylinder 4. Those are general unformatted capacity of all cards. 5. It s the logical address capacity including the area which is used for file system. 6. Different file system format (FAT16/32) might result in minor different capacity 7. Future spec change can be downloading from C-One website without further notice to each customer. This document provides information regarding to C-ONE s CompactFlash product specification and is subject to change without any prior notice. No part in this report shall be distributed, reproduced, or disclosed in whole or in part without prior written permission of C-ONE. TCADO-SCF / V5

13 5. Block Diagram 5.1 Controller Archive 5.2 Flash Card Archive Power IC Reset IC According Card Capacity From Range 25MHz ~ 38MHz Host Interface Controller Flash Memory TCADO-SCF / V5

14 6. Specification and Features 6.1 Electrical Specification Absolute Maximum Ratings SYMBOL PARAMETER RATING UNITS V CC Power supply -0.3 to 6 V V IN Input voltage -0.3 to V CC V V OUT Output voltage -0.3 to V CC V T STG Storage temperature -50 to 90 Topr Operating temperature -40 to General DC Characteristic SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS C IN Input capacitance 15 pf C OUT Output capacitance 15 pf DC Electrical Characteristics for 5 Volts Operation SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V IN Input voltage 0 V CC V V CC Power supply V T STG Storage temperature T OPR Operating temperature V IL Input low voltage CMOS 0.8 V V IH Input high voltage CMOS 2.4 V V OL Output low voltage I OL =8mA 0.4 V V OH Output high voltage I OH =-8mA V CC 0.8 V TCADO-SCF / V5

15 6.1.4 DC Electrical Characteristics for 3.3 Volts Operation SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V IN Input voltage 0 V CC V V DD Power supply V T STG Storage temperature T OPR Operating temperature V IL Input low voltage CMOS 0.6 V V IH Input high voltage CMOS 2.4 V V OL Output low voltage I OL =8mA 0.4 V V OH Output high voltage I OH =-8mA V DD 0.8 V Attribute Memory Read Timing Specification Attribute Memory Read Timing 300 ns Item Symbol IEEE Symbol Read Cycle Time tc(r) tavav 300 Address Cycle Time ta(a) tavqv 300 Card Enable Access Time ta(ce) telqv 300 Output Enable Access Time ta(oe) tglqv 150 Output Disable Time from CE tdis(ce) tehqz 100 Output Disable Time from OE tdis(oe) tghqz 100 Address Setup Time tsu (A) tavgl 30 Output Enable Time from CE ten(ce) telqnz 5 Output Enable Time from OE ten(oe) tglqnz 5 Data Valid from Address Change tv(a) taxqx 0 TCADO-SCF / V5

16 6.1.6 Configuration Register(Attribute Memory)Write Timing Specification Configuration Register(Attribute Memory)Write Timing 250 ns Item Symbol IEEE Symbol Min ns Max ns Write Cycle Time tc(w) tavav 250 Write Pulse Width tw(we) twlwh 150 Address Setup Time tsu(a) tavwl 30 Write Recovery Time trec(we) twmax 30 Data Setup Time for WE tsu(d-weh) tdvwh 80 Data Hold Time th(d) twmdx 30 TCADO-SCF / V5

17 6.1.7 Common Memory Read Timing Specification Item Symbol IEEE Symbol Min ns Max ns Output Enable Access Time ta(oe) tglqv 125 Output Disable Time from OE tdis(oe) tghqz 100 Address Setup Time tsu(a) tavgl 30 Address Hold Time th(a) tghax 20 CE Setup before OE tsu(ce) telgl 0 CE Hold following OE th(ce) tgheh 20 Wait Delay Falling from OE tv(wt-oe) tglwtv 35 Data Setup for Wait Release tv(wt) tqvwth 0 Wait Width Time tw(wt) twtlwth 350 (3000 for CF+) TCADO-SCF / V5

18 6.1.8 Common Memory Write Timing Specification Item Symbol IEEE Symbol Min ns Max ns Data Setup before WE tsu(d-weh) tdvwh 80 Data Hold following WE th(d) twmdx 30 WE Pulse Width tw(we) twlwh 150 Address Setup Time tsu(a) tavwl 30 CE Setup before WE tsu(ce) telwl 0 Write Recovery Time trec(we) twmax 30 Address Hold Time th(a) tghax 20 CE Hold following WE th(ce) tgheh 20 Wait Delay Falling from WE tv(wt-we) twlwtv 35 WE High from Wait Release tv(wt) twthwh 0 Wait Width Time tw (WT) twtlwth 350 (3000 for CF+) TCADO-SCF / V5

19 6.1.9 I/O Input (Read) Timing Specification Item Symbol IEEE Symbol Min ns Max ns Data Delay after IORD td(iord) tlglqv 100 Data Hold following IORD th(iord) tlghqx 0 IORD Width Time tw(iord) tlgligh 165 Address Setup before IORD tsua(iord) tavigl 70 Address Hold following IORD tha(iord) tlghax 20 CE Setup before IORD tsuce(iord) teligl 5 CE Hold following IORD thce(iord) tlgheh 20 REG Setup before IORD tsureg(iord) trgligl 5 REG Hold following IORD threg(iord) tlghrgh 0 INPACK Delay Falling from IORD tdfinpack(iord) tlglial 0 45 INPACK Delay Rising from IORD tdrinpack(iord) tlghiah 45 IOIS16 Delay Falling from Address tdfiois16(adr) tavisl 35 IOIS16 Delay Rising from Address tdriois16(adr) tavish 35 Wait Delay Falling from IORD tdwt(iord) tlglwtl 35 Data Delay from Wait Rising td(wt) twthqv 0 Wait Width Time 350 (3000 for tw(wt) twtlwth CF+) TCADO-SCF / V5

20 I/O Input (Write) Timing Specification Item Symbol IEEE Symbol Min ns Max ns Data Setup before IOWR tsu(iowr) tdviwh 60 Data Hold following IOWR th(iowr) tlwhdx 30 IOWR Width Time tw(iowr) tlwliwh 165 Address Setup before IOWR tsua(iowr) taviwl 70 Address Hold following IOWR tha(iowr) tlwhax 20 CE Setup before IOWR tsuce(iowr) teliwl 5 CE Hold following IOWR thce(iowr) tlwheh 20 REG Setup before IOWR tsureg(iowr) trgliwl 5 REG Hold following IOWR threg(iowr) tlwhrgh 0 IOIS16 Delay Falling from Address IOIS16 Delay Rising from Address tdfiois16(adr) tavisl 35 tdriois16(adr) tavish 35 Wait Delay Falling from IOWR tdwt(iowr) tlwlwtl 35 IOWR high from Wait high tdriowr(wt) twtjiwh 0 Wait Width Time tw(wt) twtlwth 350 TCADO-SCF / V5

21 True IDE Mode I/O (Read/Write) Timing Specification True IDE Mode I/O (Read/Write Timing Specification) item Mode 0 (ns) Mode 1 (ns) Mode 2 (ns) Mode 3 (ns) Mode 4 (ns) t0 Cycle time (min) t1 Address Valid to -IORD/-IOWR setup (min) t2 -IORD/-IOWR (min) t2 -IORD/-IOWR (min) Register (8 bit) t2i -IORD/-IOWR recovery time (min) t3 -IOWR data setup (min) t4 -IOWR data hold (min) t5 -IORD data setup (min) t6 -IORD data hold (min) t6z -IORD data tristate (max) t7 Address valid to -IOCS16 assertion (max) n/a n/a t8 Address valid to -IOCS16 released (max) n/a n/a t9 -IORD/-IOWR to address valid hold trd Read Data Valid to IORDY active (min), if IORDY initially low after ta ta ta IORDY Setup time tb IORDY Pulse Width (max) TCADO-SCF / V5

22 TCADO-SCF / V5

23 True IDE Ultra DMA Mode I/O (Read/Write) Timing Specification Name UDMA Mode 0 (ns) UDMA Mode 1 (ns) UDMA Mode 2 (ns) UDMA Mode 3 (ns) UDMA Mode 4 (ns) Min Max Min Max Min Max Min Max Min Max t2cyctyp CYC t2cyc tds tdh tdvs tdvh tcs tch tcvs tcvh tzfs tdzfs tfs tli tmli tui taz tzah tzad tenv trfs trp tiordyz tziordy tack tss TCADO-SCF / V5

24 Ultra DMA Data-In Burst Initiation Timing TCADO-SCF / V5

25 Sustained Ultra DMA Data-In Burst Timing Ultra DMA Data-In Burst Host Pause Timing TCADO-SCF / V5

26 Ultra DMA Data-In Burst Device Termination Timing Ultra DMA Data-In Burst Host Termination Timing TCADO-SCF / V5

27 Ultra DMA Data-In Burst Host Termination Timing Sustained Ultra DMA Data-Out Burst Timing TCADO-SCF / V5

28 Ultra DMA Data-Out Burst Device Pause Timing Ultra DMA Data-Out Burst Device Termination Timing TCADO-SCF / V5

29 Ultra DMA Data-Out Burst Host Termination Timing TCADO-SCF / V5

30 6.2 Power Management Normal Mode The host can reduce the power consumption of the card by changing its status with the following Power Command. Sleep mode consumes the lowest power. Response time for the card to change from sleep mode to the active state is about 30 ms or less. Standby mode, the response time is about 5ms or less. This is due to the interface of the card that accepts the command although can't access the media immediately Idle mode, the card can respond and access the media immediately. The card needs longer time in this mode than in its active mode in order to active several circuits that were not used in the active mode. Active mode, the card can respond and access the media immediately, and the commands are processed with no delay Power down Mode This card can set itself into Power Down mode. To enable this mode, it is needed to use the Information Change command, which is a vender unique command. The advantage of using this mode is the ability to move automatically into Sleep mode after command completion. TCADO-SCF / V5

31 6.3 Physical Specification CompactFlash CF Type I CompactFlash CF Type II TCADO-SCF / V5

32 7. Pin Assignment 7.1 CompactFlash Pin Type PC Card Memory Mode PC Card I/O Mode True IDE Mode No. Pin Name I/O No. Pin Name I/O No. Pin Name I/O 1 GND 1 GND 1 GND 2 D03 I/O 2 D03 I/O 2 D03 I/O 3 D04 I/O 3 D04 I/O 3 D04 I/O 4 D05 I/O 4 D05 I/O 4 D05 I/O 5 D06 I/O 5 D06 I/O 5 D06 I/O 6 D07 I/O 6 D07 I/O 6 D07 I/O 7 CE1# I 7 CE1# I 7 CS0# I 8 A10 I 8 A10 I 8 A10 I 9 OE# I 9 OE# I 9 ATASEL# I 10 A09 I 10 A09 I 10 A09 I 11 A08 I 11 A08 I 11 A08 I 12 A07 I 12 A07 I 12 A07 I 13 VCC 13 VCC 13 VCC 14 A06 I 14 A06 I 14 A06 I 15 A05 I 15 A05 I 15 A05 I 16 A04 I 16 A04 I 16 A04 I 17 A03 I 17 A03 I 17 A03 I 18 A02 I 18 A02 I 18 A02 I 19 A01 I 19 A01 I 19 A01 I 20 A00 I 20 A00 I 20 A00 I 21 D00 I/O 21 D00 I/O 21 D00 I/O 22 D01 I/O 22 D01 I/O 22 D01 I/O 23 D02 I/O 23 D02 I/O 23 D02 I/O 24 WP O 24 IOIS16# O 24 IOCS16# O 25 CD2# O 25 CD2# O 25 CD2# O 26 CD1# O 26 CD1# O 26 CD1# O 27 D11 I/O 27 D11 I/O 27 D11 I/O 28 D12 I/O 28 D12 I/O 28 D12 I/O 29 D13 I/O 29 D13 I/O 29 D13 I/O 30 D14 I/O 30 D14 I/O 30 D14 I/O TCADO-SCF / V5

33 PC Card Memory Mode PC Card I/O Mode True IDE Mode 31 D15 I/O 31 D15 I/O 31 D15 I/O 32 CE2# I 32 CE2# I 32 CS1# I 33 VS1# O 33 VS1# O 33 VS1# O 34 IORD# I 34 IORD# I 34 IORD# I 35 IOWR# I 35 IOWR# I 35 IOWR# I 36 WE# I 36 WE# I 36 WE# I 37 RDY/BSY# O 37 IREQ O 37 INTRQ O 38 VCC 38 VCC 38 VCC 39 CSEL# I 39 CSEL# I 39 CSEL# I 40 VS2# O 40 VS2# O 40 VS2# O 41 RESET I 41 RESET I 41 RESET# I 42 WAIT# O 42 WAIT# O 42 IORDY O 43 INPACK# O 43 INPACK# O 43 RFU*1 O 44 REG# I 44 REG# I 44 RFU*1 I 45 BVD2 I/O 45 SPKR# I/O 45 DASP# I/O 46 BVD1 I/O 46 STSCH#G I/O 46 PDIAG# I/O 47 D08 I/O 47 D08 I/O 47 D08 I/O 48 D09 I/O 48 D09 I/O 48 D09 I/O 49 D10 I/O 49 D10 I/O 49 D10 I/O 50 GND 50 GND 50 GND Note: 1. RFU is Reserved for Feature Use TCADO-SCF / V5

34 7.2 Signal Description Signal Name Description I/O Pin VCC (PC Card Memory Mode) (PC Card I/O Mode) (True IDE Mode) GND (PC Card Memory Mode) (PC Card I/O Mode) (True IDE Mode) A0-A10 (PC Card Memory Mode) A0-A10 (PC Card I/O Mode) A0-A10 (True IDE Mode) D0-D15 (PC Card Memory Mode) (PC Card I/O Mode) D0-D15 (True IDE Mode) CD1#, CD2# (PC Card Memory Mode) (PC Card I/O Mode) (True IDE Mode) VS1#,VS2# (PC Card Memory Mode) (PC Card I/O Mode) (True IDE Mode) 5V, 3.3V 13,38 Ground. 1,50 These address lines along with the #REG signal are used to select the I/O port address registers within the card, the memory mapped port address registers within the Card, a byte in the card's information structure and its configuration control and status registers. This signal is the same as the PC Card Memory Mode signal. In True IDE Mode only A0-A2 are used to select the one of eight registers in the ATA Task File, the other address lines should be grounded. These lines carry the Data, Commands and Status between the host and controller. D00 is the LSB of the even byte of the word. D08 is the LSB of the odd byte of the word. In True IDE Mode, all Task File operations occur in the byte mode on the low order D00-D07 while all data transfers are 16 bits using D00-D15. These Card Detect pins are connected to ground on this card and used by the host to determine that the card is fully inserted into the socket. I 8,10,11,12, 14,15,16,17, 18,19,20 I/O 2,3,4,5,6, 21,22,23,27, 28,29,30,31, 47,48,49 O 25,26 Voltage Sense Signals. O 33,40 TCADO-SCF / V5

35 Signal Name Description I/O Pin CSEL# This signal is not used for this mode. I (PC Card Memory Mode) 39 CSEL# This signal is not used of this mode. (PC Card I/O Mode) CSEL# (True IDE Mode) This internally pulled up signal is used to configure this card as a Master or a Slave. When this pin is grounded, this card is Master. When this pin is open, this card is Slave. CE1#,CE2# These signals are used both to select the card and I 7,32 (PC Card Memory Mode) to indicate to the card whether a byte or a word (PC Card I/O Mode) operation is being performed. #CE2 always accesses the odd byte of the word. #CE1 accesses the even byte or the odd byte of the word depending on A0 and #CE2. CS0#, CS1# (True IDE Mode) In the True IDE Mode, #CS0 is the chip select for the Task File Registers while #CS1 is used to select the Alternate Status and the Device Control Register. BVD1 This signal is asserted high as the BVD1 signal I/O 46 (PC Card Memory Mode) since a battery is not used with this card. STSCHG# (PC Card I/O Mode) This signal is asserted low to alert the host to changes in the RDY/#BSY and Write Protect states, while the I/O interface is configured. The Card Configure and Status Register will control it. PDIAG# (True IDE Mode) In the True IDE Mode, this I/O is the Pass Diagnostic signal in the Master/Slave handshake protocol. BVD2 This signal is always driven to a high state in I/O 45 (PC Card Memory Mode) Memory Mode since a battery is not required for this card. SPKR# (PC Card I/O Mode) This signal is always driven to a high state in I/O Mode since this card does not support the audio function. DASP# (True IDE Mode) In the True IDE Mode, this I/O is the Disk Active/Slave Present signal in the Master/Slave handshake protocol. TCADO-SCF / V5

36 Signal Name Description I/O Pin OE# This is an Output Enable Strobe generated by the host interface. It is used to read data from the card in I (PC Card Memory Mode) Memory Mode and to read CIS and configuration registers. OE# In I/O Mode, this signal is used to read the CIS and (PC Card I/O Mode) configuration registers. ATASEL# To enable True IDE Mode, this signal should be (True IDE Mode) grounded. RESET When the signal is high, the signal Resets the card. I (PC Card Memory Mode) RESET When the signal is high, the signal Resets the card. (PC Card I/O Mode) RESET# In the True IDE Mode, the signal is the active low (True IDE Mode) hardware reset from the host. REG# This signal is used during Memory Cycle to I (PC Card Memory Mode) distinguish between Common Memory and Attribute Memory accesses. High for Common Memory and Low for Attribute Memory. REG# This signal must be low during I/O Cycles when the (PC Card I/O Mode) I/O address is on the Bus. RFU In the True IDE Mode, this signal is not used and (True IDE Mode) should be connected to VCC by the host. WE# This signal is driven by the host and used for I (PC Card Memory Mode) generating memory write cycle to the registers of the card when the card is configured in the Memory mode. WE# In I/O mode, this signal is used for writing the (PC Card I/O Mode) configuration registers. WE# In the True IDE Mode, this signal is not used and (True IDE Mode) should be connected to VCC by the host. WAIT#(PC Card Memory This signal is driven low by the card to notify the host O Mode) to delay completion of the memory of I/O cycle that is (PC Card I/O Mode) in progress. IORDY In the True IDE Mode, this signal may be used as (True IDE Mode) IORDY TCADO-SCF / V5

37 Signal Name I/O Pin Description INPACK# O This signal is not used in this mode. (PC Card Memory Mode) INPACK# (PC Card I/O Mode) 43 The Input Acknowledge signal is asserted when the card is selected and responds to an I/O read cycle at the address on the address bus. RFU In the True IDE mode, this signal is not used. (True IDE Mode) IORD# I This signal is not used in this mode. (PC Card Memory Mode) IORD# (PC Card I/O Mode) 34 This is an I/O Read strobe generated by the host. This signal gates I/O data onto the bus from the card when the card is configured to use the I/O interface. IORD# (True IDE Mode) In the True IDE mode, the signal is the same as the I/O Mode. IOWR# I This signal is not used in this mode (PC Card Memory Mode) IOWR# (PC Card I/O Mode) 35 The I/O Write strobe is used to clock I/O data on the Data bus into the card controller registers when the card is configured to use the I/O interface. IOWR# (True IDE Mode) In the True IDE Mode, this signal is the same as the I/O mode. RDY/BSY# O In the Memory Mode, this signal is set high when card is (PC Card Memory Mode) ready to accept a new data transfer operation and held low when the card is busy. IREQ# 37 I/O Operation. After the card has been configured for I/O (PC Card I/O Mode) Mode, this signal is used as Interrupt Request. INTRQ (True IDE Mode) In the True IDE Mode, this signal is the active high Interrupt Request to the host. WP (PC Card Memory Mode) O Memory Mode, the card doesn't have a write protect switch. This signal is held low. IOIS16# I/O Mode, A low signal indicates that a 16 bits or odd byte 24 (PC Card I/O Mode) only operation can be performed by the addressed port. IOCS16# (True IDE Mode) In the True IDE Mode, this signal is asserted low when this device is expecting a word data transfer cycle. TCADO-SCF / V5

38 8. CIS and Functions Configuration Registers Configuration register specifications This card supports four Configuration registers for the purpose of the configuration and observation of this card. These registers can be used in memory and I/O card mode. In True IDE mode, these register can not be used. 8.1 Configuration Option Register (200H) This register is used for the configuration of the card and allows issuing software reset through this register. <Reset value = 00H> D7 D6 D5 D4 D3 D2 D1 D0 SRESET LevlREQ INDEX R/W R/W R/W Index Those bits are used for selecting an operation mode of the card as follows. When Power on, Card Hard Reset and Soft Rest, this data is for the Memory mode card interface recognition. LevlREQ This bit sets to 0 when pulse mode interrupt is selected, and sets to 1 when level mode interrupt is selected. SRESET Setting this bit to 1, places the card in the reset state (Card Hard Reset).This operation is equal to Hard Reset, except this bit is not cleared. Card configuration status is reset and the card internal initialized operation starts when Card Hard Reset is executed, so next access to the card should be the same sequence as the power on sequence. Index Bits Assignment INDEX bits Task File register address Mapping mode OH to FH, 400h to 7FFH Memory mode xx0h to xxfh Independent I/O mode F0H to 1F7H, 3F6H to 3F7H 170H to 177H, 376H to 377H Primary I/O mapped Secondary I/O mapped TCADO-SCF / V5

39 8.2 Card Configuration And Status Register (Address 202H) This register is used for observing the card state. <Reset value = 00H> D7 D6 D5 D4 D3 D2 D1 D0 CHGED SIGCHG IOIS8 0 0 PWD INTR 0 R R/W R/W R/W R --- INTR PWD IOIS8 SIGCHG CHGED INTERRUPT: When set, indicates that the #IREQ pin is low. When clear, indicates that the #IREQ pin is high. This bit state is available whether I/O card interface has been configured or not. If interrupts are disabled by the #IEN bit in the Device Control Register, this bit is zero. POWER DOWN: When set, the card enters sleep state (Power Down mode). When clear, the card transfers to idle state (active mode). I/O IS 8 bit: When set, indicates that the data bus width of the host is 8 bits (D0-D7). When clear, indicates that the data bus width of the host is 16 bits (D0-D15). SIGNAL CHGED: This bit is set and reset by the host to enable and disable a state-change signal from the Status Register, the CHANGED bit control pin 46 and the CHANGED Status signal. If no state change signal is desired, this bit should be set to zero (0) and pin 46 (#STSCHG) signal will be held high while thie card is configured for I/O. Indicated that one or both of the pin Replacement Register (204H) Crdy, or CWProt bits are set to one (1). When changed bit is set, #STSCHG pin 46 is held low if the SIGCHG bit is a one (1) and the card is configured for I/O interface. TCADO-SCF / V5

40 8.3 Pin Replacement Register (Address 204H) This register is used for providing the signal state of #IREQ signal when the card configured I/O card interface. <Reset value = 0CH> D7 D6 D5 D4 D3 D2 D1 D0 0 0 CRDY RRDY RWProt --- R/W --- R/W 0 RWProt PRDY CEProt CRDY READ WRITE PROTECT: this bit indicates the write protect status. When set, indicates write protect. When cleared indicates write is enable. This bit is used to determine the internal state of the RDY/BSY signal. This bit may be used to determine the state of the Ready/Busy as this pin has been reallocated for use as interrupt Request on an I/O card. This bit is set to one (1) when RWProt changes state. This bit may be written by the host. CARD READY: This bit is set to one (1) when the READY bit changes state. This bit may be written by the host. 8.4 Socket and Copy Register (Address 206H) This register is used for identification of the card from other cards. The host can read and write this register. The host shall set this register before the card s Configuration Option Register is set. <Read, Reset value = 00H> D7 D6 D5 D4 D3 D2 D1 D DRV# R/W DRV# DRIVE NUMBER: This bit is set by the host and compared to the DRV bit (D4), in the ATA Drive/Head Register. In this way, host can perform the card s master/slave organization. TCADO-SCF / V5

41 8.5 Card Information Structure (CIS) The CIS is attribute information of the card and its characteristics, which includes information about the type of card and the manufacturer. The CIS is allocated in the beginning of the attribute memory, between addresses 0 and 255. The data is allocated in the even addresses only. The Host uses these registers to initialize and configure the card. Addr. Data Description of contents CIS function 000H 01H CISTPL_JEDEC Device info tuple Tuple code 002H 04H TPL_LINK Link length is 4 byte Link to next tuple 004H 02H Device type W Device speed P S Device type= DH: I/O device WPS=1:No WP Device Speed=7: ext speed Device type, WPS, speed 006H 79H EXT Speed Speed 400 ns if not wait Extended speed Mantissa exponent 008H 01H 1x 2k units 2k byte of address space Device size 00AH FFH List end marker End of device End marker 00CH 1CH CISTP_DEVICE_OC Other conditions device info tuple Tuple code 00EH 04H TPL_LINK Link length 4 bytes Link to next tuple 010H 02H EXT Reserved Vcc MWAIT 3V, wait is not used Other conditions info field 012H DBH Device type W Device speed P S Device type= DH: I/O device WPS=1:No WP Device Speed=1:250 ns Device type, WPS, speed 014H 01H 1x 2k units 2k byte of address space Device size 016H FFH List end marker End of device END marker 018H 18H CISTPL_JEDEC_C JEDEC ID common memory Tuple code 01AH 02H TPL_LINK Link length is 2 bytes Link to next tuple 01CH DFH PCMCIA s manufacturer s JEDEC ID of PC Card Manufacturer s ID code JEDEC ID Code ATA 01EH 01H PCMCIA JEDEC device code 2 nd byte of JEDEC ID 020H 20H CISTPL_MANFID Manufacturer s ID code Tuple code 022H 04H TPL_LINK Link length is 4 bytes Link to next tuple 024H 45H Low byte of PCMCIA manufacturer s code manufacturer s ID Low byte of manufacturer s ID code High byte of PCMCIA Code of 0 because other byte is High byte of 026H 00H manufacturer s code JEDEC 1 byte manufacturer s ID manufacturer s ID code 028H 01H Low byte of product code Low byte of product code For PC CARD ATA 02AH 04H High byte of product code High byte of product code 02CH 15H CISTPL_VERS_1 Level 1 version/product info Tuple code TCADO-SCF / V5

42 Addre ss Data Description of contents CIS function 02EH 1AH T P L _ L I N K Link length is 26 bytes Link to next tuple 030H 04H T P P L V 1 _ M A J O R PCMCIA2.0/JEIDA4.1 Major version 032H 01H T P P L V 1 _ M I N O R PCMCIA2.0/JEIDA4.1 Minor version 034H 43H C Info string 1 036H 46H F 038H 20H 03AH 43H C 03CH 61H a 03EH 72H r 040H 64H d 042H 00H Null terminator 044H 43H C Info string 2 046H 46H F 048H 41H A 04AH 20H 04CH XXH X According for card capacity. 04EH XXH X 050H XXH X 052H XXH X 054H 4DH M 056H 42H B 058H 20H 05AH 43H C 05CH 4BH K 05EH 52H S 060H 00H Null terminator 062H FFH L i s t e n d m a r k e r End of device END marker 064H 21H CISTPL_FUNCID Function ID tuple Tuple code 066H 02H T P L _ L I N K Link length is 2 bytes Link to next tuple 068H 04H TPLFID_FUNCTION=04H Disk function, may be silicon, may be removable PC card function code 06AH 01H R e s e r v e d R P R=0: No BIOS ROM P=1: Configure card at power on System initialization byte TCADO-SCF / V5

43 Addre ss Data Description of contents CIS function 06CH 22H C I S T P L _ F U N C E Function extension tuple Tuple code 06EH 02H T P L _ L I N K Link length 2 bytes Link to next tuple 070H 01H Disk function extension Disk interface type Extension tuple type for t u p l e t y p e disk 072H 01H D i s k i n t e r f a c e t y p e PC card ATA interface Interface type 074H 22H C I S T P L _ F U N C E Function extension tuple Tuple code 076H 03H T P L _ L I N K Link length is 3 bytes Link to next tuple 078H 02H Disk function extension Single drive Extension tuple type for t u p l e t y p e disk 07AH 0CH R e s e r v e D U S V No Vpp< Silicon, single drive V=0: No Vpp required S=1: Silicon U=1: Unique serial# D=0: Single drive on card Basic ATA option Parameter byte 2 07CH 0FH R I E N P3 P2 P1 P0 P0: Sleep mode supported P1: Standby mode supported Basic ATA option parameter byte 2 P2: Idle mode supported P3: Drive auto power control N: Some config excludes 3X7 E: Index bit is emulated I: Twin IOIS 16# datd reg only R: Reserved 07EH 1AH C I S T P L _ C O N F I G Configuration tuple Tuple code 080H 05H T P L _ L I N K Link length is 5 bytes Link to next tuple 082H 01H R F S R M S R A S RFS: Reserved RMS: TPCC_RMSK size-1=0 RAS:TPCC_RADR size-1=1 1 byte register mask 2 b2 byte config base address Size of fields byte TPCC_SZ 084H 03H T P C C _ L A S T Entry with config index of 03H is final entry in table Last entry of config registers 086H 00H T P C C _ R A D R ( L S B ) Configuration registers are located at 200H in REG space Location of config registers 088H 02H T P C C _ R A D A R ( M S B ) TCADO-SCF / V5

44 Addre Data Description of contents CIS function ss 08AH 0FH R e s e r v e d S P C I I: Configuration index C: configuration and status P: Pin replacement S: Socket and copy Configuration registers present mask TPCC_RMSK 08CH 1BH CISTPL_CFTABLE_ENTR Y Configuration table entry tuple Tuple code 08EH 08H T P L _ L I N K Link length is 8 bytes Link to next tuple 090H C0H I D Configuration Index Memory mapped I/O configuration I=1: Interface byte follows Configuration table index byte TPCE_INDX D=1: Default entry Configuration index=0 092H 40H W R P B Interface type W=0: Wait not used R=1: Ready active P=0: WP not used B=0: BVD1and BVD2 not used IF type=0: Memory interface Interface description field TPCE_IF 094H A1H M M S I R I O T P M=1: Misc info present MS=01: Memory space info Feature selection TPCE_FS single 2-byte length IR=0: No interrupt info present IO=0: No I/O port info present T=0: No toming info present P=1: Vcc only info 096H 01H R DI PI AI SI HV LV Nominal voltage only follows Power parameters for Vcc N V R: Reserved DI: Power down current info PI: Peak current info AI: Average current info SI: Static current info HV: Max voltage info LV: Min voltage info NV: Nominal voltage info 098H 55H X Mantissa Exponent Nominal voltage=5v Vcc nominal value TCADO-SCF / V5

45 Addre ss Data Description of contents CIS function 09AH 08H Length in 256 bytes pages Length of memory space is 2 Memory space description ( L S B ) KB structures (TPCE_MS) 09CH 00H Length in 256 bytes pages ( M S B ) 09EH 20H X R P R O A T X=0: No more misc fields R: Reserved P=1: Power down supported RO=0: Not read only mode A=0: Audio not supported T=0: Single drive Miscellaneous features field TPCE_MI 0A0H 1BH CISTPL_CFTABLE_ENTR Y Configuration table entry tuple Tuple code 0A2H 06H T P L _ L I N K Link length is 6 bytes Link to next tuple 0A4H 00H I D Configuration Index Memory mapped I/O configuration I=0: No interface byte D=0: No Default entry Configuration index=0 Configuration table index TPCE_INDX 0A6H 01H M M S I R I O T P M=0: No misc info MS=00: No memory space inflo IO=0: No I/O port info present T=0:No timing info present P=0: Vcc only info Feature selection byte TPCE_FS 0A8H 21H R DI PI AI SI HV LV NV Nominal voltage only follows Power parameters for Vcc R: Reserved DI: Power down current info PI: Peak current info AI: Average current info SI: Static current info HV: Max voltage info LV: Min voltage info NV: Nominal voltage info 0AAH B5H X Mantissa Exponent Nominal Voltage=3.0V Vcc nominal value 0ACH 1EH X Extension +0.3 V Extension byte TCADO-SCF / V5

46 Addre ss Data Description of contents CIS function 0AEH 4DH Max average current over 10 msec Max. average current X Mantissa Exponent is 45 ma 0B0H 1BH CISTPL_CFTABLE_ENTR Configuration table entry tuple Tuple code Y 0B2H 0AH TPL_LINK Link length is 10 bytes Link to next tuple 0B4H C1H Contiguous I/O mapped ATA Configuration table index registers configuration byte TPCE_INDX ID Configuration INDEX I=1: Interface byte follows D=1: Default entry Configuration index=1 0B6H 41H W=0: Wait not used Interface description field R=1: Ready active TPCE_IF W R P B Interface type P=0: WP not used B=0: BVS1 and BVS2 not used IF type=1: I/O interface 0B8H 99H M=1: Misc info present Feature selection byte MS=00: No memory space info TPCE_FS M MS IR IO T P IR=1: Interrupt info present IO=1: I/O port info present T=0: No timing info present P=1:Vcc only info 0BAH 01H Nominal voltage only follows Power parameters for R DI PI AI SI HV LV NV R: Reserved DI: Power down current info PI: Peak current info AI: Average current info SI: Static current info HV: Max voltage info LV: Min voltage info NV: Nominal voltage info Vcc 0BCH 55H X Mantissa Exponent Nominal Voltage=5V Vcc nominal value 0BEH 64H S=1: 16-bit hosts supported I/O space description R S E IO AddrLine E=1: 8-bit hosts supported IO AddrLine:4 lines decoded field TPCE_IO TCADO-SCF / V5

47 Addre Data Description of contents CIS function ss 0C0H F0H S P L M V B I N S=1: Share logic active P=1: Pulse mode IRQ supported L=1: Level mode IRQ supported M=1: Bit mask of IRQ present V=0: No vender unique IRQ B=0: No bus error IRQ I=0: No IO check IRQ N=0: No NMI Interrupt request description structure TPCE_IR 0C2H FFH IRQ IR IR IR IR IR OR IRQ0 IRQ level to be routed 0 to 15 Mask extension byte 1 7 Q Q Q Q Q Q recommended TPCE_IR C4H FFH IRQ IR IR IR IR IR OR IRQ8 15 Q Q Q Q Q Q Recommended routing to any normal, maskable IRQ Mask extension byte 2 TPCE_IR 0C6H 20H X R P R O A T X=0: Nomore misc fields R: reserved P=1: Power down supported RO=0: Not read only mode A=0: Audi not supported T=0: Single drive Miscellaneous features field TPCE_MI TCADO-SCF / V5

48 Addre ss Data Description of contents CIS function 0C8H 1BH CISTPL_CFTABLE_ENTR Y Configuration table entry tuple Tuple code 0CAH 06H T P L _ L I N K Link length is 6 bytes Link to next tuple 0CCH 01H I D Configuration index Contiguous I/O mapped ATA registers configuration I=0: No Interface byte D=0: No Default entry Configuration index=1 Configuration table index byte TPCE_INDX 0CEH 01H M M S I R I O T P M=0: No Misc info present MS=00: No memory space info IR=0: No Interrupt info present IO=0: No I/O port info present T=0: No timing info present P=1:Vcc only info Feature selection byte TPCE_FS 0D0H 21H R DI PI AI SI HV LV NV Nominal voltage only follows Power parameters for Vcc R: Reserved DI: Power down current info PI: Peak current info AI: Average current info SI: Static current info HV: Max voltage info LV: Min voltage info NV: Nominal voltage info 0D2H B5H X Mantissa Exponent Nominal voltage =3.0V Vcc nominal value 0D4H 1EH X E x t e n s i o n +0.3V Extension byte 0D6H 4DH X Mantissa Exponent Max average current over 10 msec is 45mA Max. average current TCADO-SCF / V5

49 Addre ss Data Description of contents CIS function 0D8H 1BH CISTPL_CFTABLE_ENTRY Configuration table entry tuple Tuple code 0DAH 0FH T P L _ L I N K Link length is 15 bytes Link to next tuple 0DCH C2H I D Configuration index Contiguous I/O mapped ATA registers configuration Configuration table index byte TPCE_INDX I=1: Interface byte follows D=1: Default entry follows Configuration index=2 0E0H 41H W R P B Interface type W=0: Wait not used R=1: Ready active P=0: WP not used B=0: BVS1 and BVS2 not used IF type=1: I/O interface Interface description field TPCE_IF 0E2H 99H M M S I R I O T P M=1: Misc info present MS=00: No memory space info IR=1: Interrupt info present IO=1: I/O port info present T=0: No timing info present P=1:Vcc only info Feature selection byte TPCE_FS 0E4H 01H R DI PI AI SI HV LV NV Nominal voltage only follows R: Reserved Power parameters for Vcc DI: Power down current info PI: Peak current info AI: Average current info SI: Static current info HV: Max voltage info LV: Min voltage info NV: Nominal voltage info 0E6H 55H X Mantissa Exponent Nominal Voltage=5V Vcc nominal value TCADO-SCF / V5

50 Addre ss Data Description of contents CIS function 0E8H EAH RSE IO AddrLine R=1: Range follows S=1:16-bit hosts supported I/O space description field TPCE_IO E=1: 8-bit hosts supported IO AddrLines: 10 lines decoded 0EAH 61H 0ECH FOH 1st I/O base address(lsb) 1st I/O range address 0EEH 01H 1st I/O base address(msb) 0F0H 07H 1st I/O length-1 1st I/O range length 0F2H F6H 2nd I/O base address(lsb) 2nd I/O range address 0F4H 03H 2nd I/O base address(msb) 0F6H 01H 2nd I/O length-1 2nd I/O range length 0F8H EEH SPLMIRQ level S=1: Share logic active P=1: Pulse mode IRQ supported Interrupt request description structure TPCE_IR L=1: Level mode IRQ supported M=0: Bit mask of IRQ present IRQ level is ORQ 14 0FAH 20H X R P RO A T X=0: Nomore misc fields R: reserved P=1: Power down supported RO=0: Not read only mode A=0: Audi not supported T=0: Single drive Miscellaneous features field TPCE_MI TCADO-SCF / V5

51 Addre ss Data Description of contents CIS function 0FEH 1BH CISTPL_CFTABLE_ENTRY Configuration table entry tuple Tuple code 0FCH 06H T P L _ L I N K Link length is 15 bytes Link to next tuple 100H 02H I D Configuration index ATA primary I/O mapped configuration I=0: No Interface byte D=0: No Default entry Configuration index=2 Configuration table index byte TPCE_INDX 102H 01H M M S I R I O T P M=0: No Misc info MS=00: No memory space info IR=0: No Interrupt info present IO=0: No I/O port info present T=0: No timing info present P=1: Vcc only info Feature selection byte TPCE_FS 104H 21H R DI PI AI SI HV LV NV Nominal voltage only follows R: Reserved Power parameters for Vcc DI: Power down current info PI: Peak current info AI: Average current info SI: Static current info HV: Max voltage info LV: Min voltage info NV: Nominal voltage info 106H B5H X Mantissa Exponent Nominal voltage =3.0V Vcc nominal value 108H 1EH X Extension +0.3V Extension byte 10AH 4DH Max average current over 10 Max. average current X Mantissa Exponent msec is 45mA 10CH 1BH CISTPL_CFTABLE_ENTRY Configuration table entry tuple Tuple code 10EH 0FH T P L _ L I N K Link length is 15 bytes Link to next tuple 110H C3H ID Configuration index ATA secondary I/O mapped configuration I=1: Interface byte follow D=1: Default entry Configuration index=3 Configuration table index byte TPCE_INDX TCADO-SCF / V5

52 Addre ss Data Description of contents CIS function 114H 41H W R P B Interface type W=0: Wait not used R=1: Ready active P=0: WP not used B=0: BVS1 and BVS2 not used IF type=1: I/O interface Interface description field TPCE_IF 112H 99H M M S I R I O T P M=1: Misc info present MS=00: No memory space info IR=1: Interrupt info present IO=1: I/O port info present T=0: No timing info present P=1:Vcc only info Feature selection byte TPCE_FS 116H 01H R DI PI AI SI HV LV NV Nominal voltage only follows Power parameters for Vcc R: Reserved DI: Power down current info PI: Peak current info AI: Average current info SI: Static current info HV: Max voltage info LV: Min voltage info NV: Nominal voltage info 118H 55H X Mantissa Exponent Nominal Voltage=5V Vcc nominal value 11AH EAH R S E I O A d d r L i n e R=1: Range follows S=1:16-bit hosts supported E=1: 8-bit hosts supported IO AddrLines: 10 lines decoded I/O space description field TPCE_IO 11CH 61H LS AS N range LS=1: Size of lengths is 1 byte AS=2: Size of address is 2 I/O range format description bytes N Range=1: Address range-1 11EH 70H 1st I/O base address(lsb) 1st I/O range address 120H 01H 1st I/O base address(msb) 122H 07H 1st I/O length-1 1st I/O range length 124H 76H 2nd I/O base address(lsb) 2nd I/O range address 126H 03H 2nd I/O base address(msb) 128H 01H 2nd I/O length-1 2nd I/O range length TCADO-SCF / V5

53 Addre Data Description of contents CIS function ss 12CH EEH S P L M I R Q l e v e l S=1: Share logic active P=1: Pulse mode IRQ supported Interrupt request description structure TPCE_IR L=1: Level mode IRQ supported M=0: Bit mask of IRQ present IRQ level is ORQ 14 12AH 20H X R P R O A T X=0: Nomore misc fields R: reserved P=1: Power down supported RO=0: Not read only mode A=0: Audi not supported T=0: Single drive Miscellaneous features field TPCE_MI 12EH 1BH CISTPL_CFTABLE_ENTR Y Configuration table entry tuple Tuple code 130H 06H T P L _ L I N K Link length is 6 bytes Link to next tuple 132H 03H I D Configuration index ATA secondary I/O mapped configuration I=0: No Interface byte D=0: No Default entry Configuration index=3 Configuration table index byte TPCE_INDX 134H 01H M M S I R I O T P M=0: No Misc info MS=00: No memory space info IR=0: No Interrupt info present IO=0: No I/O port info present T=0: No timing info present P=1: Vcc only info Feature selection byte TPCE_FS 136H 21H R DI PI AI SI HV LV NV Nominal voltage only follows R: Reserved DI: Power down current info PI: Peak current info AI: Average current info SI: Static current info HV: Max voltage info LV: Min voltage info NV: Nominal voltage info Power parameters for Vcc TCADO-SCF / V5