SIPS - Group. Technical Description May ISA96 Bus Specification V 1.0

Transcription

1 SIPS - Group Technical Description May 1995 ISA96 Bus Specification V 1.0

2 o:\text\normen\isa96bu1.doc SIPS - Group Specification ISA96-Bus page 1 Contents 1. Notation ISA96 Overview General Recommendations Signal Description General Address / Data Signal Group Control Signal Group Special Function Signal Group Power Electrical Characteristics CPU Bus Cycle Timing DMA Timing Specification Bus Master Exchange Operation REFRESH* Signal Timing DC Characteristics Data Conversion Data Swapping Mechanical Characteristics...21 AT and IBM are trademarks of International Business Machines The reproduction, transmission or use of this document or its contents is not permitted without expressed written authority. Offenders will be liable for damages. All rights created by patent grant or registration of a utility model or design, are reserved. (C) SIPS - Group 1995 SIPS - Group Specification ISA96-Bus page 2

3 1. Notation Throughout the specification of the ISA96 interface the following convention is used for signal notation. An asterisk (*) following a signal name indicates that the signal is active when it is at a low voltage level. A signal name that is not followed by an asterisk indicates that the signal is active when it is at a high voltage level. Additionally a high signal voltage level may be indicated by an uppercase H and a low signal voltage level by an uppercase L. There are three types of signals which are described as inputs (I), outputs (O) and bidirectional (I/O). This notation belongs to the main CPU in the system. Many signals are discussed in logical groups and are named for example as SA<15..0> SIPS - Group Specification ISA96-Bus page 3

4 2. ISA96 Overview 2. 1 General The ISA96 Bus is designed to connect a main CPU with functional IBM ATcompatible peripheral boards to create an IBM AT compatible subsystem. The parallel architecture of the ISA96 Bus, which is electrically compatible with the IBM AT bus,offers several features described below: - the memory address space is up to 16 megabyte in using a 24 bit wide address path. The data path is 16 bits wide. - the I/O address space is up to 64 kilobyte in using a 16 bit wide address path. The data path is 16 bits wide allowing 8 and 16 bit operations taking place - while using the DMA capability of the main CPU an other board can become master on the ISA96 bus. - interrupt lines (not cascadable) - support of 8 bit and 16 bit one-cycle-dma transfers between memory and I/O devices - the address lines SA<19..0> are latched the address lines LA< > are unlatched - all signals of the original IBM AT bus are available 2. 2 Recommendations It is recommended that the main CPU, which has the control of the bus (after reset), uses a DMA controller and an interrupt controller. SIPS - Group Specification ISA96-Bus page 4

5 3. Signal Description 3. 1 General This Chapter includes a detailed description of each signal of the ISA96- interface. Table 3-1 gives an overview of all signals. Table 3-1 ISA96 - Bus Pinout (total: 96 pins) SIPS - Group Specification ISA96-Bus page 5

6 ISA96 Bus Pin a b c 1 GND MASTER* IOCHCK* 2 RESETDRV SD15 SD7 3 +5V SD14 SD6 4 IRQ9 SD13 SD5 5 MEMR* SD12 SD4 6 DRQ2 SD11 SD3 7-12V SD10 SD2 8 0WS* SD7 SD V SD8 SD0 10 GND SBHE* IOCHRDY 11 SMEMW* LA23 AEN 12 SMEMR* LA22 SA19 13 IOW* LA21 SA18 14 IOR* LA20 SA17 15 DACK3* LA19 SA16 16 DRQ3 LA18 SA15 17 DACK1* LA17 SA14 18 DRQ1 DACK7* SA13 19 REFRESH* DRQ7 SA12 20 CLK DACK6* SA11 21 IRQ7 DRQ6 SA10 22 IRQ6 DACK5* SA9 23 IRQ5 DRQ5 SA8 24 IRQ4 DACK0* SA7 25 IRQ3 DRQ0 SA6 26 DACK2* MemCS16* SA5 27 T/C IOCS16* SA4 28 BALE IRQ15 SA V IRQ14 SA2 30 OSC IRQ12 SA1 31 MEMW* IRQ11 SA0 32 GND IRQ10 GND SIPS - Group Specification ISA96-Bus page 6

7 3. 2 Address / Data Signal Group SD<15..0> (I/O) These signals provide data bus bits 0 through 15 for the microprocessor, memory and I/O devices. D0 is the least-significant and D15 is the most-significant bit. All 8-bit devices on the ISA96 bus should use D0 through D7 for communication to the microprocessor. The 16-bit devices will use D0 through D15. To support 8-bit devices, the data on D8 through D15 will be gated to D0 through D7 during 8-bit transfers to these devices; 16-bit microprocessor transfers to 8-bit devices will be converted to two 8-bit transfers. Transfers to or from 16-bit devices occur on SD<7..0> when SA0 is low and on SD<15..8> when SBHE* is low SA<19..0> LA<23..17> (I/O) Address bits 0 through 23 are used to address memory and I/O devices within the system. These 24 address lines allow access of up to 16Mb of memory. These signals are latched outputs from the microprocessor or DMA Controller on the main CPU. They also may be driven by other microprocessors or DMA Controllers that reside on the ISA96 bus when the signal MASTER* is asserted (s. MASTER*) SBHE* (I/O) us High Enable indicates a transfer of data on the upper byte of the data bus, SD<15..8>. Sixteen-bit devices use SBHE* to condition data bus buffers tied to SD8 through SD15. This signal also may be driven by other microprocessors or DMA Controllers that reside on the ISA96 bus when the signal MASTER* is asserted (s. MASTER*) BALE (O) uffered Address Latch Enable is used to latch valid addresses from the microprocessor. It is available to the ISA96 bus as an indicator of valid microprocessor or DMA address (when used with AEN ). The addresses are latched with the falling edge of BALE. BALE is forced high during DMA cycles AEN (O) ddress Enable is used to degate the microprocessor and other devices from the ISA96 bus to allow DMA transfers to make place. When this line is active, DMA controller has control of the address bus. When AEN, is high two commands (IOR* and MEMW* or IOW* and MEMR*) are active at the same time. This line will be low when MASTER* is asserted. SIPS - Group Specification ISA96-Bus page 7

8 3. 3 Control Signal Group MEMR* (I/O) This signal instructs the memory devices to drive data onto the data bus. It is active on all memery read cycles. MEMR* may also be driven by other microprocessors or DMA Controllers that reside on the ISA96 bus when the signal MASTER* is asserted (s. MASTER* ). In this case it must have the address lines valide on the ISA96 bus for one system clock period before driving MEMR* active. The refresh mechanism on the main CPU strobes MEMR* during refresh cycles when the current bus owner activates REFRESH* SMEMR* (O) This signal instructs the memory device to drive data onto the data bus. It is active only when the memory address is within the low 1MByte of memory space. The refresh mechanism on the main CPU strobes SMEMR* during refresh cycles when the current bus owner activates REFRESH* MEMW* (I/O) This signal instructs the memory devices to store the data present on the data bus. It is active on all memory write cycles. MEMW* may also be driven by other microprocessors or DMA Controllers that reside on the ISA96 bus when the signal MASTER* is asserted (s. MASTER*). In this case it must have the address lines valid on the ISA96 bus for one system clock period before driving MEMW* active SMEMW* (O) This signal instructs the memory devices to store the data present on the data bus. It is active only when the memory address is wthin the low 1MByte of memory space IOR* (I/O) SIPS - Group Specification ISA96-Bus page 8

9 I/O Read` instructs an I/O device to drive its data onto the data bus. It may be driven by the microprocessor or DMA controller on the main CPU and may also be driven by other microprocessors or DMA Controllers that reside on the ISA96 bus when the signal MASTER* is asserted (s. MASTER*) IOW* (I/O) `I/O Write instructs an I/O device to store the data on the data bus. It may be driven by the microprocessor or DMA controller on the main CPU and may also be driven by other microprocessors or DMA Controllers that reside on the ISA96 bus when the signal MASTER* is asserted (s. MASTER*) IOCHRDY (I) /O Channel Ready is pulled low (not ready) by a memory or I/O device to lengthen memory or I/O cycles. Any slow device using this line should drive it low after detecting its valid address and Write or Read command. Machine cycles are extended by an integral number of clock cycles. This signal should be held low for no more than 15 microseconds MEMCS16* (I) /O 16 Chip Select is generated from a 16 - bit memory device to run a 16 - bit bus cycle. It is derived from a address decode. The main CPU converts a 16 - bit transfer automatically into 2 8- bit transfers if this signal is not asserted. The main CPU ignores the signal IOCS16* on memory cycles IOCS16* (I) /O 16 Chip Select is generated from a 16 - bit I/O device to run a 16 - bit bus cycle. It is derived from an address decode. The main CPU converts a 16 - bit transfer automatically into 2 8- bit transfers if this signal is not asserted. The main CPU ignores the signal MEMCS16* on I/O cycles REFRESH* (I/O) This signal is used to indicate a refresh cycle on the main CPU. It can also be driven by other devices that reside on the ISA96 bus when the signal MASTER* is asserted (s. MASTER*) in order to initiate a refresh cycle on the main CPU. Refresh cycles occur at a rate of one every 15.6 microseconds OWS* (I) SIPS - Group Specification ISA96-Bus page 9

10 The 'Zero Wait State' signal tells the microprocessor that it can complete the present bus cycle without inserting any additional wait cycles IOCHCK* (I) /O Channel Check provides the main CPU with error informations (e.g. parity) about devices on the ISA96 - bus. When the signal is active, it indicates an uncorrectable system error Special Function Signal Group MASTER* (I) This signal is used by a device on the ISA96 - bus to gain control of the bus. The requesting device first has to assert a DRQx line. After receiving the correspondind DACK* signal the microprocessor or DMA controller on the ISA96 - bus may pull MASTER* low, wich will allow it to control the address, data, and control lines of the bus. After MASTER* is low, the device has to wait one system clock period before driving the address and data lines, and two clock periods before issuing a Read or Write command. If this signal is held low for more than 15 microsconds, system memory may be refreshed via the REFRESH* line CLK (O) The system clock has a frequency of 8 MHz with a 50% duty cycle. All signals on the ISA96 - bus are related to this signal. Therefore the length of a bus cycle is proportional to the system clock. The length of a bus cycle depends on IOCHRDY or OWS* in integer multiples of the CLK period. This signal should be used for synchronisation OSC (O) scillator is a high - speed clock with a 70 - nanosecond period ( MHz). This signal is not synchronous with the system clock. It has a 50% duty cycle. SIPS - Group Specification ISA96-Bus page 10

11 RESETDRV (O) Reset Drive is used to reset or initialize devices on the ISA96 - bus. It is asserted at power - up time or during a cold reset of the microprocessor. This signal is active high DRQ0 - DRQ3 and DRQ5 - DRQ7 (I) DMA Requests 0 through 3 and 5 through 7 are ansynchronous channel requests used by peripheral devices and microprocessors on the ISA96 - bus to gain DMA service (or control of the system).they are priorized, with DRQ0 having the highest priority and DRQ7 having the lowest. A request is generated by driving a DRQ line to the active level. A DRQ line must be held high until the corresponding DACK line goes active. DRQ0 through DRQ3 will perform 8-bit DMA transfers; DRQ5 through DRQ7 will perform 16 - bit transfers. DRQ4 is used for cascading on the main CPU DACK0* - DACK3* and DACK5* - DACK7* (O) DMA Acknowledge 0 to 3 and 5 to 7 are used to acknowledge corresponding DMA request (DRQ0 through DRQ7 ). They are active low. DMA requesting devices use these signals as address selection in combination with AEN = H T/C (O) erminal Count rovides a pulse when the terminal count for any DMA channel is reached IRQ3 - IRQ7, IRQ9 - IRQ12 and IRQ14 - IRQ15 (I) Interrupt Requests 3 through 7, 9 through 12 and 14 through 15 are used to signal the microprocessor on the main CPU that a bus device needs attention. The interrupt requests are priorized, with IRQ9 through IRQ12 and IRQ14 through IRQ15 having the highest priority (IRQ9 is the highest) and IRQ3 through IRQ7 having the lowest priority ( IRQ7 is the lowest). An interrupt request is generated when an IRQ line is raised from a low to high. The line must be held high until the microprocessor acknowledges the interrupt request (Interrupt Service Routine). Interrupt 13 and 8 are used on the main CPU Power SIPS - Group Specification ISA96-Bus page 11

12 The ISA96 - bus provides power at +5 Volts, +12 Volts and -12 Volts. The supply current at +5 Volts is limited to 2 amps in total (1 A per pin), at +12 Volts to 1 amp, at -12 Volts to 1 amp and at GND to 3 amps. Modules consuming a higher power supply current must provide power supply through an additional connector. 4. Electrical Characteristics 4. 1 CPU Bus Cycle Timing This section specifies the timing for CPU read and write cycles (all times in ns) : No. Description Min Typ Max Note 1 Clock period Tclk) BALE high width 54 3 SA<1..0> setup to BALE low 8 4 SBHE* setup to BALE low 20 5 SA<19..2>LA<23..17> setup to BALE low 130 SIPS - Group Specification ISA96-Bus page 12

13 6a Command width 16 bit cycles 125 2) (with zero wait states) 6b Command with 8 bit cycles 325 3) (with 2 wait states) 7 SA<1..0> setup to command 8 1) (with zero command delay) 8 SBHE* setup to command 20 1) (with zero command delay) 9 SA<19..2>LA<23..17> setup to command 130 1) (with zero command delay) 10 MEMCS16*, IOCS16* delay from 80 SA<19..2>LA<23..17> 11 MEMCS16*, IOCS16* hold after 0 SA<19..2>LA<23..17> 12a SA<1..0> hold after command 23 12b SA<1..0> hold after SMEMR* or SMEMW* 18 13a SBHE* hold after command 23 13b SBHE* hold after SMEMR* or SMEMW* 18 14a SA<19..2>LA<23..17> hold after command 30 14b SA<19..2>LA<23..17> hold 25 after SMEMR* or SMEMW* 15 Write Data setup to command active 6 16 Read Data setup to command inactive 65 1) 17a Write Data hold after command 45 17b Read Data hold after command 0 18 IOCHRDY setup to CLK IOCHRDY hold after CLK 2 20 OWS* setup to CLK OWS* hold after CLK 0 Notes: 1) Command delay programmable between 0 and 3 CLK/2 cycles seperately for 16 - bit memory, 8 - bit memory and I/O cycles 2) Command width is correlated to the number of wait states (programmable from 0 to 3 CLK cycles ) and command delay (note 1) 3) note 2) with programmable wait states from 2 to 5 CLK cycles SIPS - Group Specification ISA96-Bus page 13

14 19 LA<23..17> SIPS - Group Specification ISA96-Bus page 14

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16 4. 2 DMA Timing Specification This section specifies the timing for Direct Memory Access cycles (all time in ns): No. Description MIN TYP MAX Note 1 Clock period (Tclk ) IOCHRDY setup to CLK 35 3 IOCHRDY hold from CLK 20 4 DRQ inactive delay from command 55 5 AEN setup to command 80 6 AEN hold from command 10 7 SA<19..0>LA<23..17> setup to command 50 8 SA<19..0>LA<23..17> hold from command 50 9 DACK setup to command 0 10 DACK hold from command 0 11 Extended Write delay Write command width 80 1) (Extended Write, 0 Waitstates) 13 Read inactive delay from Write T/C delay from command T/C hold from command 0 16 Read data setup Read data hold 0 18 Write data delay after command 80 2) 19 Write data hold 15 Notes: 1) with programmable wait states from 1 to 4 CLK cycles 2) Note that this time cannot be extended by insertion of wait states SIPS - Group Specification ISA96-Bus page 16

17 19 LA<23..17> SIPS - Group Specification ISA96-Bus page 17

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19 4. 3 Bus Master Exchange Operation This section specifies the timing for exchange of bus ownership between the CPU and a secondary Busmaster (all times in ns) : No. Description MIN TYP MAX Note 1 MASTER* delay after DACKn* 0 2 AEN inactive after MASTER* active 45 3 CPU tristates bus signals 45 4 DACKn* inactive from DRQn inactive 0 5 MASTER* delay from DRQn inactive AEN delay after MASTER* inactive CPU drives bus signals 0 8 Secondary Master tristates bus signals 0 LA<23..17> 19 SIPS - Group Specification ISA96-Bus page 19

20 4. 4 REFRESH* Signal Timing This section specifies the timing for the REFRESH* signal No. Description MIN TYP MAX 1 REFRESH* pulse width 750 ns 2 REFRESH* inactive time 15,6 us SIPS - Group Specification ISA96-Bus page 20

21 4. 5 DC Characteristics Requirements for Bus Drivers The table shows the requirements for the bus drivers. There are some definitions described below : T.S. Tri State Driver O.C. Open Collector Driver T.P. Totem Pole Driver Note: Current flow is denoted positiv if it enters a driver and negative if it leaves the driver. Table Signal Driver Iol min.ma Ioh min.ma Iil max.ma Iih max.ma Type (Vol = 0.5V) (Voh = 2.4V) (Vil = 0.4V) (Vih = 2.7V) SD T.S SA T.S LA T.S SBHE* T.S BALE T.P AEN T.P MEMR* T.S MEMW* T.S IOR* T.S IOW* T.S SMEMR* T.S SMEMW* T.S IOCHRDY O.C. 24 (*) -.4 SIPS - Group Specification ISA96-Bus page 21

22 MEMCS16* O.C. 24 (*) -.4 IOCS16* O.C. 24 (*) -.4 REFRESH* O.C. 24 (*) -.4 OWS* O.C. 24 (*) -.4 IOCHCK* O.C. 24 (*) -.4 MASTER* O.C. 24 (*) -.4 CLK T.P OSC T.P RESETDRV T.P DRQ T.P DACK* T.P T/C T.P IRQ T.P (*) The Ioh of all O.C. driver must be max. 400 microamps at 2. 4V Pullup Requirements The table shows the pullup requirements for the system Table Pullup Requirements Value ( Ohms ) IOCHRDY 1K IOCHCK* 1K REFRESH* 470 All other signals with driver type O.C. 470 SD<15..0> (if special backplane is used ) 10K MEMR* 10K MEMW* 10K IOR* 10K IOW* 10K SIPS - Group Specification ISA96-Bus page 22

23 SMEMR* SMEMW* 10K 10K Data Conversion 16 - bit transfers by the main CPU via the ISA96 - bus are converted into two 8 - bit trnsfers (low and high Byte ) if the control signals MEMCS16* or IOCS16* are not asserted. The higher Byte - Data (SD<15..8> ) is directed to SD <7..0> with SA0 =H during write cycles and from SD <7..0> to SD <15..0 > with SA0 =H during read cycles. This operation is transparent to the software. SIPS - Group Specification ISA96-Bus page 23

24 4. 7 Data Swapping Data are swapped between SD <15..8 > and SD <7..0 > on the main CPU for odd Byte transfers (SA0 =H) with 8 - bit devices on the ISA96 - bus. Swapping occurs also during DMA cycles (SA0 =H) if the devices on the ISA96 - bus is a 16 - bit memory device and an 8 - bit DMA channel is used for the transfer. 5. Mechanical Characteristics The interconnection between two boards via the ISA96 - bus will be done with a 96 pin DIN Connector. A right - angle 96 pin male connector connects all boards, which use the ISA96 bus interface to a special backplane. SIPS - Group Specification ISA96-Bus page 24

25 ISA96 SIPS - Group Specification ISA96-Bus page 25