CREMSON- Subboard Documentation. Fujitsu Microelectronics Europe GmbH Am Siebenstein Dreieich-Buchschlag, Germany

Transcription

1 CREMSON- Subboard Documentation Fujitsu Microelectronics Europe GmbH Am Siebenstein -0 0 Dreieich-Buchschlag, Germany

2 History Revision Date Comment V New Document V Update (redesign of board) V New board plan

3 Warranty and Disclaimer To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH restricts its warranties and its liability for all products delivered free of charge (e.g. software include or header files, application examples, target boards, evaluation boards, engineering samples of IC s etc.), its performance and any consequential damages, on the use of the Product in accordance with (i) the terms of the License Agreement and the Sale and Purchase Agreement under which agreements the Product has been delivered, (ii) the technical descriptions and (iii) all accompanying written materials. In addition, to the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH disclaims all warranties and liabilities for the performance of the Product and any consequential damages in cases of unauthorised decompiling and/or reverse engineering and/or disassembling. Note, all these products are intended and must only be used in an evaluation laboratory environment.. Fujitsu Microelectronics Europe GmbH warrants that the Product will perform substantially in accordance with the accompanying written materials for a period of 0 days form the date of receipt by the customer. Concerning the hardware components of the Product, Fujitsu Microelectronics Europe GmbH warrants that the Product will be free from defects in material and workmanship under use and service as specified in the accompanying written materials for a duration of year from the date of receipt by the customer.. Should a Product turn out to be defect, Fujitsu Microelectronics Europe GmbH entire liability and the customer s exclusive remedy shall be, at Fujitsu Microelectronics Europe GmbH sole discretion, either return of the purchase price and the license fee, or replacement of the Product or parts thereof, if the Product is returned to Fujitsu Microelectronics Europe GmbH in original packing and without further defects resulting from the customer s use or the transport. However, this warranty is excluded if the defect has resulted from an accident not attributable to Fujitsu Microelectronics Europe GmbH, or abuse or misapplication attributable to the customer or any other third party not relating to Fujitsu Microelectronics Europe GmbH.. To the maximum extent permitted by applicable law Fujitsu Microelectronics Europe GmbH disclaims all other warranties, whether expressed or implied, in particular, but not limited to, warranties of merchantability and fitness for a particular purpose for which the Product is not designated.. To the maximum extent permitted by applicable law, Fujitsu Microelectronics Europe GmbH and its suppliers liability is restricted to intention and gross negligence. NO LIABILITY FOR CONSEQUENTIAL DAMAGES To the maximum extent permitted by applicable law, in no event shall Fujitsu Microelectronics Europe GmbH and its suppliers be liable for any damages whatsoever (including but without limitation, consequential and/or indirect damages for personal injury, assets of substantial value, loss of profits, interruption of business operation, loss of information, or any other monetary or pecuniary loss) arising from the use of the Product. Should one of the above stipulations be or become invalid and/or unenforceable, the remaining stipulations shall stay in full effect.

4 Important notice This Starterkit contains an evaluation board, documentation and software on a CD-ROM. For documentation or software updates, please refer to our web site Fujitsu reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice..0.0 V.0

5 . Introduction The CREMSON-Subboard is a low cost multifunctional evaluation board for Fujitsu graphic device controller Cremson. It can be used with CREMSON-Starterkit CPU-Modul only for software development and testing as a simple target board. The board allows the designer immediately to start the software development before his own final target system is available.. Features Graphic controller Cremson in a package FPT-0P-M0. MHz oscillator high-performance Mbit SDRAM s designed for demanding multimedia applications (MBFB) PALLVV a ALS0 (six not inverted buffer) LEDs for power supply Display interface (HD-DSUB-BU-Pol) CPU-Modul interface Reset button for Cremson

6 . Jumpers and Switches This chapter describes all jumpers and switches which can be modified on the evaluation board. The default setting is shown with a gray shaded area. All jumpers and switches are named directly on the board by its meaning, so it is very easy to set the jumpers according to the features.. Power Supply Voltage (JP, JP, JP) Jumper setting V power supply Power supply (JP) NO Power supply Jumper setting V power supply Power supply (JP) NO Power supply Jumper setting V power supply Analog Power supply (JP) NO Analog Power supply NOTE: The supply voltage for the core and the IO Pins must be set. Otherwise it could happen that the controller does not work correctly!

7 . Define graphic controller Operating Mode (SW) The Cremson can be connected to Fujitsu FR0, Hitachi SH(SH0), SH(SH0/0A) and NEC V. The host CPU type is specified by the MODE pins. CPU Type SW/Mode0 SW/Mode FR0/SH ON ON Mode-0 SH OFF ON V ONF OFF Reserved OFF OFF Clock mode signal SW/CKM ON OFF Output from internal PLL is selected Host CPU bus clock is selected Even/Odd signal mode SW/EO ON OFF Low level output in even frame, High level output in odd frame High level output in even frame, Low level output in odd frame

8 . Reset Pin (JP) The Jumper JP determines the Scarlet Reset Pin. It can be connected directly with the Reset of the VGC, or with a port of the MCU, to execute a software Reset. JP Reset - MCU Reset - Software Reset (Port S0). PLL power supply voltage (JP) PLL power supply. C-sync for display (JP) JP - - PLLVDD connect to core voltage PLLVDD connect to separated voltage C-sync JP C-sync connected to VGA connector C-sync not connected. PAL Settings (JP, JP, JP, JP, JP0, JP, JP, JP, JP, JP, JP, JP, JP, JP, JP0, JP) Bus clock for PALLVV JP Needed for internal state machine - Wait request JP Wait request from Scarlet - JP Read strobe Read signal to Scarlet -

9 JP Write strobe XWE0 Write signal D0 D - JP Write strobe XWE Write signal D D - JP Write strobe XWE Write signal D D - JP Write strobe XWE Write strobe D D - DMA acknowledge JP Not needed for internal logic DMA end operation JP0 Not needed for internal logic Bus clock for PALLVV JP Not needed for internal logic CS JP CS for PAL logic enable CS for PAL logic disable

10 CS JP CS for PAL logic enable CS for PAL logic disable CS JP CS for PAL logic enable CS for PAL logic disable CS JP CS for PAL logic enable CS for PAL logic disable JP0 PAL Reset PAL Reset from MCU - JP Reset Switch Reset from switch SW -. Interrupt Interrupt enable JP / JP Connected interrupt to MCU Not connected. DMA DREQ0 enable JP / JP Connected DREQ0 to MCU Not connected 0

11 . Header for Debug Signals Analog Output (JP0) DCLK_OUT - Dot Clock Signal for Display DCLK_IN - Dot Clock Input for External Synchronization RED - Analog signal output (RED) GREEN - Analog signal output (GREEN) BLUE - Analog signal output (BLUE) H_SYNC - Horizontal sync signal output V_SYNC - Vertical sync signal output C_SYNC - Composite sync signal output GV - Video/Graphics Switch Chip Select Signals(JP) CS0- - Chip Select from MCU PWM (JP) PortS- - Free usable Port S (bit ) Power Supply Voltage (JP) Power supply voltage (V, V, V0) GND Buffer signals (JP, JP, JP, JP, JP, JP, JP0, JP) I/O Pins for ALS0 (six not inverted buffer) PAL Output Pins (JH, JH, JP, JP, JP) Not used in internal Logic For more information please look at the Hardware Manual of the Cremson graphic controller and the Data Sheet of the PALLVV.

12 . Schematics and Drawings

13 D D C C B B A A Abschluss der MEMORY-CLOCK-Leitung beachten!!! MASSEKONZEPT: die analoge Masse bitte als Masseinsel ausfuehren und die digitale Masse sternförmig!! CREMSON-Subboard / CREMSON. CREMSON-Subboard (CREMSON-STARTERKIT-CRM), FUJB A Thursday, March, 00 Title Size Document Number Rev Date: Sheet of VccV_ VccV0 D0 D D D D D D D D D D0 A A A A A A PortS0 PortS PortS Interrupt_A D D VccV_ D0 D D A A PortS A PortS D D D A A D A A0 D AS CS CS CS WR0 Bus_CLK FR_WAIT DACK0 WR CS DREQ0 WR DEOP0 CS FR_Reset WR CS CS0 RDX D A D D A0 D D A D D D PortS PortS A D0 A PortS A D D VccV0 VccV_ VccV_ VccV_ CRM_MODE0 CRM_TEST VccV_ VccV_ PAL_CS Interrupt_A DREQ0 DACK0 DEOP0 D CRM_TEST RDX CRM_MODE PAL_A A D D PAL_A A D CRM_TEST CRM_TEST0 CRM_V CRM_TEST A0 A D PLLVDD PAL_Reset D D D D PAL_DRACK A CRM_TEST CRM_WAIT WR D D D CRM_MODE CRM_TEST0 A D D CRM_TEST PAL_A A D CRM_DREQ Bus_CLK A A0 D D CRM_TEST PAL_DTACK WR0 A D D CRM_XINT WR WR D0 D D0 D D0 A D D CRM_TEST CRM_TEST PAL_CS CRM_MODE0 A A D PAL_A A A A A D D D0 AS A A D D RED GREEN BLUE H_SYNC V_SYNC C_SYNC DCLK_OUT DCLK_IN CLK_M CRM_TEST CRM_V CLK_M MCLK MCLKI MCLKI CRM_XINT CRM_DREQ Interrupt_A A_GND Reset_SW RED GREEN BLUE H_SYNC V_SYNC H_SYNC GREEN C_SYNC DCLK_OUT BLUE V_SYNC DCLK_IN RED GV GV CRM_EO VccV_ VccV_ PLLVDD PortS PortS CS PortS PortS CS CS0 PortS PortS CS PortS CS CS CS VccV_ VccV0 PAL_Reset DEOP0 RDX PAL_DRACK PAL_DTACK WR PAL_RES_in PortS0 CS CS PAL_A CS PAL_A CS WR Reset_SW WR FR_Reset DACK0 PAL_CS PAL_A Bus_CLK FR_WAIT Bus_CLK PAL_RES_in WR0 PAL_A CRM_WAIT CRM_CKM CRM_CKM A_GND VccV0 CRM_V D_GND CRM_V D_GND A_GND A_GND PAL_CS DREQ0 CRM_CKM CRM_EO CRM_EO MDQM MCKE MD MD MD MD MDQM MA MA0 MD0 MD MD MDQM MD MD MD0 MD MDQM MD0 MD MD MD MD0 MA MA MD MD MD MA0 MD MD MD MD MD MD MD MWE MA MD MD MD MD MRAS MD MD MD MD MA MA MD MD MD MD MCLK MDQM0 MA MD MD MDQM MA MD MD MA MD MD MD MD MD MD MD MD MD MDQM MA MD MD MD MA MD0 MD MD MD MD MDQM MCAS MD MD MD MD0 MD0 VccV_ VccV0 JH HEADER JDRB DIN _ABC-R B B B B B B B B B B0 B B B B B B B B B B0 B B B B B B B B B B0 B B B B B B B B B B B B0 B B B B B B B B B B0 B B B B B B B B B B0 B B JDRA DIN _ABC-R A A A A A A A A A A0 A A A A A A A A A A0 A A A A A A A A A A0 A A A A A A A A A A A A0 A A A A A A A A A A0 A A A A A A A A A A0 A A R 0k JP PortS.. JP VGA-Stecker (SUB-D, pol, -reihig, weiblich) 0 JDRC DIN _ABC-R C C C C C C C C C C0 C C C C C C C C C C0 C C C C C C C C C C0 C C C C C C C C C C C C0 C C C C C C C C C C0 C C C C C C C C C C0 C C SW SW DIP- JP HEADER JDRC DIN _ABC-R C C C C C C C0 C C C C C C C C C C C C C C C C0 C C C C C C C C C JDRA DIN _ABC-R A A A A A A A A A A A A A A0 A A A A A A A A A A A A A A A A0 A A JDRB DIN _ABC-R B B B B B B B0 B B B B B B B B B B B B B B B B0 B B B B B B B B B UD ALS0 JP UE ALS0 0 UF ALS0 UC ALS0 JP0 Analog-out 0 JP CS0.. JP VddL Y Oszillator_.MHz JP VddH JP Vcc_ANALOG JP0 JUMPER C0 JP HEADER C 00pF R 00k UA ALS0 JP0 R 0R C UB ALS0 R 0R R k + C uf SW CREMSON_RESET C C JP JUMPER JP C U CREMSON D0 D D D D D D D D D D0 D D D D D D D D D D0 D D D D D D D D D D0 D A A A A A A A A A0 A A A A A A A A A A0 A A A A MD0 MD MD MD MD MD MD MD MD MD MD0 MD MD MD MD MD MD MD MD MD MD0 MD MD MD MD MD MD MD MD MD MD0 MD MD MD MD MD MD MD MD MD MD0 MD MD MD MD MD MD MD MD MD MD0 MD MD MD MD MD MD MD MD MD MD0 MD MD MD MA MA MA MA MA MA0 MA MA MA MA0 MA MA MA MA XRESET MODE0 MODE BCLKI XBS XCS XRD XWE0 XWE XWE XWE XRDY DREQ DRACK DTACK XINT TEST0 TEST TEST TEST TEST TEST MRAS MCAS MWE MCKE MDQM0 MDQM MDQM MDQM MDQM MDQM MDQM MDQM MCLKO MCLKI DCLKO DCLKI AOUTR AOUTG AOUTB HSYNC VSYNC CSYNC EO GV VREF ACOMPR ACOMPG ACOMPB VRO Vss- Vss- Vss- Vss- Vss- Vss- Vss- Vss- Vss- Vss-0 Vss- Vss- Vss- Vss- Vss- Vss- Vss- Vss- Vss- Vss-0 VddL- VddL- VddL- VddL- VddL- VddL- VddL- VddL- VddL- VddL- VddH- VddH- VddH- VddH- VddH- VddL- VddL-0 VddH- VddH- VddH- VddH- VddH-0 AVD0(VCO) CLK S AVS0 CKM AVS AVD AVS AVD AVD AVS AVD AVS <open> JP JUMPER R0 0R C C JP JUMPER R 0R R.k JP JUMPER JP C JP HEADER U V (Sockel) 0 0 I0 I I I I I I I I I F0 F F F F F F F VCC GND C C 0.uF C C C 0.uF C JP JP HEADER C JP PLLVDD-select C C 0.uF JP R 0R JP HEADER C C JP HEADER JP D CREMSON_Reset C JP JP HEADER C C R 0R C0 C R 0R C R x k C0 R 0R C C JP HEADER JP0 JP JP JP HEADER JP C_SYNC JP C JP0 HEADER JP C U V (Sockel) 0 0 I0 I I I I I I I I I F0 F F F F F F F VCC GND JP JP HEADER C JP C R x k RGND 0R JP RES_select JP C

14 D D C C B B A A CREMSON-Subboard / Memory. CREMSON-Subboard (CREMSON-STARTERKIT-CRM), FUJB A Thursday, March, 00 Title Size Document Number Rev Date: Sheet of D_GND D_GND VccV_ VccV_ VccV0 VccV0 VccV_ VccV0 VccV0 VccV_ D_GND MD0 MD MD MD MD MD MD MD MD MD MD0 MD MD MD MD MD MD MD MD MD MD0 MD MD MD MD MD MD MD MD MD MD0 MD MA0 MA MA MA MA MA MA MA MA MA MA0 MA MA MA MA MA0 MA MA MA MA MA MA MA MA MA0 MA MD MD MD MD MD MD MD MD MD0 MD MD MD MD MD MD MD MD MD MD0 MD MD MD MD MD MD MD MD MD MD0 MD MD MD MWE MCAS MRAS MCAS MWE MRAS MCKE MCLK MCLK MCKE MDQM0 MDQM MDQM MDQM MDQM MDQM MDQM MDQM VccV0 VccV_ C0 C TP GND C C C C C C0 U MBFB-0FN-X Vcc- DQ0 VccQ- DQ DQ VssQ- DQ DQ VccQ- DQ DQ VssQ- DQ n.c.- Vcc- DQM0 /WE /CAS /RAS /CS n.c.- A A A0 / AP A0 A A DQM Vcc- n.c.- DQ VssQ- DQ DQ VccQ- DQ DQ0 VssQ- DQ DQ VccQ- DQ Vcc- Vss- DQ VssQ- DQ DQ VccQ- DQ DQ VssQ- DQ DQ0 VccQ- DQ n.c.- Vss- DQM A A A A A A A CKE CLK n.c.- n.c.- DQM Vss- n.c.- DQ VccQ- DQ DQ0 VssQ- DQ DQ VccQ- DQ DQ VssQ- DQ Vss- C C C C C C JP Vcc C0 C C R k D V R 0R R0 0R D V0 D V U MBFB-0FN-X Vcc- DQ0 VccQ- DQ DQ VssQ- DQ DQ VccQ- DQ DQ VssQ- DQ n.c.- Vcc- DQM0 /WE /CAS /RAS /CS n.c.- A A A0 / AP A0 A A DQM Vcc- n.c.- DQ VssQ- DQ DQ VccQ- DQ DQ0 VssQ- DQ DQ VccQ- DQ Vcc- Vss- DQ VssQ- DQ DQ VccQ- DQ DQ VssQ- DQ DQ0 VccQ- DQ n.c.- Vss- DQM A A A A A A A CKE CLK n.c.- n.c.- DQM Vss- n.c.- DQ VccQ- DQ DQ0 VssQ- DQ DQ VccQ- DQ DQ VssQ- DQ Vss-