Application Note APIX PRBS

Transcription

1 Application Note APIX Rev March 2016 Graphic Competence Center GCC 1

2 Warranty and Disclaimer The use of the deliverables (e.g. software, application examples, target boards, evaluation boards, starter kits, schematics, engineering samples of IC s etc.) is subject to the conditions of (SNEU) as set out in (i) the terms of the License Agreement and/or the Sale and Purchase Agreement under which agreements the Product has been delivered, (ii) the technical descriptions and (iii) all accompanying written materials. Please note that the deliverables are intended for and must only be used for reference in an evaluation laboratory environment. The software deliverables are provided on an as-is basis without charge and are subject to alterations. It is the user s obligation to fully test the software in its environment and to ensure proper functionality, qualification and compliance with component specifications. Regarding hardware deliverables, SNEU warrants that they will be free from defects in material and workmanship under use and service as specified in the accompanying written materials for a duration of 1 year from the date of receipt by the customer. Should a hardware deliverable turn out to be defect, SNEU s entire liability and the customer s exclusive remedy shall be, at SNEU s sole discretion, either return of the purchase price and the license fee, or replacement of the hardware deliverable or parts thereof, if the deliverable is returned to SNEU in original packing and without further defects resulting from the customer s use or the transport. However, this warranty is excluded if the defect has resulted from an accident not attributable to SNEU, or abuse or misapplication attributable to the customer or any other third party not relating to SNEU or to unauthorized decompiling and/or reverse engineering and/or disassembling. SNEU does not warrant that the deliverables do not infringe any third party intellectual property right (IPR). In the event that the deliverables infringe a third party IPR it is the sole responsibility of the customer to obtain necessary licenses to continue the usage of the deliverable. In the event the software deliverables include the use of open source components, the provisions of the governing open source license agreement shall apply with respect to such software deliverables. To the maximum extent permitted by applicable law SNEU disclaims all other warranties, whether express or implied, in particular, but not limited to, warranties of merchantability and fitness for a particular purpose for which the deliverables are not designated. To the maximum extent permitted by applicable law, SNEU s liability is restricted to intention and gross negligence. SNEU is not liable for consequential damages. Should one of the above stipulations be or become invalid and/or unenforceable, the remaining stipulations shall stay in full effect. The contents of this document are subject to change without a prior notice, thus contact SNEU about the latest one. Should one of the above stipulations be or become invalid and/or unenforceable, the remaining stipulations shall stay in full effect. 2

3 Revision History Date Revision Description Initial Reviewed and Socionext layout applied Socionext layout and new document code added. 3

4 Contents 1. Introduction overview Block Diagram Inova Socionext Inova Pattern Checker in Receiver Pattern Generator in Transmitters Socionext Known Limitations (downstream) Selection of Active Channels Programming a Pattern Programming a Fixed Pattern of Variable Length Other Pattern Types (Downstream) Pattern Rate (Downstream) Pattern Checker (Downstream) Pattern Type (Upstream) Pattern Rate (Upstream) Pattern Checker (Upstream) Standard Patterns

5 1. Introduction The device is a multi-channel graphics controller device incorporating 3 APIX transmitters and 1 APIX receiver interfaces. APIX is a propriety interface of Inova Semiconductors GmbH. This application note describes the setup of the generators and checkers available. 5

6 2. overview Block Diagram Analog Rx Fujitsu logic Checker Downstream Inova Receiver logic Checker Upstream Analog Tx2 Upstream & Pattern Generator Checker Inova Transmitter logic Downstream Generator Analog Tx1 Upstream Checker Inova Transmitter logic Downstream Generator Analog Tx0 Upstream Checker Inova Transmitter logic Downstream Generator Figure 1 : Pattern Generators and Checkers Inova The link level logic from Inova includes a pattern generator/checker for the downstream data paths. The transmitter can generate 4 patterns (8,10,12,16-bit) or a fixed 16-bit pattern. The receiver can check the patterns. 6

7 1.1 Socionext The Socionext generator uses a freely programmable 16-bit polynomial capable of generating and checking any up to 16-bit length or any fixed pattern up to 16-bit length. 32 bit fixed patterns can also be generated. The pattern generators and checkers are available on both downstream and upstream paths. Only 3Gbps and 1Gbps patterns can be generated see section 3.1 (limitations). 7

8 2 Inova APIX mode and bit rate are selected as required by the application. Pattern Checker in Receiver Register Name Address Bits Type Field Name Comment TEST_CONFIG 0x3A :11 RW psrtest_8b10b 00 = 8 01 = = = RW psrtest_mode 1= test enable TEST_STS_DATA 0x3A :0 R BistErrCnt Error count APIX_ctrl_1 0x3A W1P BistErrCntClear Write 1 to clear error count dbg_status_data_3 0x3A :16 R dbg_status_data_0x0f dbg_status_data_0x10 16-bit raw data (LSB first, MSB newest) Pattern Generator in Transmitters Register Name Address Bits Type Field Name Comment TEST_CONFIG 0x3A0* :16 RW test_config_data_0x03/0x04 16-bit fixed test pattern (LSB is sent first) 12 RW testpattern_en 1= enable fixed test pattern 11 RW psrtest_mode 1= enable * = 1,2,3 for Tx0,1,2 10:9 RW psrtest_8b10b 00 = 8 01 = = = 16 APIX data is sent LSB first. The Socionext generator should be disabled when using the Inova generator. 8

9 3. Socionext The Socionext generator uses a freely programmable 16-bit polynomial. It is capable of generating: any of up to 16-bit length fixed patterns of up to 16-bit length 32-bit fixed patterns 16-bit incrementing patterns The same pattern/polynomial is used for all generators and checkers, including downstream and upstream paths. The downstream transmit pattern rate is set by the receiver downbw see section 3.6. Channels that transmit or receive the pattern are enabled individually see section 3.2 Known Limitations (downstream) Mode Pattern Limitation APIX2 32-bit fixed 3Gbps only 3Gbps only APIX1 32-bit fixed 1Gbps only. Not recognized by pattern checker. 16-bit fixed 8bit pattern 8lsbs of BistStartValue 1Gbps only Selection of Active Channels The pattern generator can output on 4 transmitters (3 downstream, 1 upstream). Each receiver (1 downstream, 3 upstream) has a checker. BistMode 0x3A RW Down0_Tx_En Down1_Tx_En Down2_Tx_En Downstream transmitters 1= enable 12 Down_Rec_Tx_En Downstream checker 16 Up_Tx_En Upstream transmitter Up0_Rec_En Up1_Rec_En Up2_Rec_En Upstream checkers 9

10 Programming a Pattern The pattern generator implements a 16-bit Fibonacci many-to-one LFSR structure. A LSFR Polynominal is defined by its feedback coefficients, eg X8 + X6 + X5 + X1 +1 Each active feedback is indicated by a 1 giving, but since X0 = 1 is always 1, this is assumed. Therefore, for example: X 8 +X 6 +X 5 +X *X 8 +0*X 7 +1*X 6 +1*X 5 +0*X 4 +0*X 3 +0*X 2 +1*X 1 (+1) = 0x B1 Polynomials for various sequences are listed in section 4. The seed is read from BistStartValue. BistPatType 0x3A :0 RW Bist_Pat_Type Set to 0 () BistPolynomial 0x3A :0 RW Bist_Polynomial Polynomial BistStartValue 0x3A00081C 15:0 RW Bist_Start_Value seed for (do not set to 0) Bist_SWreset 0x3A W1P Bist_SWRes Write 1 to restart* BistMode 0x3A RW *Restart after changing Bist_Polynomial or Bist_Start_Value Down0_Tx_Data_Swap Down1_Tx_Data_Swap Down2_Tx_Data_Swap Down_Rec_Data_Swap Set to 1 Programming a Fixed Pattern of Variable Length A fixed pattern on length up to 16 bits can be configured by setting a single 1 at the desired length. The fixed pattern is defined by BistStartValue. BistPatType 0x3A :0 RW Bist_Pat_Type Set to 0 () BistPolynomial 0x3A :0 RW Bist_Polynomial Polynomial. Set only 1 bit. Eg 0x1000 = 13-bit pattern BistStartValue 0x3A00081C 15:0 RW Bist_Start_Value Fixed pattern (lsbs used) Bist_SWreset 0x3A W1P Bist_SWRes Write 1 to restart* BistMode 0x3A RW *Restart after changing Bist_Polynomial or Bist_Start_Value Down0_Tx_Data_Swap Down1_Tx_Data_Swap Down2_Tx_Data_Swap Down_Rec_Data_Swap Set to 1 10

11 Example: To configure an 11-bit fixed pattern: Bist_Polynomial = 0x Bist_Start_Value = 0x0000ABCD Returns a sequence 0x3CD ( ) (In this case only the 11 LSBs of Bist_Start_Value are used) Other Pattern Types (Downstream) 16-bit fixed and incrementing patterns can be generated and checked. 32-bit fixed pattern can be generated, but not checked automatically. BistPatType 0x3A :0 RW Bist_Pat_Type 0= (see above) 1= fix 16-bit Pattern 2= fix 32-bit Pattern 3= 16-bit incrementing pattern BistStartValue 0x3A00081C 31:0 RW Bist_Start_Value Fix 32-bit Pattern 15:0 Fix 16-bit Pattern 15:0 Start value for incrementing pattern BistDelta 0x3A :0 RW Bist_Delta Increment value Bist_SWreset 0x3A W1P Bist_SWRes Write 1 to restart* BistMode 0x3A RW *Restart after changing Bist_Polynomial or Bist_Start_Value Down0_Tx_Data_Swap Down1_Tx_Data_Swap Down2_Tx_Data_Swap Down_Rec_Data_Swap Set to 0 11

12 Pattern Rate (Downstream) The pattern generator can generate 1Gbps or 3Gbps patterns. The pattern checker can check 1Gbps, 3Gbps or 500Mbps patterns. The pattern rate is defined by the Rx downbw. The Tx downbw is ignored. The APIX mode is set individually for each receiver and transmitter. Rx APIXmode 0x3A RW apix_mode 0= APIX1 mode 1= APIX2 mode Tx APIXmode 0x3A0* RW apix_mode 0= APIX1 mode 1= APIX2 mode Rx APIX12_cfg_0 0x3A00011C 9:8 RW downbw 0= unused 1= 500Mbps 2= 1Gbps 3= 3Gbps (APIX2 mode only) Also used for Tx Tx APIX12_cfg_0 0x3A0*0044 1:0 RW downbw Not used downbw is copied from Rx * = 1,2,3 for Tx0,1,2 Pattern Checker (Downstream) The pattern checker monitors the received data for a given period. Bist_SWreset 0x3A W1P Bist_SWRes Write 1 to restart* BistTestDuration 0x3A :0 RW Bist_Test_Duration Length of test 31 = infinite LockingTime 0x3A00080C 11:0 RW LockingTime Max clocks to wait for a lock set to FFF (default) BistTrigger 0x3A W1P Trigger_start Trigger_stop Fault_value_reset Write 1 to start test Write 1 to stop test Write 1 to clear test DownLinkRxStatus 0x3A :8 R Down_Lock Down_Lock_Error Down_Done Down_Data_Error Down_Data_Error_Counter 1 =good 0 =good 1= good 0= good 0= good DownFaultValue 0x3A :0 R Fault_value Current and previous 31:16 Previous_value raw data. These freeze at first error. 12

13 Pattern Type (Upstream) The upstream pattern generator uses a subset of the controls for the downstream generator. Tx UpTxControl 0x3A RW Up_tx_prbs_mode 0= 1= fix 32-bit Pattern Rx Up*Control 0x3A x3A00083C 0x3A RW Up*_prbs_mode 0= 1= fix 32-bit Pattern BistStartValue 0x3A00081C 31:0 RW Bist_Start_Value fix 32-bit Pattern * = 1,2,3 for Tx0,1,2 Pattern Rate (Upstream) Rx APIXmode 0x3A RW apix_mode 0= APIX1 mode 1= APIX2 mode Tx APIXmode 0x3A0* RW apix_mode 0= APIX1 mode 1= APIX2 mode BistMode 0x3A :17 RW Up_Tx_BW 0= (APIX2): 187.5Mbit/s 22:21 RW Up0_rec_BW 1= (APIX1): 62.5Mbit/s 2= (APIX2): 62.5Mbit/s 26:25 RW Up1_rec_BW 3= (APIX1): Mbit/s * = 1,2,3 for Tx0,1,2 30:29 RW Up2_rec_BW 13

14 Pattern Checker (Upstream) Each upstream receiver includes a pattern checker. Control is partially shared with the downstream checker. Up*Control 0x3A x3A00083C 0x3A RW Up*_prbs_mode 0= 1= fix 32-bit Pattern 8 RW Up*_edge_detect_mode 0 = adjust on every edge 1 = adjust on first edge only 3:0 RW Up*_sample_offset Offset from edge to sampling point (default = 1) Up*LinkStatus 0x3A x3A x3A :8 R Up*_Lock Up*_Lock_Error Up*_Done Up*_Data_Error Up*_Data_Error_Counter 1 =good 0 =good 1= good 0= good 0= good Bist_SWreset See downstream checker BistTestDuration LockingTime BistTrigger * = 1,2,3 for Tx0,1,2 14

15 4. Standard Patterns The following patterns are generated by the Agilent 81134A pattern generator. Some patterns are also recognized by name by the LeCroy SDA808 oscilloscope. Order Length Bist_Polynomial Polynomial LeCroy Comment 5 31 bits 0x B X5 + X4 + X2 + X bits 0x X6 + X5 + X3 + X2 + 1 ITU-T V bits 0x X7+X bits 0x000000c6 X8+X7+X3+X bits 0x X9+X5+1 9 CCITT ITU-T V bits 0x X10+X CCITT0.152 ITU-T Inova bits 0x X11+X bits 0x X12+X9+X8+X bits 0x00001b00 X13+X12+X10+X bits 0x x14 + x13 + x11 + x bits 0x X15 + X Lists of prime polynomials are readily available in internet Further useful polynomials CCITT ITU-T Order Length Bist_Polynomial Polynomial Comment bits 0x000000b8 X8+X6+X5+X4+1 Inova bits 0x X10+X7+1 Inova bits 0x X12 + X6 + X4 + X1 + 1 Inova x0000d008 X16 + X15 + X13 + X4 + 1 Inova 16 bits - 16 bits 0x bit fixed pattern Pattern set by register - 15 bits 0x bit fixed pattern BistStartValue - 12 bits 0x bit fixed pattern 15