T3 Framer MegaCore Function (T3FRM)

Transcription

1 MegaCore Function August 2001; ver Data Sheet Features Achieving optimum performance in the Altera APEX TM 20K device architecture, the multi-featured MegaCore Function meets your innovative design needs, and provides fast time-to-market release for increased productivity. The T3FRM features include: Extraction and formatting of data for T3 line; Support of nominal T3 data rates of megabits per second (Mbps); Five interfaces provide connections to other devices, including a serial connection to a T3 mapper; The T3FRM complies with all applicable standards, including: Telcordia, Transport Systems Generic Requirements (TSGR): Common Requirements GR-499-CORE, Issue 2, December 1998 American National Standards Institute, Digital Hierarchy-Formats Specifications T Altera Corporation, Atlantic TM Functional Specification Easy-to-use MegaWizard Plug-In customizes your MegaCore function. Quartus II software and OpenCore feature allow placeand-route, and static timing analysis of designs prior to licensing; Secure register transfer level (RTL) simulation models allow simulation of the user design in third-party simulators. Generating Variants Table 1 shows the optional features available to generate all variants. Table 1. Optional Features Note (1) Options Parameters Choices LEs ESBs Basic Configuration 1,301 0 HDLC Controller Transmit and receive HDLC controllers with data FIFO buffer to process overhead bit HDLC channel HDLC Y/N Note: (1) The logic element (LE) and embedded system block (ESB) numbers are approximate as of August, Users are strongly advised to run the MegaWizard Plug-In and the Quartus II software to see exact numbers for each T3FRM. 1 Altera Corporation A-DS-IPT3FRM-1.02

2 Typical Applications Figure 1 shows the T3FRM connecting to different Altera MegaCore functions.these three examples show the T3FRM acting as a Midbus master. See s & Protocols on page 4 for more information about the Midbus interface. Figure 1. T3FRM as a Midbus Master Midbus Atlantic Cell Processor (CP155) ATM (1) Midbus Atlantic PLCP (2) Mapper Cell Processor (CP155) ATM Atlantic Packet Processor (PP155) Packet Data Notes (1) ATM Asynchronous Transfer Mode (2) PLCP Physical Layer Conversion Protocol Figure 2 illustrates the T3FRM acting as a interface slave.the T3 Mapper MegaCore Function (T3MAP), and SONET STS-1 Framer MegaCore Function (STS1FRM) are also shown. Figure 2. T3FRM as Line Slave Midbus T3 Mapper Line Circuit SONET STS-1 Framer (STS1FRM) T3 Mapper (T3MAP) Altera Corporation 2

3 Functional Description The T3FRM supports unchannelized digital signal level 3 (DS3) applications with C-bit parity functions and specialized multiplex 23 (M23) applications. It comprises two sub-blocks, the receive framer (RXFRMR), and the transmit framer (TXFRMR), illustrated in Figure 3. The following list of functions is based on a full-feature T3FRM. RXFRMR Sends payload data to various blocks Provides frame synchronization for: Unchannelized C-bit parity applications Specialized unchannelized M23 applications Bipolar Three Zero Substitution (B3ZS) Decoding Provides high-level data link control (HDLC) to terminate the path maintenance data link and accumulate data in a first in first out (FIFO) buffer Processes HDLC and link access protocol D (LAPD) frames Provides alarm detection Monitors performance using interval counters to accumulate: line code violations (LCV), far end block error (FEBE) events, alarm indication signals (AIS), loss of signal (LOS), excessive zeroes (EXZ), P-bit parity errors, C-bit parity errors, out of frame (OOF) errors Detects far end alarm and control (FEAC) codes Extracts overhead bits to a serial hardware interface Detects pseudo random bit sequence (PRBS) TXFRMR Receives payload data from various blocks Constructs frame for: Unchannelized C-bit parity applications Specialized unchannelized M23 applications B3ZS Encoding Provides HDLC to insert data to the path maintenance data link channel with a data FIFO buffer Generates HDLC and LAPD frames Inserts FEAC code Inserts overhead bits from a serial hardware interface Provides diagnostic insertion of alarm and error signals Generates PRBS Provides software control of C-bits 1 While T3FRM provides transparent transmission of M23 frames, it does not handle digital signal level 2 (DS2) multiplexing, or bit stuffing. 3 Altera Corporation

4 s & Protocols Five interfaces, illustrated in Figure 3, support the T3FRM. Midbus The Midbus is a simple synchronous full-duplex data path bus. The T3FRM Midbus runs at MHz over a single byte lane in each direction. In the receive (RX) direction, data is transferred from the Midbus master, RXFRMR, to the slave. In the transmit (TX) direction, data is transferred from the slave to the master, TXFRMR. In each direction, the Midbus can carry eight bits per clock cycle. It includes Midbus receive data (mrxdat[7:0]) and Midbus receive enable (mrxena) lines to indicate valid data transfers in the receive direction, and Midbus transmit data (mtxdat[7:0]) and Midbus transmit enable (mtxena) lines to indicate valid data requests in the transmit direction. AIRbus Using a simple synchronous internal processor bus protocol, the AIRbus provides access to internal registers. This protocol consists of separate read (rdata) and write (wdata) data buses, a data transfer acknowledge (dtack) signal, and a select (sel) signal. An address bus (addr[6:1]) and read (read) signal indicate the location and type of access within the block. The rdata buses and dtack signals can be merged from multiple blocks using a simple OR function. The dtack signal is sustained until the block sel is removed (four-way handshaking) meaning the AIRbus can cross clock domain boundaries. The T3FRM is an AIRbus slave with a data width of 16 bits. T3 Mapper The T3 Mapper interface offers an optional serial connection to a T3 mapper. The DS3 bit stream, including the overhead bits, is mapped into the SONET STS-1 synchronous payload envelope (SPE), asynchronously. The interface sends and receives DS3 signals at a data rate of Mbps and acts as a T3FRM master. This interface provides a connection to a transceiver. In the transmit direction it converts encoded digital signals into pulses for transmission over cable, and vice versa in the receive direction. The T3FRM is a interface slave. Altera Corporation 4

5 T3 Overhead As a serial hardware interface, the T3 Overhead interface, provides proper clocking and framing of the overhead bit stream for the insertion and extraction of overhead bits. Figure 3 illustrates the T3FRM divided into RXFRMR and TXFRMR, including the five interfaces. Figure 3. Block Diagram rxreset_n rclk rpdata rndata (2) lcv (2) alos RXFRMR rxsclk rxbit rohclk rohfp roh mrxclk mrxena mrxffp mrxefp mrxfoh mrxval mrxdat[7:0] T3 Mapper T3 Overhead Midbus RCLK DOMAIN txreset_n clk44 CLK44 DOMAIN read sel wdata[15:0] addr[6:1] rdata[15:0] dtack irq AIRbus (1) tclk tpdata tndata (3) tfp (3) TXFRMR mtxclk mtxena mtxffp mtxefp mtxfoh mtxval mtxdat[7:0] Midbus tohclk tohfp toh tohins txsclk txbit T3 Overhead T3 Mapper Notes: (1) The AIRbus interface provides access to internal registers for the entire block. (2) lcv and rndata are one pin. (3) tfp and tndata are one pin. 5 Altera Corporation

6 I/O Signals The following is a list of input/output signals, for the T3FRM. The signal direction is indicated by (I) for input and (O) for output. RCLK Domain: Signals: rclk (I), rpdata (I), rndata or lcv (I); T3 Mapper Signals: rxsclk (O), rxbit (O); T3 Overhead Signals: rohclk (O), rohfp (O), roh (O): Midbus Signals: mrxffp (O), mrxefp (O), mrxfoh (O), mrxdat[7:0] (O), mrxclk (O), mrxval (O), mrxena (O). CLK44 Domain: clk44 (I), Signals: tclk (O), tpdata (O), tndata or tfp (O); T3 Mapper Signals: txsclk (O), txbit (I); T3 Overhead Signals: tohclk (O), tohfp (O), toh (I), tohins (I); Midbus Signals: mtxffp (O), mtxefp (O), mtxfoh (O), mtxdat[7:0] (I), mtxclk (O), mtxval (O), mtxena (O). AIRbus Signals: read (I), sel (I), wdata[15:0] (I), addr[6:1] (I), rdata [15:0] (O), dtack (O), irq (O). Maintenance Signals: rxreset_n (I), txreset_n (I). Test Signal: alos (I). Performance Table 2 shows the required speed and estimated gate count of the T3FRM in an APEX 20K device. Table 2. Performance Note (1) LEs ESBs f MAX (MHz) 1,301 1, is required Note: (1) All LE and ESB numbers are approximate as of August They reflect the range from the basic to full feature variant. Licensing A license is not required to perform the following trial operations using your own custom logic: Instantiation Place-and-route Static timing analysis Simulation on third-party simulator Only when you are ready to generate programming files, do you need to obtain a license through your local Altera sales representative. 1 All current variants use a single license with ordering code: PLSM-T3FRM. Altera Corporation 6

7 Deliverables The following elements are provided with the T3FRM package: Data sheet User guide Midbus and AIRbus interface functional specifications MegaWizard Plug-In Encrypted gate level netlist Place-and-route constraints (where necessary) Secure RTL simulation model Demo testbench Access to problem reporting system 101 Innovation Drive San Jose, CA (408) Applications Hotline: (800) 800-EPLD Customer Marketing: (408) Literature Services: Copyright 2001 Altera Corporation. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. All rights reserved. 7 Altera Corporation