Helio X20: The First Tri-Gear Mobile SoC with CorePilot 3.0 Technology
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1 Helio X20: The First Tri-Gear Mobile SoC with CorePilot 3.0 Technology Tsung-Yao Lin, g-hsien Lee, Loda Chou, Clavin Peng, Jih-g Hsu, Jia-g Chen, John-CC Chen, Alex Chiou, Artis Chiu, David Lee, Carrie Huang, Kenny Lee, TzuHeng Wang, Wei-Ting Wang, Yenchi Lee, Chi-Hui Wang, Pao-Ching Tseng, Ryan Chen, Kevin Jou August 2016
2 Agenda Tri-Gear Concept Challenges Key Technologies Tailored CPU cores for gears Enhanced coherent interconnect Hybrid scheduler Holistic gear allocation Adaptive thermal management Achievements Summary
3 User Behavior Changed Source: Flurry Analytics Scenarios Example Application Task Load Time Spent% Per Day (2013) Time Spent% Per Day (2014) Time Spent% Per Day (2015) Changes ( ) Web Browsing Chrome Browser Gaming Temple Run 2 Social Messaging Heavy ~ Medium Heavy ~ Light 20% 14% 10% -4% 32% 32% 15% -17% Facebook Medium 24% 28% 31% +3% Entertainment, Utilities, and others YouTube, Mail Medium ~ Light 24% 26% 44% +18% Social messaging, entertainment, and utilities (with medium to light loads) take up to 75% of user time
4 Task Load Distribution of Scenarios Energy Consumption of Scenarios 100% 80% 60% 40% 20% 33% 38% 13% 48% 12% 28% 47% 36% 17% 42% Heavy Load Medium Load Light Load 0% Web Browsing Gaming Social Messaging Entertainment, Utilities & Others Idle Medium load tasks are important across all scenarios (36% ~ 48%) Heavy load tasks are still important for specific scenarios
5 The Dual-Gear Dilemma Light Tasks Medium Tasks Heavy Tasks big always-on, connected game multimedia
6 The Dual-Gear Dilemma Light Tasks Medium Tasks Heavy Tasks Execute medium load tasks on big wasted energy cannot meet performance requirement big always-on, connected Sustainable usage game multimedia
7 The Dual-Gear Dilemma Light Tasks Medium Tasks Heavy Tasks Execute medium load tasks on : balance between performance and power big always-on, connected Sustainable usage game multimedia
8 power Introduction to Tri-Gear High Performance 1 New gear introduced Sustainable Performance 2 gear goes for even lower power, gear aims for higher performance Low Power 3 Reduced power consumption across entire performance range 0 % 100 % 0 % 100 % performance
9 Info. Challenges of Tri-Gear Previous Evolving to Dual-Gear Tri-Gear Revised scheduler Tailored processors Enhanced coherent interconnect SW HW Scheduler Balance power and performance Light Task Heavy Task Thermal Management imize thermal performance Prevent overheating Power Management imize power consumption Right Task to Right CPU Control Info. big Coherent Interconnect Control Improved thermal sensing, power budgeting Improved gear management
10 Agenda Tri-Gear Concept Challenges Key Technologies Tailored CPU cores for gears Enhanced coherent interconnect Hybrid scheduler Holistic gear allocation Adaptive thermal management Achievements Summary
11 Energy Consumption Tailored CPU Cores for Three Gears gear for efficient performance +30% power-efficiency Multi-bit flip-flops optimization Delicate usage of high leakage LVT cells +40% performance vs. gear LIB and MEM optimizations, gears extend power/performance ranges A53 A53 A53 1.4GHz A53 A53 A53 A53 2.0GHz A53 A72 A72 2.5GHz 2.5X 2.0X 1.5X 1.0X +30% power-efficiency vs. +40% Performance vs. 0.5X 0X 1X 2X 3X Single-Thread Performance * Energy and Performance scale relative to the highest point of curve
12 Enhanced Coherent Interconnect Enhanced from 2 ACE ports to 3 ACE ports Increased logic extra power ~50% power reduction by sub-module Fine-Grain Clock Gating (FGCG) Coherent Interconnect Power Comparison big ACE ACE Coherent Interconnect Memory 0.3 common usage range -50% power * Power is relative to 2-gear at 1GB/s ACE ACE ACE Tri-Gear Coherent Interconnect Memory
13 Hybrid Scheduler HMP Dual-Gear scheduler Limited to Dual-Gear Boot CPU is always on and cannot be migrated (Fixed CPU0) Typically in cannot be off Dual-Gear scheduler Fixed CPU0 HMP (Heterogeneous Multi-Processing) SMP (Symmetric Multi-Processing) SMP C0 big C1 big big big Dual-level HMP scheduler for Tri-Gear? Might not be optimal Fixed CPU0 limits power saving opportunities Tri-Gear scheduler Fixed CPU0 SMP HMP? SMP HMP SMP C0 C1 Power-Off
14 CPU Power Intelligent Core Activation Technology (ICAT) ICAT assigns CPU0 dynamically gear can be off by task migration 8%~10% CPU power saved for medium load always online for CPU0(booted CPU) Fixed CPU0 C0 C1 2.5X Power/Tj curve 2.0X 1.5X 1.0X 2 threads w/o ICAT 2 threads with ICAT 1 thread w/o ICAT ICAT: can be offline Dynamic CPU0 C0 C1 0.5X Tj ( C) 1 thread with ICAT Power-Off * Power is relative to 1 thread with ICAT at 65 C
15 Asymmetric Multi-Processing (AMP) with ICAT AMP: enhanced HMP with dynamic gear operation for power saving Packing tasks to for sustainable performance HMP AMP task migration with ICAT Tri-Gear scheduler HMP AMP (Asymmetric Multi-Processing) SMP SMP SMP Packing tasks to for low power C0 C1 HMP AMP
16 power Hybrid Scheduler Instant boost technology HMP for high performance Instant boost technology Quick response to utilize for urgent or heavy tasks Inter-gear task migration Hybrid = SMP + AMP + HMP Inter-gear task migration Dynamic threshold control for energy efficiency and responsiveness Thread-group migration strategy to increase cluster (L2 cache) locality AMP HMP High Performance Sustainable Performance Low Power 0 % 100 % performance
17 Enhanced Power Management Previous Power Management Dynamic Voltage & Frequency Scaling (DVFS) and Hot-Plug drivers consider inputs separately: Power budget, performance requests, and system status such as load, Thread Level Parallelism (TLP) Big gear on/off controlled by Hot-Plug driver Status Thermal, Battery... Power Budget Requests CPU DVFS Heavy task, Scenario... Performance Requests CPU Hot-Plug Status Thermal, Battery... Heavy task, Scenario... Centralized Gear Allocation A holistic control to handle increased complexity Tracking steady states to avoid unnecessary gear migration overhead Linking to user-specified performance, normal, power-saving modes Status Power Budget Requests Centralized Gear Allocation Control CPU DVFS Performance Requests Control CPU Hot-Plug
18 Power Power Adaptive Thermal Management (ATM) Power budgeting by both core limit and frequency limit for all CPUs 2X Dual-Gear Dual-Gear to Tri-Gear More possible solutions from core / frequency combination meeting power target 1.5X ~ 3X more possible solutions on core combination alone, depending on TLP 1X 0X 0X 1X 2X 2-Thread Performance Tri-Gear 2X 1X 0X 0X 1X 2X 2-Thread Performance * Power and performance are relative to the highest point of curve * Each point in a curve represents a choice of gear / core / freq
19 Power Power ATM for More Combinations Previous power allocation Simple cost function: power efficiency only Large search space: chosen solution might not meet actual system requirement Precise power allocation Comprehensive cost function: power efficiency, system requirement (#core, frequency and power), system overhead +10% Performance from considering system requirement -5 C max Tj from reducing system overhead: hot-plug vs. DVFS latency 3X 2X 1X 0X 0X 1X 2X 3X 4X 5X 3X 2X 1X Previous Power Allocation Large search space Power budget Multi-Thread Performance Precise Power Allocation Reduced search space Power budget 0X 0X 1X 2X 3X 4X 5X Multi-Thread Performance * Power and performance are relative to the highest point of curve * Geekbench v3 Multi-core Performance 1 Heavy + 3 Light tasks Freq. limit Freq. limit
20 Agenda Tri-Gear Concept Challenges Key Technologies Tailored CPU cores for gears Enhanced coherent interconnect Hybrid scheduler Holistic gear allocation Adaptive thermal management Achievements Summary
21 Energy Consumption Energy Saving from Tri-Gear CPU Architecture Energy saving from Dual-Gear to Tri-Gear Up to -38% CPU energy measured for scenarios used daily 100% -35% -38% -38% -21% -12% 80% 60% Dual-Gear big 40% Dual-Gear 20% Tri-Gear Tri-Gear 0% Video Record+EIS (Utilities) Web Rollover (Web Browsing) Burst Photo (Utilities) Facebook (Social Messaging) Heavy Loading Game (Gaming) Tri-Gear
22 CorePilot Technology Evolvement SMP Symmetric Multi-Processing HMP Heterogeneous Multi-Processing HC Heterogeneous Computing Tri-Gear Hybrid Tri-Gear Multi-Processing C0 C1 C2 C3 C0 C1 C2 C3 C0 C1 C2 C3 C0 C1 C2 C3 C0 C1 C2 C3 C0 C1 C2 C3 C0 C1 C2 C3 C0 C1 big big GPU GPU MT6592 MT6595 Helio P10 Helio X20 CorePilot 1.0 CorePilot 2.0 CorePilot 3.0 Octa-core with SMP big. HMP Global Task Scheduling CPU+GPU Computing Dynamic Gear Migration for low power Tri-Gear CPU Architecture 12% ~ 38% CPU energy saving
23 power power Summary Majority of tasks are medium and light loads Added gear and enhanced gear CorePilot 3.0 Key Technologies Tailored CPU cores for gears Enhanced coherent interconnect Hybrid scheduler Holistic gear allocation Adaptive thermal management Benefit of Tri-Gear Up to 38% CPU energy saving for typical scenarios used daily over extended performance range 0 % 100 % performance
24 Copyright MediaTek Inc. All rights reserved.
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