Gigascale Integration Design Challenges & Opportunities. Shekhar Borkar Circuit Research, Intel Labs October 24, 2004

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1 Gigascale Integration Design Challenges & Opportunities Shekhar Borkar Circuit Research, Intel Labs October 24, 2004

2 Outline CMOS technology challenges Technology, circuit and μarchitecture solutions Integration opportunities Summary 2

3 Goal: TIPS by MIPS Pentium 4 Architecture Pentium Pro Architecture Pentium Architecture How do you get there? 3

4 CMOS Technology Scaling GATE SOURCE Xj GATE DRAIN SOURCE DRAIN D Tox BODY BODY Leff Dimensions scale down by 30% Oxide thickness scales down Vdd & Vt scaling Doubles transistor density Faster transistor, higher performance Lower active power Technology has scaled well, will it in the future? 4

5 Is Transistor a Good Switch? I = 0 I 0 On I = I = ma/u I = 0 I 0 Off I = 0 I 0 Sub-threshold Leakage 5

6 Sub-threshold Leakage MOS Transistor Characteristics Ids (log) ΔVt Exponential Increase in Ioff Vgs Ioff (na/u) Temp (C) SD Leakage (Watts) X Tr Growth.5X Tr Growth 0.25u 0.8u 0.3u 90nm 65nm 45nm Transistors will not be switches,, but dimmers Dennis Buss, TI Technology 6

7 Gate Oxide is Near Limit 90nm MOS Transistor 50nm Gate Leakage (Watts).E+06.E+05.E+04.E+03.E+02.E+0.E+00.E-0.E-02.E-03.5X 2X During Burn-in.4X Vdd 0.25u 0.8u 0.3u 90nm 65nm 45nm Technology Gate.2 nm SiO 2 Silicon substrate High K & Metal Gate crucial for the industry 7

8 Leakage Power Leakage Power (% of Total) 50% 40% 30% 20% 0% 0% Technology (μ) Must stop at 50% A. Grove, IEDM 2002 Leakage power limits Vt scaling 8

9 Sources of Variations Mean Number of Dopant Atoms Technology Node (nm) Random Dopant Fluctuations micron nm 80nm 30nm 248nm 90nm 65nm Generation 45nm 32nm Lithography Wavelength 93nm Gap 3nm EUV nm 00 0 Source: Mark Bohr, Intel Sub-wavelength Lithography Heat Flux (W/cm 2 ) Results in Vcc variation Heat Flux (W/cm2) Temperature (C) Temperature Variation ( C) Hot spots 9

10 Impact of Variations Normalized Frequency % 20X Normalized Leakage (Isb) 0.8 micron ~000 samples Low Freq Low Isb High Freq Medium Isb High Freq High Isb 0

11 The Power Envelope Power (W), Power Density (W/cm 2 ) mm Die SiO2 Lkg SD Lkg Active 8 MB 4 MB MB 2 MB 90nm 65nm 45nm 32nm 22nm 6nm Technology, Circuits, and Architecture to constrain the power

12 The Gigascale Dilemma Huge transistor integration capacity But unusable due to power Logic T growth will have to slow down Transistor performance will be limited Solutions Low power design techniques Improve design efficiency Multi everywhere Valued performance by even higher integration (of potentially slower transistors) 2

13 New Transistors: Tri-Gate Gate Tri-gate Gate 3 Drain Gate L g W Si Source Drain Gate Source T Si Gate 2 Source: Intel Improved short-channel effects Higher ON current for lower SD Leakage Manufacturing control: research underway 3

14 Active Power Reduction Low Supply Voltage Slow Fast Slow High Supply Voltage Multiple Supply Voltages Vdd Logic Block Replicated Designs Freq = Vdd = Throughput = Power = Area = Pwr Den = Vdd/2 Logic Block Logic Block Freq = 0.5 Vdd = 0.5 Throughput = Power = 0.25 Area = 2 Pwr Den =

15 Leakage Control Body Bias Stack Effect Sleep Transistor Vdd +Ve Vbp Equal Loading Logic Block -Ve Vbn 2-0X Reduction 5-0X Reduction 2-000X Reduction 5

16 Variation-tolerant tolerant Design small large Transistor size power target frequency probability Balance power & frequency with variation tolerance low high Low-Vt usage 0.5 frequency large small Logic depth target frequency probability 0 less more # uarch critical paths 6

17 Design & μarch Efficiency Growth (X) from previous uarch Same Process Technology Die Area Performance Power Reduction in MIPS/Watt 40% 20% Same Process Technology Enegry efficiency drops ~20% 0 S-Scalar Dynamic Deep Pipeline 0% S-Scalar Dynamic Deep Pipeline Employ efficient design & μarchitectures 7

18 Memory Latency 000 CPU Small ~few Clocks Cache Memory Large 50-00ns Memory Latency (Clocks) 00 0 Assume: 50ns Memory latency Freq (MHz) Cache miss hurts performance Worse at higher frequency 8

19 Increase on-die Memory 00 Power Density (Watts/cm 2 ) 0 Logic Memory Cache % of Total Area 00% 75% 50% 25% 0% Pentium M Pentium III 486 Pentium Pentium 4 u 0.5u 0.25u 0.3u 65nm 0.25μ 0.8μ 0.3μ 0.μ Large on die memory provides:. Increased Data Bandwidth & Reduced Latency 2. Hence, higher performance for much lower power 9

20 Multi-threading threading 00% Thermals & Power Delivery designed for full HW utilization Performance 80% 60% 40% GHz 2 GHz ST Single Thread Full HW Utilization Wait for Mem Multi-Threading 20% 0% 3 GHz 00% 98% 96% MT Wait for Mem MT2 Wait MT3 Cache Hit % Multi-threading threading improves performance without impacting thermals & power delivery 20

21 Chip Multi-Processing C C3 Cache C2 C4 Relative Performance Multi Core Single Core Die Area, Power Multi-core, each core Multi-threaded Shared cache and front side bus Each core has different Vdd & Freq Core hopping to spread hot spots Lower junction temperature 2

22 Special Purpose Hardware TCP Offload Engine.E+06 PLL OOO ROB Send buffer MIPS.E+05.E+04 GP TCB Exec Core TCB Exec Core ROM ROM Input seq CAM CLB.E+03.E+02 TOE mm X 3.54 mm, 260K transistors Opportunities: Network processing engines MPEG Encode/Decode engines Speech engines Special purpose HW Best Mips/Watt 22

23 Valued Performance: SOC (System on a Chip) Special-purpose purpose hardware more MIPS/mm² SIMD integer and FP instructions in several ISAs General Purpose Multimedia Kernels Si Monolithic Special HW Wireline CMOS RF Die Area 2X <0% Polylithic Power 2X <0% Performance ~.4X.5-4X Heterogeneous Si, SiGe, GaAs Opto- Electronics CPU Memory RF Dense Memory 23

24 Roadmap to TIPS MIPS Speculative, OOO Super Scalar Era of Pipelined Architecture Multi-Threaded, Multi-Core Multi Threaded Era of Instruction Level Parallelism Era of Thread & Processor Level Parallelism Special Purpose HW Multi-everywhere: MT, CMP 24

25 Summary Business as usual is not an option Performance at any cost is history Move away from frequency alone to deliver performance Future μarchitectures and designs More memory (larger caches) Multi-threading threading Multi-processing Special purpose hardware Valued performance with higher integration 25