Parag Choudhary Engineering Architect
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1
2 Parag Choudhary Engineering Architect
3 Agenda Overview of Design Trends & Designer Challenges PCB Virtual Prototyping in PSpice Simulator extensions for Models and Abstraction levels Examples of a coding algorithm models into PSpice PCB Level cycle accurate mixed signal simulation
4 System integration trends Design Trends Electronic systems trending to large devices for lower power, higher reliability, and increased functionality in smaller package Software controlled Digital Content with Analog circuitry all in one Electronic Package are the new Mixed Signal devices Handhelds, wearable(s) and Internet of Things boosting growth of Embedded Systems
5 Design Development Challenges Discrete Devices Basic Integration Mixed-Signal Technologies Mixed-Signal Electro- Mechanical SoC Integration Package Integration Embedded Software controlled Mixed Signal Device require solutions where S/W algorithms can be tested together with H/W SPICE Models Mixed-Signal Models System Models Higher abstraction and lower accuracy and lower simulation time In PCB systems simulation for large ICs HDL-level IC models are prohibitively slow for the new emerging class of devices
6 PCB Virtual prototyping Requirements Package Integration SoC Integration Mixed-Signal Electro- Mechanical Mixed-Signal Technologies System macromodel (System model embedded in mixed-signal model) Mixed-signal SPICE and gate-level simulation (Small D- Big A) Model Abstractions Architectural Functional Behavioral Gate Level Integrated C/C++ & Spice language based solution to model large mixed signal electronic devices at any abstraction level and achieve desired accuracy at PCB level simulation while supporting existing PCB analysis flows Cadence, the Cadence logo, and PSpice are registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners. Basic Integration Discrete Devices Physical SPICE parametric extraction and curve fitting Circuit Level Physical Implementation
7 PSpice virtual prototyping PCB systems Integrated C/C++ & Spice language based solution to model large mixed signal electronic devices at any abstraction level and achieve desired accuracy at PCB level simulation while supporting existing PCB analysis flows Package Integration SoC Integration Mixed-Signal Electro- Mechanical Mixed-Signal Technologies Basic Integration Discrete Devices System macro-model (System model embedded in mixed-signal model) Mixed-signal SPICE and gate-level simulation (Small D- Big A) Physical SPICE parametric extraction and curve fitting Model Abstractions Architectural Functional Behavioral Gate Level Circuit Level Physical Implementation Cadence, the Cadence logo, PSpice are registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners. PSpice Model PSpice System Macro Model with SystemC-TLM PSpice System Macro Model with SystemC, C, C++, PSpice Digital PSpice System Macro Model with SystemC, C/C++, PSpice Mixed Signal PSpice Mixed-Signal Macro Model with C/C++, PSpice Mixed Signal Devices PSpice Macro Model with SPICE, Analog-C/C++/SystemC-AMS PSpice Macro Model with SPICE, Analog-C/C++/SystemC-AMS with Physical Parasitic
8 PSpice mixed-signal simulator Digital Event Solver 6 logic levels (Z level is strength) Analog Matrix Solver Pin I/O Models IN 0 IN 1 IN 2 Behavioral Logic (Functional Model) OUT 0 OUT 1 OUT 2 D/A & D/A Convertors [G][V]=[I] Pin to Pin Timing Model Constraint Model Cadence, the Cadence logo, and PSpice are registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.
9 Cadence, the Cadence logo, and PSpice are registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners. PSpice mixed-signal device models D/A & D/A Convertors A/D (O device) Behavioral primitives Bidirectional transfer gates D/A (N device) Delay line GaAsFET Capacitor Diode VCVS and Flux Source CCVS File stimulus Pullup and pulldown Flip-flops and latches Random access read-write memory Input/output model Read-only memory Multi-bit A/D and D/A converters Standard gates Programmable logic array Stimulus generator VCCS and Charge Source CCCS Independent Current source JFET Mutual Coupling Inductor Mosfet D/A A/D IGBT Bipolar transistor Resistor Voltage- Controlled switch Transmission lines Independent Voltage Source Tristate gates Current Controlled Switch Generic C/C++ Model
10 PSpice mixed-signal macro model with C/C++/SystemC extensions D/A and D/A Convertors Integrated C/C++ & Spice language based solution to model large mixed signal electronic devices at any abstraction level and achieve desired accuracy at PCB level simulation C/C++ Digital Model SystemC Model A/D (O device) Delay line Multi-bit A/D and D/A converters Read-only memory Behavioral primitives File stimulus Programmable logic array Standard gates Bidirectional transfer gates Flip-flops and latches Pullup and pulldown Stimulus generator Cadence, the Cadence logo, and PSpice are registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners. D/A (N device) Input/output model Random access read-write memory Tristate gates VerilogA-ADMS Configuration C/C++ Behavioral Model Device Compact Models GaAsFET Capacitor Diode CCVS JFET VCCS and Charge Source Mutual Coupling CCCS Inductor D/A A/D IGBT Resistor Voltage- Controlled switch Current Controlled Switch Transmission lines Generic C/C++ Model VCVS and Flux Source Independent Current source Mosfet Bipolar transistor Independent Voltage Source
11 PSpice Event solver Acceleration with Accuracy for PCB Simulation IN 0 IN 1 IN 2 Pin I/O Models System Model Abstraction OUT 0 OUT 1 OUT 2 Pin to Pin Timing Model Constraint Model Temporal Data Accuracy Timing and I/O models at Interface Simulation Acceleration with System-Level Abstractions Functionality Structural
12 IN Power Stage Example - S/W Algorithm Controlled PWM in Power Supply Filter Stage OUT Develop and test MCU targeted algorithms in PSpice models PWM Microcontroller with S/W control A/D PWM Control C/C++ Digital Model SystemC Model
13 Example: C/C++ Digital Model in PSpice Detect clock edge Read Input signal bits Convert Signal Bits to C/C++ variables Execute Algorithm Convert C/C++ variables to Signal bits and post to output
14 Example: SystemC Model in PSpice Read input signals Create SystemC variables for input Signals Write to SystemC block Evaluate SystemC Block Read SystemC Block output Write to output signal bits
15 PSpice accelerated mixed-signal system model for large IC on PCB with mixed-signal accuracy at interface Physical device compact model SystemC model supporting embedded S/W and different abstraction levels Analog behavioral Digital C/C++ with embedded SW block Temporal Functionality Data Accuracy Simulation Acceleration with System-Level Abstractions Structural Cadence, the Cadence logo, and PSpice are registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.
16 Specify Model I/O, Timing and Constraints inside Model core behavior in System Model Function al Logic PSpice digital block allows user to specify functional logic, I/O, timing and constraints at a block level (PCB solutions need to work from datasheet) I/O model, timing information and constraints can be captured directly from datasheet or PSpice re-usable model specification directly input as specs from IC datasheets Constraint Specificati on PSpice Digital Block Timing Specificati on I/O Drive Specs PSpice system modeling extensions allows functional logic to be simple C/C++ or can be sophisticated models from SystemC The PSpice C/C++ digital block API allow specification of timing and I/O also enabling more complex models instead of always using block-level specification
17 Algorithmic Block Simulation in Matlab- Simulink Using Matlab/Simulink blocks using PSpice Device Modeling (DMI) API MATLAB Model Block Implementation & Simulation in PSpice Mixed-level Cosimulation in Matlab- Simulink & PSpice Mixed-level Simulation in PSpice Design Algorithmic module in Matlab/Simulink Use PSpice Adapter to embed code inside PSpice behavioral block Use MATLAB/Simulink Coder to Generate C Code Compile code in Microsoft Visual Studio IDE to generate PSpice- DMI compatible dll Associate Macro-model to Schematic on OrCAD Capture Canvas Run PSpice simulation and verify results Algorithmic Abstraction Implementation
18 Using Device modeling API with MathWorks Algorithms Algorithmic Block Simulation in Matlab-Simulink MATLAB Model Block Implementation & Simulation in PSpice Mixed-level Cosimulation in Matlab- Simulink & PSpice Mixed-level Simulation in PSpice Algorithmic Abstraction Implementation
19 Algorithm Transfer to PSpice Circuit Model Matlab PSpice
20 PSpice virtual prototyping PCB systems Single Simulation environment with embedded software and Electronic devices models at multiple abstraction levels PSpice SPICE Macro-Model PSpice Analog Behavioral PSpice Functional Block Defined in C Cadence, the Cadence logo, Virtuoso, MMSIM and PSpice are registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.
21 Simulink & PSpice co-simulation Instantiate and co-simulate PSpice Design Block in Simulink Filter
22 Chip-Package-Board PSpice PCB Block in Simulink PSpice System Design Implementation across multiple design fabrics Simulink Coder to PSpice Block Miniaturizationiterative block implementation with system design exploration to implementation PSpice PCB Implementation
23 PCB system model in Cadence Chip- Package-Board solution Virtuoso Technology Specctre PSpice Netlist Support MMSIM 14.1 Dec Allegro PCB Technology Sigrity Technology Improved model quality for increased model complexity Virtuoso System In Package Technology PSpice SystemC, C/C++ Support 16.6 QIR Verilog-ADMS July 2015 OrCAD Technology
24 MMSIM with Spectre & PSpice Goal MMSIM simulations enabled with sub-blocks defined in PSpice format Allows designer to include PCB components in Spectre simulations Use model Spectre netlist: pspice_include <file> Spice netlist:.pspice_include <file> All file content inside <file> and any included file are required to be in PSpice format No supported PSpice only designs Spectre PSpice control statements Spectre Top Level Spectre Sub-block Spectre PSpice Sub-block PSpice
25 MMSIM PSpice features Features pspice_include reads the PSpice format netlist Models included in PSpice netlist simulated using the PSpice default values and equations All basic analog devices are supported Basic device types Independent and dependent sources Subckt and model definition Parameter and function definitions Transmission lines Analog behavioral modeling Note Digital devices are not supported with Spectre simulation. Basic gates may be built using analog behavioral elements. Virtuoso Analog Design Environment support available in IC616 ISR4/MMSIM13.1 ISR1
26 PSpice Systems Modeling System Design with Embedded S/W Authoring with PSpice System Design Macro Model Mixed-Signal Simulation with Embedded System Models PSpice-Simulink (SLPS) OrCAD PSpice Mixed Signal PSpice Advanced Analysis To System Implementation PSpice Behavioral and Compact Device Modeling with VerilogA and C/C++ Circuit Reliability Analysis SI/PDN Analysis (Sigrity Technology with PSpice) Multi-Domain Modeling and Simulation Open Application Programming Interface (API) World s Leading Schematic Authoring Technology Co-Simulation with Implementation Interface to postprocessing and reports Reliability Analysis with customized algorithms
27 Summary PSpice system model extensions enable modeling of large mixed-signal ICs in PCB simulation enabling simulation of entire PCB PSpice analog C/C++ extensions with VerilogA-ADMS configurations enable modeling of: Analog behavioral blocks for multi-domain PCB simulation New technology device compact models into PSpice simulator PSpice-Virtuoso collaboration provide model and netlist portability between Virtuoso- Spectre environments and PSpice
28 Next Level Implementation details in Session on modeling Embedded Device
29 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, OrCAD, PSpice, Spectre, and Virtuoso are registered trademarks and Sigrity is a trademark of Cadence Design Systems, Inc, All other trademarks are the property of their respective owners.
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