Reducing MLC Flash Memory Retention Errors through Programming Initial Step Only

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1 Reducing MLC Flash Memory Retention Errors through Programming Initial Step Only Wei Wang Computational Science Research Center San Diego State University San Diego, CA 95 Tao Xie Computer Science Department San Diego State University San Diego, CA 95 Antoine Khoueir, Youngpil Kim Seagate Technology Shakopee, MN Abstract Retention error has been recognized as the most dominant error in MLC (multi-level cell) flash. In this paper, we propose a new approach called PISO (Programming Initial Step Only) to reduce its number. Unlike a normal programming operation, a PISO operation only carries out the first programmingand-verifying step on a programmed cell. As a result, a number of electrons are injected into the cell to compensate its charge loss over time without disturbing its existing data. Further, we build a model to understand the relationship between the number of PISOs and the number of reduced errors. Experimental results from y-nm MLC chips show that PISO can efficiently reduce the number of retention errors with a minimal overhead. On average, applying PISO operations each on a one-yearold MLC chip that has experienced 4K P/E cycles can reduce its retention errors by.5% after 3 s. I. INTRODUCTION NAND flash memory (hereafter, flash memory) has been extensively used in various computer systems because of its attractive features such as high I/O performance and low energy consumption [], []. To largely reduce NAND flash memory cost in dollars per GB, manufacturers are aggressively scaling down memory cell size and pushing each cell to store more bits [3]. However, these technologies substantially lower the reliability and endurance of flash memory. For example, a typical 7-nm technology SLC (single-level cell) flash can survive k P/E (programming/erase) cycles with a minimum -bit per KB ECC capacity (i.e., bit errors can be corrected per KB data), whereas a sub 5-nm technology -bit MLC flash can only tolerate no more than k P/E cycles with a minimum 8-bit per KB ECC capacity [3]. The decreasing reliability demands stronger ECC schemes whose capacity increasing rate may not be able to keep the same pace with the shrinking lithography [4]. Reducing bit errors, theore, becomes a critical way to improve the reliability of flash memory under a certain ECC capacity. A flash memory cell is a floating-gate MOS transistor [] (see Fig. a). The floating-gate of a cell stores a number of electrons, which affects the cell s threshold voltage. The value of is measured to determine the state of a cell [5]. A -bit MLC cell can store -bit data with four different states (i.e., S,S,S, and S 3, see Fig. b). In this paper, we only investigate -bit MLC flash. A programming operation is to charge a cell to a particular threshold voltage level, whereas an erase operation is to remove charges stored in each cell s /5/$3. c 5 IEEE Control gate Floating gate S D Substrate Distribution of cells Reference voltage S S S S Vth Fig. : A cell; (b) MLC threshold voltage distribution. floating-gate. If a cell s shifts across the boundary of its erence voltage(s), its data will be misinterpreted, and thus, an error happens [4]. A flash memory error could occur due to various noise sources like cell-to-cell interference, random telegraph noise, and data retention [6]. A retention error is caused by electron leakage and de-trapping phenomenon [7] over time, which shift the of a programmed cell to a lower level across its left erence voltage (see the four dotted curves in Fig. b). Retention error has been identified as the dominant flash memory error [8], [6]. Obviously, the number of retention errors enlarges as the retention time increases. To compensate a cell s charge loss over time, and thus, correct its retention error, an intuitive solution is to inject an appropriate amount of electrons into a cell so that its can be pushed back to its original level. Compared with a read operation, a programming operation provides a more effective means of charging a cell because it applies a higher voltage on the control gate [6]. A programming operation uses the ISPP (incremental step pulse programming) method to lift a cell s threshold voltage to an expected level [4]. Fig. illustrates how ISPP changes the threshold voltage of a cell. The expected is the threshold voltage, to which a cell is going to be programmed. ISPP consists of a series of programming-and-verifying steps. In each step, a programming voltage, V program, is first applied to raise a cell s threshold voltage by injecting a number of electrons. Next, a verifying process is carried out to compare the cell s current with the expected. If the current does not reach the expected, a subsequent programming-and-verifying step is executed to further increase the cell s. Otherwise, the programming process is terminated. V pp, the V program increase between two adjacent steps, affects programming speed for programming time can be shortened if it is increased [4]. MLC cell programming is complicated because the two bits (b)

2 V V start V verify ΔV pp V max inhibit Distributio n of cells EE E E represents erase state E Programming the LSB of -bit Expected Time of memory cell Fig. : Incremental step pulse programming (ISPP). Distributio n of cells Fig. 3: Programming an MLC cell. Programming the MSB of -bit of an MLC cell belong to two different pages, and thus, have to be programmed separately. The most significant bits (MSBs) of all cells in a block form MSB pages, whereas the least significant bits (LSBs) are grouped to LSB pages. Programming an LSB page is faster than programming an MSB page because the latter requires to first read its corresponding LSB page, and then, a smaller V pp is applied to accurately control the precision of the final threshold voltage level [4]. Fig. 3 shows an MLC cell programming procedure. For example, after programming to the LSB of an erased cell, its LSB (i.e., the left bit) becomes while its MSB (i.e., the right bit) remains in the erase state E. If we continue to program to the cell s MSB, the cell s current state (i.e., E ) will be first read out. And then a further threshold voltage increase will be added on top of it so that the threshold voltage of the cell reaches the final state. This is how the data is programmed into an MLC cell. After a cell is newly programmed, its must be within one of the four threshold voltage ranges (i.e., S, S, S, and S 3 in Fig. b). If we deliberately program the data corresponding to a safe threshold voltage (i.e., a voltage lower than the cell s current, see Section III-A) into the cell, based on the programming-and-verifying mechanism the programming operation will be immediately terminated after the first verifying process for the cell s is already higher than the expected. As a result, the data stored in the cell remains unchanged. This one step programming process, however, can correct retention errors as it injects some electrons into the cell. Inspired by this observation, we develop PISO (Programming Initial Step Only), a new approach to reducing retention errors. Its basic idea is to periodically program the data corresponding to a safe into a programmed cell. The injected electrons can partially compensate charge loss over time so that retention error can be mitigated. PISO incurs a minimum overhead as it can program a cell in-place without requiring prior knowledge of the data stored. Besides, it can be readily implemented in an SSD device driver or the firmware of an SSD controller. Major contributions of this paper include: () We propose a new approach called PISO that can correct retention errors with a low cost; () We build an analytical model to understand the relationship between the number of PISOs and the number of reduced retention errors; (3) We conduct experiments on modern y-nm MLC chips from two vendors; experimental results show that PISO lowers retention errors by.9% for a 4K-P/E-cycled flash memory chip after 3 retention baking; (4) We qualitatively compare PISO with existing schemes to illustrate its advantages and limitations. The remainder of the paper is organized as follows. Section II briefly summarizes the related work. Section III introduces the PISO approach. An analytical model derived from the threshold voltage distribution of flash memory is introduced in Section IV to calculate an appropriate number of PISO operations. Section V evaluates the effectiveness of the PISO approach and compares it with the read disturb. Section VI discusses how to apply PISO on real applications. The paper is concluded in Section VII. II. RELATED WORK A few retention error reduction schemes [8], [9], [], [] have been recently reported in the literature. A dynamic threshold scheme for flash memory was developed by Sala et al. to reduce retention errors [9]. After a shifts to its left, the scheme pushes erence voltages to the same direction so that the shifted can still be correctly interpreted. However, finding a suitable erence voltage change typically requires a series of read retry operations with different erence voltage settings, which incurs a high overhead [9]. Moreover, as the corrected data has to be written to a new place, the block with the original data will be reclaimed later, which consumes one P/E cycle, and thus, reduces its lifetime [9]. Ma et al. proposed a retention error correcting scheme called RE-WPD (Reliability Enhancing through Word-line Program Disturbance) []. Each RE-WPD operation writes xff sequentially on all least significant bit (LSB) pages in a selected block so that cells in the selected word line are all biased in the program inhibit status due to the xff data pattern. As a result, a small amount of electrons are injected into the cells floating gates because the high voltage between the control gate and the channel induces slightly FN (Fowler-Nordheim) tunneling []. The RE-WPD operation can be repeatedly applied multiple times in order to inject more elections for the data retention error recovery purpose. Unlike the approach presented in [], PISO directly utilizes the programming operation and can be applied on both MSB and LSB pages. Cai et al. proposed a flash correct-and-resh (FCR) technique, which periodically corrects retention errors by reading, correcting, and re-programming (in-place) [8]. To avoid the over-programmed problem, after a number of in-place programming operations it moves the data to a new page [8]. However, they found that the remapping-based FCR technique could negatively affect the performance of a read-intensive

3 TABLE I: The layout of an MLC block (56 pages x 6 KB). Row Index LSB of the 7 cells MSB of the 7 cells page page page page 4 page 3 page page 5 page 54 7 page 53 page 55 application due to the fact that it incurs considerable data movement and unnecessary reshes although the average flash memory lifetime can be significantly improved. To reduce the overhead of data movement caused by reprogramming, they further proposed hybrid FCR. The key idea is that a page can be reshed by reprogramming it in-place instead of by re-mapping it to another location. This is based on the insight that retention errors are caused by charge loss and cells with retention errors are re-programmable without first erasing them. To further reduce unnecessary reshes, they also proposed adaptive-rate FCR, which has a low resh rate for a flash block when its retention error rate is low (i.e., early in its lifetime) [8]. Nevertheless, dynamically monitoring the number of over-programmed errors and determining a good timing of a data migration degrade performance and reduce P/E cycles [8]. Tanakamaru et al. introduced an error reduction scheme by using read disturb effect in flash []. Their scheme is named DRRP (data-retention error-recovery pulse), which is applied to the memory cells. With DRRP, electrons are injected into the floating gate, and thus, DRRP mitigates the data-retention errors. Unfortunately, it has to perform hundreds of read operations (see Section V for details), which results in a high overhead. A low-cost yet effective retention error reduction approach is greatly needed. III. A. The Safe Threshold Voltage THE PISO APPROACH Table I shows the page layout of an MLC block, which consists of 8 rows of 7 cells. These cells are mapped to 56 pages with each of them being 6 KB. Page and page share the first row of 7 cells. To program page, an LSB page, the threshold voltage that represents data is the safe threshold voltage as it is the lowest among the two possible ranges (see LSB programming in Fig. 3). Because only one programming-and-verifying step is executed, programming data to an LSB page will not change its current data, and thus, it is safe. Programming page, an MSB page, demands a read operation of the cells current states. If a cell s is within E state (i.e., the cell s LSB is ), it can only be further programmed to either state (i.e., the cell s MSB is ) or state (i.e., the cell s MSB is ). Since the of state is lower than that of state, writing data to the MSB of the cell is equivalent to programming it to the safe threshold voltage. Similarly, if a cell s LSB stores, programming data to the cell s MSB equals to programming it to the safe threshold voltage (see MSB programming in Fig. 3). In other words, for an LSB page, data always represents the safe. For an MSB page, the data stored in its associated LSB page represent each individual cell s safe. V expected V verify V program of memory cell Time Δ Fig. 4: A PISO operation; (b) before; (c) after PISO. B. A PISO Operation PISO exploits the first programming-and-verifying step in a programming operation by programming the data corresponding to the safe. Fig. 4 illustrates a PISO operation and the threshold voltage change before and after applying it. Assuming that a cell is programmed to the state, after a certain period of retention time a retention error occurs as its threshold voltage shifts left into the range of state (see the dotted curve in Fig. 4b). Now, a PISO operation programs data (i.e., the safe ) to the cell s LSB. The expected (i.e., the safe ) is shown in Fig. 4a. The PISO operation will be immediately terminated after the first programmingand-verifying step because the cell s exceeds the expected. Consequently, the of the cell is pushed back to its original range (i.e., state), and thus, the retention error is corrected (see the dotted curve in Fig. 4c). C. PISO on LSB/MSB Pages MLC uses different programming procedures for the LSB and MSB of a cell. Hence, applying the PISO operation on an LSB page is different to that of on an MSB page. To correct a cell s retention error, a PISO operation can be applied on either an LSB page or its associated MSB page because they share the same memory cells. Applying a PISO operation on an LSB page can be simply carried out by programming data to the page. In contrast, applying a PISO operation on an MSB page is complicated as the data on its associated LSB page need to be first read out. And then, the data are programmed to the MSB page. Compared with an LSB page PISO operation, the overhead of performing an MSB page PISO operation is much higher because: () an MSB page PISO operation requires an extra page read operation; () programming an MSB page demands more clock cycles due to the internal programming mechanism (typically, programming an MSB page is 3 4 times slower than programming an LSB page [4]). Besides, the retention error correction capabilities of the two types of PISO operations are similar as both of them execute one programming-and-verifying step, which injects a close number of electrons. Based on the analysis above, an LSB page PISO operation is superior to an MSB page PISO operation. Thus, we only carry out LSB page PISO operations in all our experiments shown in Section V. (b) D. Preventing the Excessive Use of PISO Although a PISO operation can reduce retention errors, an excessive use of it may generate new errors. First of all, a (c)

4 Probability Probability μ μ μ μ 3 σ σ =σ =σ 3 S -3V.6V.8V 3V.48. σ V V V S S S 3 σ σ σ μ - - μ μ μ 3 4 Voltage (V) V Δ Δ Δ V Δ 3 Δ 4 V μ Voltage (V) μ μ 3 4 (c) Δ 5 Probability Probability ΔV L th V V V ΔV L th ΔV L th ΔV L th μ Voltage (V) μ μ 3 4 (b) Retention Errors V Over-programming Errors V V μ Voltage (V) μ μ 3 4 (d) Fig. 6: distributions; normal; (b) left shifted; (c) with inadequate number of PISOs; (d) over-programmed. errors errors Vth Electrons leakage in real applications. - (b) Injecting the same number of electrons. Fig. 5: Threshold voltage distribution shifts. programming operation may also introduc programming errors. Secondly, memory cells that are programmed to a higher threshold voltage (i.e., state and state ) incur more retention errors [6] (see Fig. 5). Cai et al. [6] show that 46% and 44% of total retention errors are state! state and state! state errors, respectively. This observation can be explained by the mechanisms of retention errors. The electron loss during retention can be attributed to two reasons: the first one is the stress induced leakage current (SILC) and the second one is the relaxation of interface traps [6]. As memory cells in higher threshold voltage states (e.g., state and state ) have a larger number of electrons, SILC is higher and theore more electrons leak away from these cells. The threshold voltage drift, theore, is more large in these cells. As shown in Fig. 5a, the decrease of threshold voltage level in memory cells with state is the largest, whereas the threshold voltage levels in memory cells with state do not have obvious shift. Thus, injecting the same amount of electrons into all memory cells cannot push the threshold voltage distributions back to their original positions. Even worse, the threshold voltage of cells in a lower state (i.e., or ) may be over-pushed, and thus, new errors are generated (see Fig. 5b). Thus, an appropriate number of PISO operations needs to be caully chosen. IV. AN ANALYTICAL MODEL In this section, we derive an analytical model to understand the relationship between the number PISOs and the number of reduced errors. The threshold voltage distribution of flash memory follows a sum of Gaussian distributions model [4]: f(x) = = 3X P (S)f s (x) s= 3X 4 p exp{ (x µ s) }, s s= s where P (S) is the probability of state S. Ideally, P (S) for each state is approximately equal to 4 in an MLC flash because there are a large amount of memory cells in one flash chip. µ s is the mean value of state S. The distribution model of a standard MLC flash is illustrated in Fig. 6a and all the parameters used are set according to [4]. It is obvious that the state S has a flattened bell shape while the distributions of other three states are much taller and tighter. V,V, and V are erence voltages used to differentiate the four different states. When a leaves its original range and crosses a erence voltage, an error happens (see Fig. 6b). It is clear that the cells that are at the tail of distribution incur errors when a threshold voltage changes. () A higher threshold voltage results in a higher SILC, which leads to a larger loss of electrons. As a result, Vth L (i.e., the left shift amount of a cell s ) is in direct proportion to its original. Also, it is well understood that a longer retention time results in more retention errors. Thus, Vth L for state S can be estimated as below: V L th,s = (t),s, ()

5 where,s is the original of a cell in state S and (t) is the retention time. The original distance between state S and state S 3 is (,3, ). After retention time (t), the threshold voltages of the four states all shift to left. Their shift amount can be calculated by equation (). Thus, the new distance between the state S and state S 3 can be derived as follows: (,3 Vth,3) L (, V L =( (t)) 3 ( (t)) =( (t))(,3, ). th,) Clearly, the charge loss shrinks the distance between,3 and,. Since the three erence voltages keep unchanged, applying PISO operations to push the four states back to their original positions has three possible consequences: () The number of PISO operations is insufficient. As shown in Fig. 6c, in this case the of state S could be pushed back to its correct range, whereas state S or S 3 could not because no enough electrons are injected; () The of a state is overpushed across its right boundary for too many PISO operations are carried out. Fig. 6d illustrates this situation. In this scenario, state S 3 is fully pushed to its initial range. However, cells whose are originally in state S and S are overcharged. Their pass the upper boundaries, which incurs over-programmed errors. (3) An appropriate number of PISO operations are carried out so that a maximum number of errors are reduced. We assume that each PISO operation can shift by Vth,S R (i.e., the right shift amount of a cell s in state S). After m PISO operations, the total threshold voltage right shift amount for a state S is m Vth,S R. Thus, the voltage distribution model shown in Equation () can be modified as below: 3X f(x) = 4 p exp{ [x + m,s R ( (t))µ s ] }. s s= s The tail probability function of each state is used to compute errors existing in this distribution model [4]. Hence, the error minimization problem can be expressed as follows: min[ 4 Q S ( )+ 4 Q S ( )+ 4 Q S ( ) + 4 Q S ( 3 )+ 4 Q S ( 4 )+ 4 Q S 3 ( 5 )], where s is the distance between the mean value of state S and a erence voltage (see Fig. 6). Q s (x) is the tail probability function of state S: Q s (x) = p Z exp( x 3 (3) (4) (5) t )dt. (6) For example, in state S, = V read m Vth,S R ( (t))µ. By solving this problem, we can obtain an optimal number of PISO operations m. In practice, the th,s and (t) of a flash memory chip vary from vender to vender. Hence, an optimal m for a particular flash memory can be empirically measured in a lab by a manufacturer, and then, can be provided to users. V R Group A B C D E F TABLE II: Parameters of the two flash chips. Flash A Flash B Page size 6 KB 6 KB Pages per block 5 56 Blocks per plane,48,48 Plane per die Dies per package 4 Read latency (µs) LSB page write latency (µs) MSB page write latency (µs),353,87 P/Es K K 4 K 6 K K K, Loops... P/E P/Es P/Es P/Es Group A Group B Group E Group F Fig. 7: Variable relaxation cycling procedure. A. Experimental Setting V. EVALUATION We use a TRIAD TCII-6IC NAND flash memory tester [] to perform P/E cycling and PISO operations as well as to collect error numbers. The tester has 6 DUTs, which can execute I/O commands to 6 flash chips simultaneously. We study two types of flash from two venders called Flash A and Flash B, respectively. We use 6 chips of each type. They are all cmlc flash chips manufactured in Y-nm technology. Table II shows their detailed parameters. The read and programming latency are directly measured on the tester. The latency values shown in the table are the mean value of all measured pages. The chips are specified to survive 3K P/E cycles with -bit ECC capacity per 5 bytes. B. Testing Methodology All chips are experienced Variable Relaxation Aging and Retention Acceleration before testing. The goal of applying the variable relaxation aging is to examine the effectiveness of PISO on chips with different P/E cycles. In our experiments, all chips are supposed to be used in a 3 45 C environment, which means a flash memory will be cycled to a certain number of P/E cycles in a 3-year long period and the operating temperature is 45 C. Before applying the aging method, a read bad block operation is performed on all flash memories to identify their bad blocks. All bad blocks are recorded and will not be used in our experiments. For each plane in a chip, 4 blocks are randomly chosen. In order to minimize the programming interference between blocks, choosing the 4 blocks follows two restrictions: () the 4 blocks should be spread across an entire chip as widely as possible; () the number of blocks between two adjacent testing blocks should be larger than. These 4 blocks are separated into 6 groups with each being cycled to a particular P/Es (see the table in Fig. 7). The cycling procedure used in the variable relaxation aging method is illustrated in Fig. 7. The entire procedure consists of, loops. In each loop, different P/E cycles are performed on different groups according to their

6 56 48 K K 4 4K 6 6K PISO operations K K 4 4K 6 6K PISO operations 6 6 (b) PISO operations (c) 4 K K K K PISO operations (d) K K 4 4K 6 6K Read operations (x 3 ) (e) 45 K K Read operations (x 3 ) (f) Fig. 8: Number of errors under, (b) PISO on small cycles; (c), (d) PISO on large cycles; (e), (f) read operations. expected P/E cycles. As a result, the total number of P/E cycles is equal to the number designed. Clearly, the relaxation time of each group varies. Group A receives the longest relaxation time, whereas group F has the shortest one. Pseudo-random data are programmed to all chips. After cycling, we apply an endurance bake for all the chips to simulate a 3 45 C operating environment. According to the Arrhenius equation (.ev activation energy is used) [6], all chips are baked under C for 7.6 hours. The retention acceleration is used to simulate a long period of retention time in a laboratory environment. We assume that all chips are stored under 4 C. Thus, in order to simulate a 3- retention time, chips are baked for 63 hours under 7 C(.eV activation energy is used in the Arrhenius equation). Two types of retention baking schemes are used in our experiments: () long-term baking scheme (LB) applies 63-hour baking time in a single baking process, which directly accelerates flash chips to a 3- retention; PISO operations are carried out after the baking process. () step-baking scheme (SB) divides the entire 63 hours into 3 equal sections so that each -hour section simulates a - retention. The time interval between two adjacent sections is set to hour, within which a group of PISO experiments are performed. It is understood that the number of retention errors varies under different temperatures. In this research, we assume that all flash memory devices are used in a temperature-controlled environment like a data center. Thus, the impact of temperature on the PISO approach is not considered. C. Evaluating the Effectiveness of PISO Fig. 8a to 8d show the average number of bit errors under PISO on Flash A under the LB scheme, whereas Fig. 8e and 8f show that under the read disturb scheme. From the figures we can clearly see that the number of bit errors on all blocks rapidly decreases within the first PISO operations. On average, the number of bit errors is reduced by 3.7% after the first 5 PISO operations. As the number of PISO operations increases, the number of bit errors on all blocks continuously decreases but in a lower rate. Among all cases shown in Fig. 8, PISO delivers its best performance when it reduces bit errors by.9% on 4K-cycled blocks. The rapid decrease in retention errors within the first few PISO operations is due to the fact that when the width of a cell transistor is below -nm the generation of interface traps increases rapidly by a positive stress (i.e., PISO operation) on a memory cell [7]. The newly generated interface traps have the same effect as injected electrons, which push drifted back to its original voltage range. When more PISO operations are applied, the total number of interface traps in the tunnel oxide of a memory cell reaches its saturation point. After that, injecting electrons becomes the major factor to correct retention errors. Theore, the change becomes moderate. After a particular point (e.g., PISOs on K-cycled blocks in Fig. 8c), further increasing the number of PISO operations enlarges the number of bit errors. The error increasing rate in different blocks varies. The blocks cycled to K experience the most significant error increase, while blocks cycled to K have the lowest error increasing rate. The number of errors in K-cycled blocks and in K-cycled blocks increase by 8% and 3.3%, respectively. The reason behind this is that electrons are more prone to escape from and to be injected into blocks with a larger P/E cycles due to a weakened tunnel oxide. D. Comparing Cost with Read Disturb The PISO approach and the read disturb scheme can be categorized into one camp because of the following reasons: () they reduce retention errors by injecting electrons; () they do not require a prior knowledge of the original data; (3) they do not consume extra P/E cycles. Theore, we compare the cost of the two schemes in this section. Fig. 8e and 8f show the retention error reduction capability of the read disturb scheme. Read disturb demands a

7 PISOs PISOs 5 5 PISOs 5 PISOs PISOs PISOs st st nd nd 3 3rd st 3rd nd nd 3rd 3 rd Blocks cycled to K P/Es Blocks cycled to K P/Es 4 PISOs 3 PISOs 5 PISOs 5 PISOs PISOs PISOs st nd nd 3 3rd Blocks cycled to 6K P/Es st st nd nd 3rd 3 rd Blocks cycled to K P/Es Fig. 9: The impact of the number of PISO operations under different P/E cycles. PISOs 5 PISOs PISOs st st nd nd 3 3rd rd Blocks cycled to 4K P/Es PISOs 5 PISOs PISOs st st nd nd 3rd 3 rd Blocks cycled to K P/Es much larger number of read operations in order to reduce a similar number of retention errors that PISO can achieve. For example, 5 PISO operations can reduce 7% of errors on 6K-cycled blocks (see Figure 8c), whereas roughly 7 read operations are needed to reduce the same amount of retention errors by the read disturb scheme (see Figure 8e). According to the read and write latencies shown in Table II, performing 5 PISO operations costs 5, 353µs =6.8ms, whereas applying 7 read operations costs 7 47µs = 3.9ms. Theore, the PISO approach is much faster than the read disturb scheme in order to reduce the same amount of bit errors. Typically, a read operation consumes µj energy, whereas a programming operation costs 5 3µJ energy [3]. Theore, reducing 7% of errors on 6K-cycled blocks consumes at least 7µJ energy (7 operations µj) by the read disturb scheme. PISO, however, at most costs 5µJ energy (5 operations 3µJ). Furthermore, as a PISO operation only performs the first programming-and-verifying step, the total energy consumption is much lower than 5µJ. Thus, PISO is superior to the read disturb scheme in both operation time and energy consumption. E. Impact of the Number of PISO Operations In this section, we use an experiment to illustrate the impact of the number of PISO operations on error reduction. In our experiments, the PISO operations are directly performed by a TRIAD tester on raw flash chips. Unlike real application environments, we use retention bake to accelerate the retention time in a laboratory environment. Fig. 9 exhibits the retention errors on Flash B under an SB scheme. Sixteen chips are evenly divided into four groups with each performing a particular number of PISO operations (see Fig. 9). One group is served as a control group on which no operations is performed. The other three groups receive different numbers of PISO operations after Both PISO and the read disturb scheme are carried out on all the pages of a certain block. We choose one page as an example to compare their costs. every retention bake period. It is obvious that applying PISO operations times each can reduce the largest number of retention errors among the four groups. On average, the retention errors can be reduced by.5% if PISO operations are applied each. Further, we can see that if applying more than PISO operations (i.e., 5 and ) each, the number of errors begins to increase. The reason is that the over-programmed errors introduced by PISO (see Figure 6d) outweighs the number of its reduced retention errors. From Fig. 9 we can see that there is no noticeable difference in terms of retention errors between 5 PISOs and PISOs in most cases. This is because the number of retention errors further reduced by the extra 5 PISOs is almost equal to their introduced over-programmed errors. When the number of P/E cycles is small (i.e., flash is at the beginning for its life), the impact of PISO on retention reduction is limited (see the blocks cycled to K P/Es). Furthermore, the differences of bit errors among the four groups are also small. This is because electrons are difficult to leak from or inject into the floating gate of a less damaged memory cell. Theore, performing PISO operations on a new flash is neither necessary nor helpful. Fig. 8 and 9 demonstrate that the PISO approach noticeably reduces retention errors on both Flash A and B. VI. APPLYING PISO ON REAL APPLICATIONS The PISO approach can be simply implemented in either the FTL of an SSD or in a flash file system. Still, there are multiple issues on how to efficiently apply PISO operations on real applications. In this section, we provide discussions on these issues. Discussion : When is the best time to launch PISO operations? In this group of experiments, the PISO operations are simply launched every. For real applications, however, the timing to invoke a PISO operation has to be caully chosen as various flash memory devices may incur different numbers of retention errors over the same amount of retention time. In addition, it is clear that retention error does not exist in a piece of newly written data. Theore, performing

8 PISO operations on the blocks with newly written data is unnecessary. Discussion : What is the best time interval between two adjacent PISO operations? As stated in Section IV, the distance between and 3 shrinks when retention time increases. If the interval time is too long, the change of distribution will be too large to be pushed back to its initial state. In this case, PISO has little impact on correcting retention errors. For distinct types of flash chips, the effects of a PISO operation vary due to manufacturing processes and materials. Hence, an optimal interval time should be caully examined for a particular flash type. Discussion 3: How many PISO operations are needed in one error correcting process? An appropriate number of PISO operations to be performed demands a comprehensive consideration. A practical solution to the above two issues is to establish a dynamic retention error detection mechanism, which periodically samples retention errors. When the number of retention errors exceeds a pre-defined threshold, it launches a PSIO operation. After a few number of PISO operations (e.g., 5), the mechanism measures the current number of retention errors to decide whether to stop or to carry out more PISO operations. To reduce the performance degradation caused by the mechanism, the priority of PISO operations is configured to a level lower than normal operations. Obviously, an SSD can launch PISO operations whenever it is idle. A PISO operation can introduce over-programmed errors, which may be accumulated over time. The over-programmed errors neutralize the effect of a PISO operation. As a result, the maximum number of reduced errors by PISO decreases. When the minimum number of errors after PISO operations is close to the ECC capacity of a flash memory, any further PISO operations may damage the stored data as the ECC can no longer correct all the errors. In this case, data have to be remapped to another location so that all accumulated errors are eliminated. The remapping process is combined with the dynamic retention error detection mechanism. VII. CONCLUSIONS We propose a novel retention error reduction approach called PISO (programming initial step only). It injects electrons to compensate charge loss over time by programming data that represents a memory cell s lowest threshold voltage to a programmed cell. Experimental results from two types of y-nm NAND flash memory prove the effectiveness of PISO and its low-cost compared with read disturb []. Moreover, an analytical model is built to guide us to discover an appropriate number of PISO operations on a particular flash memory device. The PISO approach has several advantages over the existing retention error reduction schemes discussed in Section II. First of all, a PISO operation is more efficient than a read operation in terms of compensating a cell s charge loss over time for it uses a higher programming voltage to inject electrons into it. Experimental results demonstrate that 5 PISO operations can reduce the same amount of retention errors on a 6K-cycled block as 7 read operations []. Secondly, the over-programmed issue can be well controlled as the number of PISO operations can be easily modulated. On the contrary, the FCR technique [8] only has one programming process, and thus, has no opportunity to manage the over-programmed issue. Finally, the cost of a PISO operation is low because it performs neither a prior read operation nor an ECC algorithm. In current study, we only examine the effectiveness of PISO on raw flash chips. In future work, we will integrate it into a flash storage product like an SSD to further evaluate its efficiency in real-world applications. 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