NAND Flash Basics & Error Characteristics

Transcription

1 NAND Flash Basics & Error Characteristics Why Do We Need Smart Controllers? Thomas Parnell, Roman Pletka IBM Research - Zurich Santa Clara, CA 1

2 Agenda Part I. NAND Flash Basics Device Architecture (2D + 3D) SLC, MLC & TLC Program/Read/Erase Procedure Part II. Error Characteristics Program/erase cycling stress Cell-to-cell Interference Data Retention / Read Disturb Programming Errors 2D vs. 3D Reliability Comparison Santa Clara, CA 2

3 Part I: NAND Flash Basics Santa Clara, CA 3

4 Flash Fundamentals N-Channel MOSFET transistor Applying a gate-to-source voltage generates an electric field through insulator and creates a conduction channel through which current can pass from drain to source. Floating Gate N-Channel MOSFET The fundamental storage cell for Flash memory. Electrons can be stored onto and removed from the isolated floating gate (tunneling effect). Electrons residing on the floating gate remain there when power is removed The tunneling effect is destructive (e- get stuck in the insulator), hence limiting the number of program erase cycles. Electrons may fall off the floating gate over time, especially with increased temperature. Santa Clara, CA 4

5 NAND Flash Architecture (2D) WL[M-1] WL[M-2] WL[2] WL[1] WL[0] BL[0] BL[1] BL[2] BL[3] BL[N-2] BL[N-1] A block of planar NAND Flash consists of a grid of cells connected by word lines (WLs) and bit lines (BLs) Data is programmed/read from the device page-by-page (~16KB) Every WL in the block contains: 1 page (SLC) 2 pages (MLC) 3 pages (TLC) Within a WL, pages can be further interleaved so that each WL contains 2/4/6 pages ( Even-Odd BL Architecture ) Santa Clara, CA 5

6 NAND Flash Architecture (3D) Layer L Layer 3 Layer 2 Layer 1 A block consists of vertically-stacked layers of NAND Flash cells Each layer consists of a grid of cells connected by WLs and BLS Santa Clara, CA 6

7 Flash Memory Organization NAND Flash cell Erase operation Multi-plane operations 3D Architecture Block k Pages Die 2 4 Planes Source: Applied Materials Layers Page 16k+ Bytes Plane Blocks Target 1/2/4/8 dies Read/write operations Data & cache registers Separate I/O Interfaces Santa Clara, CA 7

8 SLC vs. MLC Upper Page Data Lower Page Data Single Level Cell (SLC) 2 States (1 Erase + 1 Pgm) = 1 bit of information per cell Multi Level Cell (MLC) 4 States (1 Erase + 3 Pgm) = 2 bits of information per cell = 2x capacity of SLC! Santa Clara, CA 8

9 TLC Extra Page Data Upper Page Data Lower Page Data Triple Level Cell (TLC) 8 States (1 Erase + 7 Pgm) = 3 bits of information per cell = 1.5x capacity of MLC = 3.0x capacity of SLC Santa Clara, CA 9

10 Incremental Programming (a) Erased State E ISPP Procedure START V TARG (b) First programming pulse Electrons tunnel into FG Apply Programming Pulse FAIL V TARG Verify most cells have higher than V TARG (c) N programming pulses PASS END t PROG ~1500us Santa Clara, CA 10

11 MLC Two-Pass Programming (a) Erased State E Data is programmed to the device one page at a time LP=1 LP=0 (b) Program Lower Page x1 V LPONLY x0 The cells are either left in the erased state of programmed to an intermediate state depending on the lower page data. UP=1 UP=0 UP=0 UP=1 (c) Program Upper Page An intermediate read determines the previously programmed lower page data and the cell distribution for the WL is finalized using the upper page data Santa Clara, CA 11

12 Reading Data Back (MLC) Lower Page Read Upper Page Read V B Detect LP =1 Detect LP =0 Detect UP=1 V A Detect UP =0 V C Detect UP= Lower page can be read using a single read voltage (V B ) Upper page can be read using a pair of read voltages (V A,V C ) A page read typically takes up to 100us Santa Clara, CA 12

13 (a) Fully prog. State Erasing Data is erased one block at a time. An individual page cannot be erased. START (b) First erase pulse V EV Apply Erase Pulse FAIL V EV Verify most cells have less than V EV (c) N erase pulses PASS END t ERASE ~5000us Santa Clara, CA 13

14 Part II: Error Characteristics Santa Clara, CA 14

15 Read Errors Broadening of distributions due to noise can lead to read errors What are the main sources of noise? V B Detect LP =1 Detect LP =0 Detect UP=1 V A Detect UP =0 V C Detect UP= Lower page read errors Upper page read errors Santa Clara, CA 15

16 Program/Erase Cycling Stress RBER of different flash blocks in the same device as a function of P/E cycles 1 in 100 bits are in error Different blocks exhibit different trajectories Repeated application of program/erase (P/E) pulses leads to degraded reliability of the underlying NAND flash cells The measured raw bit error rate (RBER) increases as a function of P/E cycles Low RBER at early life does not indicate a good block, and an early high RBER not a weak one! Strong error-correction codes must be implemented on the controller to be able to deal with increased RBER Santa Clara, CA 16

17 Cell-to-Cell Interference Threshold voltage of victim cell is strongly affected by programming of neighboring aggressor cells can the controller compensate? X i, j 11 X i, j Santa Clara, CA 17

18 Data Retention Over time electrons can escape from the programmed flash cells, causing a loss of threshold voltage This can cause a large increase in RBER unless the controller can shift the read voltage to compensate for charge loss The data retention effect is temperature dependent (charge escapes faster at higher temperature) Before Data Retention 2 40C Santa Clara, CA 18

19 Read Disturb Before Read Disturb After N Reads When reading a particular page in a block of NAND Flash, a voltage is applied to all other WL in order to deselect them Dominant effect of read disturb is seen on Erase state This applied voltage can affect the distributed of the unselected WLs If a block is read from too many times, the RBER will increase to a point that the ECC is no longer able to correct The controller must be able to manage such effects Santa Clara, CA 19

20 Programming Errors Degradation of erase state can cause error propagation during the twopass programming procedure switch to 1-pass? Cells are programmed to the wrong state! Santa Clara, CA 20

21 2D vs. 3D Reliability Scorecard Reliability Issue 2D 3D Comment Program/Erase Cycling TLC endurance: ~100 cycles TLC endurance: >1000 cycles Increased cell dimensions enable new applications for TLC Flash Cell-to-cell Interference X/Y-direction Z-direction Controller management required Data Retention Years (consumer) Months (enterprise) Fast Initial Charge Loss Controller management required Read Disturb Affects both Controller management required Programming Errors 2-pass programming 1-pass programming Improved algorithm can remove programming errors entirely Santa Clara, CA 21

22 Conclusions NAND Flash is currently unrivalled technology in terms of the performance/cost trade-off However, it is inherently unreliable and cannot be used without a controller providing additional functionality What do we require of a controller? Media management / signal processing Powerful error-correction Data placement and garbage collection algorithms Wear-leveling algorithms Efficient FPGA/ASIC/firmware implementations Santa Clara, CA 22