NAND Flash: Where we are, where are we going?

Transcription

1 NAND Flash: Where we are, where are we going? Pranav Kalavade Intel Corporation

2 Outline Introduction 3D NAND Floating Gate 3D NAND Technology CMOS Under Array Cell Characteristics Summary

3 Cell Size [um 2 ] NAND Scaling Trend 70nm 1E+0 2D NAND Cell Size Scaling 1E-1 1E-2 25nm 1E-3 1E-4 '00 '05 '10 '15 '20 Year 2D NAND scaling has slowed down 20nm

4 Cells Vt distribution width [a.u.] 2D NAND Scaling Limiters Lithography Limitations Small Cell Area Effects: Number Fluctuation Proximity Effects: Cell to Cell interference High Electric Field Effects Vt distribution width Vt Cell feature size [nm]

5 Outline Introduction 3D NAND Floating Gate 3D NAND Technology CMOS Under Array Cell Characteristics Summary

6 3D NAND - Scaling Through Stacking Vertical channel 3D NAND Horizontal channel 3D NAND Vertical String vs. Horizontal String Vertical string more attractive electrically Horizontal string more attractive for cell size

7 3D NAND Advantage Cells ~1X nm 2D NAND 3D NAND Eliminates lithography constraint Larger cell size and cell to cell spacing Less parasitic effects and tighter threshold voltage distributions Vt

8 3D NAND Floating Gate vs Charge Trap Floating Gate 3D NAND Charge Trap 3D NAND Discrete Charge Storage Node Continuous Charge Storage Node Floating Gate Good Program/Erase Vt window and Charge isolation between cells Charge Trap Charge dispersion between cells & Need for Metal Gate process

9 Outline Introduction 3D NAND Floating Gate 3D NAND Technology CMOS Under Array Cell Characteristics Summary

10 3D FG NAND Cell Formation (a) Tier deposition (d) IPD formation (g) Tunnel-oxide and channel formation (b) Cell hole etch (e) FG deposition (h) WL Step formation for contacting (c) Recess Formation (f) FG isolation

11 3D FG NAND Technology Metal Layer Contact/Bitline SGD Wordlines (32 Active) SGS Source CMOS Circuits

12 Outline Introduction 3D NAND Floating Gate 3D NAND Technology CMOS Under Array Cell Characteristics Summary

13 CMOS Under Array 3D NAND String is formed fully above the silicon. Enables silicon area under for CMOS circuitry 2 Metal Layers below array for CMOS connections 2 Metal layers above the array for Bitline and Bussing

14 Outline Introduction 3D NAND Floating Gate 3D NAND Technology CMOS Under Array Cell Characteristics Summary

15 Key Cell Characteristics Cell Id-Vg Characteristics Erase Operation Program/Erase Vt Program Disturb Cell Vt distributions Cell to Cell Interference

16 Current [A] Current [Norm] Cell Id-Vg Characteristics 1E-06 1E E-10 1E-12 Vds = 0.5V WL Voltage [V] Surround gate structure of 3D NAND provides for good gate control 3D NAND String on-current matches that of 2D NAND D NAND 20nm 2D NAND WL Voltage [V]

17 Wordlines GIDL Current [A] Erase Operation 1E-08 1E-10 SGS N+ Source Vg Vs 1E-12 1E-14 V WL Vs =0V Vbl = -2V Vgs [V] Erase bias applied to the Source Body biased up by the SGS GIDL

18 Cell Vt [V] Program/Erase Characteristics Program Erase Program/Erase Voltage Delta [V] >10V P/E Window >10V Cell Program/Erase Vt Window is achieved

19 Cell Vt [V] Program Disturb >10V Disturb -1.0 Window -1.5 Achieved -2.0 >10V Sel Cell Inh Cell Gate Voltage [V]

20 Arbitrary Units # Channel Area # of Elec/100mV DVt Vt Distributions 1E+4 1E+3 90nm 70nm 50nm 34nm 3D 25nm 20nm nm 70nm 3D NAND 50nm 34nm 25nm 20nm 1E+2 Technology Node Larger physical cell size of 3D NAND improves Vt distributions Technology Node Natural Vt Distribution Number fluctuation 2D 20nm 3D

21 Cell to Cell Interference e e e e e e e e e e 2D NAND Better shielding from the control gate in the 3D NAND reduces interference by ~80% e e e e 3D NAND Net Interference (A.U.) 2D 20nm 3D 1 2

22 Number of Cells Vt distribution width [a.u.] MLC Vt Distribution Width D 0.5X Vt Distribution [A.U.] 2D 20nm Better intrinsic distribution and lower interference leads to an overall tighter Vt distribution for 3D NAND D NAND Eff Cell feature size [nm]

23 Outline Introduction 3D NAND Floating Gate 3D NAND Technology Cell Characteristics CMOS Under Array Summary

24 SLC MLC TLC QLC? SLC: 2 Levels => 1 bit/cell MLC: 4 Levels => 2 bit/cell RD 1 0 R1 R2 R3 Vt EV 0 PV Vpass_R TLC: 8 Levels => 3 bit/cell 0 EV PV1 PV2 PV3 Vt R1 R2 R3 R4 R5 R6 R7 EV PV1 PV2 PV3 PV4 PV5 PV6 PV7 Vpass_R Vt QLC: 16 Levels => 4 bit/cell R1 R4 R5 R6 R7 EV Vpass_ PV1PV2PV3PV4PV5PV6PV7PV1PV2PV3PV4PV5PV6PV7PV7 Vt

25 Outline Introduction 3D NAND Floating Gate 3D NAND Technology Cell Characteristics CMOS Under Array Summary

26 Summary 3D NAND extends NAND scaling with cell characteristics superior to that of scaled 2D NAND More bits / cell accelerates the scaling: facilitated by superior characteristics of 3D NAND