Digital Logic Level. Buses PCI (..continued) PTE MIK MIT

Transcription

1 Digital Logic Level Buses PCI (..continued) PTE MIK MIT

2 PCI - arbitration REQ# GNT# REQ# GNT# PCI arbiter REQ# GNT# The PCI bus has to be acquired before use by the devices PCI uses centralised bus arbitration REQ# GNT# PCI device PCI device PCI device PCI device

3 PCI - arbitration Device and arbiter have 2 links: REQ# GNT# PCI arbiter REQ# GNT# REQ# - Request line GNT# - Grant for use REQ# GNT# REQ# GNT# PCI device PCI device PCI device PCI device

4 PCI - arbitration Request REQ# GNT# PCI arbiter REQ# GNT# Device (or CPU) asserts REQ#, and waits for GNT# If GNT# asserted, device can use the bus in the next cycle REQ# GNT# REQ# GNT# PCI device PCI device PCI device PCI device

5 PCI - arbitration Arbitration The algorithm to be used is not defined in the standard. It can be Round-robin Priority based Etc.. Arbiter must be fair No device should wait too long/forever

6 PCI - arbitration Bus grant Valid for one transaction Length of transaction is unbound If no others require, the granted master can start several further transactions on the bus, divided by idle cycles In special cases, no idle cycles are needed (even faster data rate). If arbiter negates the GNT# (some device wants to use the bus), master has to stop the transfer and free the bus long and fast transfers and rapid master switches are also possible

7 PCI bus signals Mandatory signals

8 PCI bus signals Mandatory signals CLK clock, drives the bus, not like in ISA, transactions begin at the falling edge of CLK

9 PCI bus signals Mandatory signals AD address or data (early version: 32 bit) (3 cycles: 1-addr, 2-turnaround,3-data)

10 PCI bus signals Mandatory signals PAR AD parity

11 PCI bus signals Mandatory signals C/BE 1st cycle: bus command, what happens (read a word, write a block, etc..)

12 PCI bus signals Mandatory signals C/BE 2nd cycle: bitmap (mask) for valid bytes, which one we need (1,2,3,4 byte)

13 PCI bus signals Mandatory signals FRAME# - busmaster asserts it at start. Indicates: address/data is valid

14 PCI bus signals Mandatory signals IRDY# - At read master asserts it with FRAME#. It says: master is ready to accept incoming data

15 PCI bus signals Mandatory signals IDSEL Every PCI device has a 256 byte configuration space. With IDSEL, it can be read by other devices (Eg.: PnP uses it as well)

16 PCI bus signals Mandatory signals DEVSEL# - if slave detects it s address on AD, it indicates that it is ready for a transaction. If no signal here, master sees slave as broken or absent

17 PCI bus signals Mandatory signals TRDY# - at read: data on AD; at write: ready to receive data

18 PCI bus signals Mandatory signals STOP# - error, slave stops transaction

19 PCI bus signals Mandatory signals PERR# - parity error in the last cycle. At read, master sets it, at write, slave sets it. Receiver chooses what to do

20 PCI bus signals Mandatory signals SERR# - Address error (parity) or system error

21 PCI bus signals Mandatory signals REQ#/GNT# - arbitration signals

22 PCI bus signals Mandatory signals RST# - Reset, system goes to initial state (extreme error or user presses reset)

23 PCI bus signals Optional signals Optional signals Most of them needed for bit mode

24 PCI bus signals Optional signals REQ64# - busmaster wants a 64 bit transaction

25 PCI bus signals Optional signals ACK64# - slave accepts the 64 bit transaction

26 PCI bus signals Optional signals AD/PAR64/C/BE# - +32bit extensions for 64 bit transfer (data, parity, bitmap)

27 PCI bus signals Optional signals Next three signals optional not every PCI card has to handle connected with Multiprocessor systems (eg. Snooping)

28 PCI bus signals Optional signals LOCK bus is locked for several transactions by one master (CPU)

29 PCI bus signals Optional signals SBO#/SDONE snooping signals - cache cocherency

30 PCI bus signals Optional signals INTx Interrupt request signals. One physical PCI device can be a composition of 4 logical, independent devices with separate interrupt request lines

31 PCI bus signals Optional signals JTAG IEEE JTAG test functions. (connection and function test for IC-s)

32 PCI bus signals Optional signals M66EN clock frequency setup (33 or 66 MHz). Can t be changed during operation

33 Bus transactions Read idle cycle write transactions

34 PCI bus transactions T1 falling edge: AD gets memory address, C/BE# has the bus command (memory read), FRAME# is set, transaction starts

35 PCI bus transactions T2 : master lets bus free (turn around), slave gets control in T3. Master sets C/BE# (byte mask)

36 PCI bus transactions T3: slave sets DEVSEL#, master gets known that slave has the address and will reply. Slave puts data onto AD, sets TRDY# - it is done. If slave can t provide data instantly, sets DEVSEL# but keeps TRDY# negated waiting (this was the WAIT signal in general).

37 PCI bus transactions T4: idle cycle, mostly one idle cycle is inserted at he end of transactions

38 PCI bus transactions T5: Writing transaction starts: data onto AD, C/BE# bus command (write), start with FRAME#t

39 PCI bus transactions T5: no real turn around, same device will use the AD lines, still, we call it turn around

40 PCI bus transactions T7: memory gets the data

41 PCI PCI works well, but I/O bandwidth got low for needs New buses arose for faster devices. The new central element for bus communication is the bridge chip

42 PCI The PCI cards were too big for portable devices (laptops, palmtops) New direction: repartition the PC CPU, Graphical card, etc.. Can go into one boksz, far away, HDD (rack), optical drive, USB ports can go on a desktop box. PCI doesn t support this distances

43 (PCI-E, PCIe) Intel development (2004) Nothing to do with PCI, but the name was well marketed Not even a bus Concept Parallel wires has to go, master-slave duos has to go High speed serial connections must work, parallel This is a radical change to ISA/EISA/PCI concepts Many ideas come from LAN-s

44 PCI Express CPU,Memory - I/O-chips connected by a general switch This is the PCI Express

45 PCI Express CPU,Memory is connected on a dedicated high speed lane, the Bridge Chip is on it as well The Bridge Chip is connected to the PCIe Switch. Every I/O Device connects to it with two cables: GND + DATA high noise immunity PCI Express

46 PCI Express 3 key differences to PCI First 1. PCI: multidrop, common bus PCIe: centralized switch Second 2. PCI: wide, parallel wires (32/64 bits) PCIe: narrow serial point-to-point connections (1 bit) Third 3. PCI: bus master/slave communication PCIe: packet based communication

47 PCI Express PCIe packet switching Packets: Header (control info, like control lines) Data (payload) PCIe based PC is a little packet switched network

48 PCI Express Some minor diff. between PCI and PCIe PCIe uses error detecting code Chip Switch distance can be up to 50 cm Device can be a switch (tree structure) Hotplug is allowed PCIe connectors are smaller smaller, integrated devices can use it as well

49 PCI Express Protokol Stack The PCI Express uses a layered protocol stack Protokol: set of rules of conversation between two parties (a) : PCIe protokol stack 4 layers

50 PCI Express Protokol Stack Physical layer Moving bits between two parties Every connection is one or more simplex (one way) lane pairs (channel pairs). Normally there is one pair, but it can be 2,4,8,16 or 32 pairs (byte striped) Number of lanes equal in both directions One direction speed: min. 2,5 Gbps (3.0: 8 Gbps, : 16 Gbps - raw transfer rate (GT/s))

51 PCI Express Protokol Stack Physical layer No clock, devices start sending as soon they has to fast communication, but: Several similar 0-s or 1-s: how many? 10? 11? Solution: 8b/10b coding: 8 bits on 10 bits (20% bandwidth loss) Not too many 0 or 1 can follow each other Same number of 0 and 1 should be in one word This is enough signal change to sync.

52 PCI Express Protokol Stack Link layer Task: Package transmission Packet from transaction layer gets CRC (Cyclic Redundancy Check) code. CRC: error detection code Receiver calculates CRC as well, if it s the same, OK sends an acknoledgment packet. If not, asks for resend. (PCI couldn t do that)

53 PCI Express Protokol Stack Link layer Flow control mechanism Fast transmitters shouldn t flood slow receivers: Receiver gives credits (buffer size) for the transmitter. Transmitter sends just as much data for the receiver how much it can accept in the buffer slow and fast devices can communicate (and network is not overloaded)

54 PCI Express Protokol Stack Transaction layer Bus actions are handled Eg.: reading a word from memory needs two transactions: CPU (or DMA) initiates a transfer, ask for data Target answers back with data New services : Every lane is divided into 8 virtual circuits. Each can handle different class of traffic. They all are taged different, like high priority, no snoop, out of order delivery, etc.. Switch can decide between them what to forward next.

55 PCI Express Protokol Stack Transaction layer Every transaction uses one of these address spaces: Memory space (read - write) I/O space (device register addressing) Similar to prevoius systems Configuration space This is similar to prevoius systems Eg. Good for PnP realisation Message space (Signaling) No signal lines (wires) in PCIe, this must be used for signaling

56 PCI Express Protokol Stack Software layer Connection to the OS It can emulate the PCI bus (If OS doesn t know PCIe, it can communicate as it was PCI)

57 PCI Express information flow Software layer gives the command to the transaction layer. It will be divided into Header and Payload parts Link layer adds sequence number and CRC Physical layer adds start and end frames and sends packets

58 PCI Express The packet switched behaviour is fully done by hardware, it is transparent to the OS. Computer network layers are known by the OS.

59 PCI Express PCI Express connectors (4 lane, 16 lane, 1 lane, 16 lane connections and PCI connector)

60 PCI Express PCI Express 2.0 speeds PCI Express 2.0 Implementation Encoded Data Rate Unencoded Data Rate x1 5 Gbps 4 Gbps (500 MB/sec) x4 20 Gbps 16 Gbps (2 GB/sec) x8 40 Gbps 32 Gbps (4 GB/sec) x16 80 Gbps 64 Gbps (8 GB/sec) 2x bandwidth as for 1.0 High power device support ( W) PCIe Cable: even 10 meters distance is OK. New boksz types (separated boxes)

61 Slow device connections PCI and PCIe are fast but expensive. Slower needs should be solved more cheap Simple devices need simple connectors Originally every device had a controler card, this means setting up (jumpers? PnP) and building in cards Serial and parallel ports were not fully standard issues for normal users and driver development problems

62 USB (Universal Serial Bus) 1993 several companies (Compaq, DEC, IBM, Intel, Microsoft, NEC, etc..) created the standard for slow devices: USB Some goals: No nees for configuring devices (jumpers, miniswitches) No need for opening computer cases Only one type of cable Power should be provided by this cable

63 USB (Universal Serial Bus) Some goals: Several devices should be attachable Good for real-time devices (telephony) Devices should be installable while running (no reboot or switch off) Should be stay cheap

64 USB (Universal Serial Bus) USB 1.0 USB Mbps printer, digital cameras USB 2.0 1,5 Mbps keyboard, mouse, webcam, scanner, etc Mbps external storages USB Gbps

65 USB Root hub connects to system bus Further devices and switches can be attached to root hub tree structure 4-wire cable : 2 data 1 power (+5V) 1 ground

66 USB USB signals Voltage transition: 0 No voltage transition: 1 New device: Root hub senses it, interrupts CPU OS checks type of device (what is the bandwidth need) If there is enough bandwidth, device gets unique address (1-127) and loads configuration data to device

67 USB USB logic Bit pipes (channels) between device and roothub Devices can divide channels into 16 sub-channels Data goes only through the root-hub, no direct connection between usb-devices

68 USB Root hub broadcasts every 1,00±0,05 ms a new frame to keep devices synchronised in time One frame Is associated with a channel Consists of packets. First is sent by root-hub to device. Others can go in several directions.

69 USB Four frame series:

70 USB In frames 0 and 2 : no job, only a SOF (Start of Frame) packet (every device gets it synch.)

71 USB Frame 1: reading from a device (eg. scanner), Frame 3: writing to a device (eg. printer)

72 USB USB supports 4 frame types: Control frame Used for configuring devices, send commands, asking status Isochronous frame Real time devices use this (telephones, microphones, speakers), they have to do tasks at given intervals. No repeat at failures Bulk frame (data frame) Large transfers not real-time (error detection needed) Interrupt frame USB doesn t support interrupts. Eg. a keyboard generates no interrupts, but the OS has to read out it s buffer in a given interval (every 50 ms)

73 USB Frames consist of one or more packets TOKEN From root to device SOF Start of Frame, every frame starts with that IN device is asked for data. Fields in IN tell which channels are polled, what data has to be sent OUT Device gets data SETUP device configuration DATA Max. 64 byte data in one direction

74 USB Packets DATA 8 bit synch field (SYN), 8 bit packet type (PID), Payload 16 bit CRC code

75 USB Packets Three handshake packets ACK everything arrived fine NAK CRC error in transfer STALL device is busy, wait

76 USB Interface USB 1.1 (1998) UHCI (Universal Host Controller Interface) Intel design, work has to be done by software cheaper, uses more CPU OHCI (Open Host Controller Interface) Compaq/MS design, work has to be done by hardware more expensive, less CPU consuming

77 USB Interface USB 2.0 (2000) EHCI (Enhanced Host Controller Interface) This can emulate OHCI,UHCI (for older USB devices) This can use the 480 Mbps speed USB 2.0 competitor: IEEE 1394 FireWire 400 Mbps (used for camera, video devices)

78 USB connectors Robust Not easy to brake Hard to attach bad Cheap to produce Different endings (USB A,B, USB mini A,B) help to support the topology (tree) Easy to use Outer metal shell to handle static charge

79 USB connectors USB A USB B USB Mini A & B