Fusion Power Sequencing and Ramp-Rate Control

Size: px

Start display at page:

Download "Fusion Power Sequencing and Ramp-Rate Control"

Gavin Snow
5 years ago
Views:

1 Application Note AC285 Fusion Power Sequencing and Ramp-Rate Control Introduction As process geometries shrink, many devices require multiple power supplies. Device cores tend to run at lower voltages to reduce power and maximize performance. To interface to legacy devices or to comply with existing I/O standards, I/O voltages run at voltages different from and typically higher than the core. Often devices support multiple I/O banks, each running at a different voltage level (1.8 V, 2.5 V, or 3.3 V). In order to reconfigure or reprogram devices, it is common to support yet another power rail. The increase in the number and inter-relationships between these power rails greatly increases the complexity of board-level power supply management. Designs with FPGAs, DSPs, and ASICs can demand four, five, or even more power supplies to power up in a prescribed sequence and ramp-rate in order to avoid issues such as latch-up, inrush current, or I/O contention. Additionally, many applications require adjustable power-up sequencing and ramp-rates to accommodate various scenarios. To fulfill the requirements in these applications, a power system management master must be live at power-up in order to sample and monitor multi-channel analog voltage inputs. Based on the system requirements, the master sequences multiple power supplies at a given ramp-rate. The master also has the flexibility to update to a different sequencing and ramp-rate and can remember the previous parameters used in sequencing and ramp-rate control. The Actel Fusion Programmable System Chip (PSC), the world's first mixed-signal FPGA, is an excellent single-chip solution for power sequencing and ramp-rate control applications. As a Flash-based FPGA, the Fusion PSC is live at power-up. It delivers a configurable analog system to sample and monitor up to 30 channels of analog signals and control up to 10 gate drivers with programmable drive strengths that control sequence and ramp-rates of multiple power supplies. Integrated embedded Flash memory enables a wide variety tasks: recording system performance history, updating operating parameters, monitoring system parameters to predict failures before they occur (prognostics), EEPROM emulation, and boot code storage. The embedded Flash can be read or updated from the standard JTAG ports or from the FPGA fabric while the device is online. With an internal voltage regulator to generate the 1.5 V core voltage, Fusion PSCs require only a single 3.3 V power supply. While the Flash process provides Fusion with low static and dynamic power consumption, the user can easily implement low power standby and sleep operation modes by using the internal voltage regulator for further power savings. The internal real-time counter (standby) or an external signal (standby and sleep) can wake up a Fusion device. Fusion system development is supported by the SmartGen core generator, a graphical interface delivered within the Actel Libero Integrated Design Environment (IDE). This document discusses the use of Fusion for power sequencing and ramp-rate control. Power Sequencing and Ramp-Rate Control There are four basic types of power sequencing and ramp-rate control. 1. The power supplies will be turned on successively with a fixed delay between them (i.e., V2 power supply will be on with a fixed delay after V1 is powered up), as shown in Figure 1. V1 V2 T Figure 1 Power Sequencing Type 1 September Actel Corporation

2 2. One power supply has to reach a minimum threshold level before the next supply is initiated, as shown in Figure 2. V1 V1 Threshold or Min V2 Figure 2 Power Sequencing Type 2 3. Turn on multiple power supplies at the same time but with different ramp-rates, as shown in Figure 3. V1 V2 Figure 3 Power Sequencing Type 3 4. Actively monitor and control multiple supplies during power-up to ensure they are within a specified range of each other (digital tracking), as shown in Figure 4. V1 V2 Figure 4 Power Sequencing Type 4 Although Fusion is capable of managing all four types of power sequencing and ramp-rates, this document only describes the first three types of power sequencing. Before discussing these three types, it is important to understand traditional methods of power sequencing and ramp-rate control. 2

3 Traditional Power Sequencing and Ramp-Rate Control Techniques RC Solution A simple approach for sequencing the supply voltages of two or more circuits on the same rail is to introduce a delay between them by adding a series resistor and capacitor to ground on the power line (Figure 5). R V SUPPLY1 V SUPPLY2 C V SUPPLY1 Figure 5 Power Sequence Control Using a Series Resistor and Capacitor The delay on the second supply (V SUPPLY2 ) will depend on the rise time of the main supply (V SUPPLY1 ). Although this technique may work for some applications, it has many disadvantages: 1) the second supply could ramp-up faster than the main supply when there is residual charge in the capacitors during power cycling, resulting in no ramp-rate control at all; 2) the delayed supply voltage at power-down remains applied to the load longer than does the supply voltage that came up first; 3) there may be a significant power loss through the resistor. Comparator Solution In order to prevent one supply from coming up before another, the primary supply needs to be monitored. When the primary supply comes up first and reaches a certain level (V REF ), the second supply is powering on by turning on the pass MOSFET transistor. The ramp-rate is defined by the driving strength of the MOSFET driver as well as the parasitic capacitor value of the MOSFET transistor. Figure 6 illustrates the comparator solution. V SUPPLY2 V SUPPLY2 C MOSFET Driver R V REF V SUPPLY1 V SUPPLY1 Figure 6 Power Sequence Control Using a Comparator and Delay Elements The reference voltage on the negative input of the comparator sets the level to be reached by V SUPPLY1 before V SUPPLY2 turns on. An RC combination on the other input adds a delay to the trigger. Adding this small delay provides an additional reliability advantage. An N-Channel MOSFET switch guarantees no current flows into the V SUPPLY2 line when power is off or when V SUPPLY1 has not yet reached the desired voltage. This approach also guarantees that V SUPPLY2 is shut down when V SUPPLY1 is not present. However, 3

4 the power-up timing still depends on the rise time of V SUPPLY1, which may not be accessible to the designer. In addition, for different ramp-rate requirements, the user needs to find different MOSFET drivers. The more the power supplies need to be sequenced, the more complex the design will be. Because external components are required for this solution, it will also increase the board size dramatically as well as the cost. This solution may not work well when both positive and negative supplies are presented for sequencing. Fusion Power Sequencing and Ramp-Rate Control Solution With the Fusion PSC family, Actel introduces the Analog Quad analog I/O structure (Figure 7). The Analog Quad is comprised of four I/O pads including analog voltage (AV) input, analog current (AC) input, analog temperature (AT) input, and a single gate driver output, analog gate (AG) pad. AV, AC, and AT are used to precondition analog signals before sending to a configurable 12-bit successive approximation register (SAR) analog to digital converter (ADC) for conversion. The Analog Quad inputs are tolerant up to 12 V ± 10%. The Analog Quad offers a wide range of configurability in terms of prescaler values, positive or negative voltage support, and I/O functionality. Refer to the Fusion Family of Mixed-Signal Flash FPGAs datasheet for details on Analog Quads. Power Supply Line Side Load Side Off-Chip Pads AV AC AG AT Voltage Monitor Block Current Monitor Block R pullup Gate Driver Temperature Monitor Block On-Chip Analog Quad Prescaler Prescaler Prescaler Digital Input Digital Input Power MOSFET Gate Driver Digital Input Current Monitor/Instr Amplifier Temperature Monitor To FPGA To FPGA From FPGA To FPGA To Analog MUX To Analog MUX To Analog MUX Figure 7 Fusion Analog Quad Utilizing Analog Quads and the ADC, Fusion provides a smart, simple, and flexible solution for power sequencing and ramp-rate control. This solution does not need external components like RC, comparator, or MOSFET drivers, which saves board space and cuts down the system cost tremendously. Also, this allows true sequencing while not relying on the main power supply s rise time. 4

5 Figure 8 shows an example of power sequencing and ramp-rate control using a Fusion device VDC +5 VDC +12 VDC 12 VDC AVn12p0v ACn12p0v AV12p0v AC12p0v AV5p0v AV3p3v AVn12p0vON V CC AV12p0vON Fusion AV5p0vON AVn12p0V_load AV12p0V_load AVn5p0V_load AV3p3vON AV3p3V_load Figure 8 Fusion Power Sequencing and Ramp-Rate Control Solution Diagram For power sequencing and ramp-rate control applications, Fusion can be configured to continuously monitor power supplies (four power supplies in the above example). Based on user-defined conditions, Fusion can turn on the power MOSFET transistors to provide power to the load. Using voltage monitoring, the user can define the turn-on condition for one power supply based on the voltage level of another power supply, or one power supply can turn on with a fixed delay after another power supply is turned on. At the same time, the user can also define the ramp-rate of each power supply by selecting a different driving strength of the Fusion gate driver. The Fusion Gate Driver is designed to work with external P-Channel or N-Channel MOSFETs. The gate driver is a configurable current sink or source and requires an external pull-up or a pull-down resistor. The ramp-rate is defined by the following parameters in EQ 1: dv/dt = Ig/Cgd EQ 1 Ig Drive strength of the Fusion gate driver, or source/sink current on the gate Cgd Parasitic capacitor between gate and drain of the power MOSFET transistor 5

6 For a given power supply voltage, Ig and Cgd define how soon it can ramp up to its full scale. Figure 9 shows the concept of ramp-rate control using the Fusion gate driver. V SUPPLY = 5 V R pullup Cgs Power s Fet d g Cgd V LOAD V V SUPPLY V GATE V LOAD 5 Ig 4 3 Gate slews until Vt is reached 2 Sample Parameters: 1 Gate slews to final value Vgs = lg R pullup = 3 V V SUPPLY = 5 V R pullup = 300 kω lg = 10 µa Fet Vt = 2 V Cgs = Ciss = 10 nf Cgd = Coss = 2 nf 0 0 Turn on lg Cgd feedback damps Vg and limits load slew to dv/dt = lg/cgd = 5 V/mS Time (ms) Figure 9 Ramp-Rate Control Concept Using Fusion Gate Driver To control the power supply at different ramp-rates, the user can preset the driving strength of each Fusion gate driver for the corresponding power MOSFET transistor. See the "Application Implementation" section on page 7 to configure the gate driver. The user can also dynamically change the ramp-rate for multiple power supplies by controlling the On/Off state of the corresponding MOSFETs. This is also called digital tracking, which is covered in a different application note. Fusion gate drivers have 4 levels of selectable driving strength: 1 µa, 3 µa, 10 µa, and 30 µa. In Figure 9, the user implemented a 5 V/mS ramp-rate control for a 5 V power supply by selecting a 10 µa gate driver driving strength for Ig, and a power MOSFET with the Cgd fixed to 2 nf. The user can easily change the ramp-rate by selecting a different driving strength gate driver or a different power MOSFET. Figure 10 shows the Fusion gate driver with different selections of source and sink driving strength. AG High Current 1 µa 3 µa 10 µa 30 µa Figure 10 Fusion Gate Driver 6

7 All control logic and timing for power-up sequencing and ramp-rate is implemented inside the FPGA fabric, and it is therefore completely configurable and controllable by the user. Application Implementation Application Description This section examines a design example and shows the voltage sequencing and ramp-rate control using Actel Fusion. A simplified ATX power supply system serves as an example. See Figure 8 on page 5. A 4-voltage system (+5 VDC, +12 VDC, 12 VDC, and +3.3 VDC), as shown in Figure 8 on page 5 The power supplies may be turned on in any sequence as specified by the user. In this case, the order is 12 VDC, +12 VDC, +5 VDC, and +3.3 VDC. All four supply voltages and load voltages will be continuously monitored. Monitoring the load side voltage ensures that the sequence works correctly. Current on the 12 VDC and +12 VDC power supplies will be monitored. The power supplies will be shut down in the reverse order (i.e., +3.3 VDC, +5 VDC, +12 VDC, and 12 VDC). There are various ways and possibilities for turning on the supplies one after another. In this design example, the MOSFET will be turned on using two scenarios: One power supply has to reach a threshold level on the load side before the next MOSFET is turned on for another power supply. The power supplies will turn on, one by one, with a fixed delay in between them; i.e., all the load supplies will turn on and off with fixed delays between them. In each scenario, a different ramp-rate is selected for different power supplies. The design will use the following peripherals in the Fusion device: 8 voltage monitors to monitor the supply and the load voltages 2 current monitors to monitor the supply current on the 12 VDC and +12 VDC power supplies 4 gate drivers connected to three external P-Channel MOSFETs to control the positive power supplies and one external N-Channel MOSFET to control the negative power supply 2 digital inputs to start power-up and power-down sequence Several output flags to show the supply voltage and load voltage conditions Table 1 shows the signal names and the threshold levels for the various voltage and current monitors. Table 1 Voltage/Current Monitor Signal Names and Threshold Values Threshold Max. Value (V) Gate Driver Driving Strength Descriptions Signal Name Voltage Tolerance High Low Ramp-Rate (Cgd = 2 nf) 12 VDC Supply AVn12p0v 10% 10.8 V VDC Supply AV12p0v 5% 11.4 V VDC Supply AV5p0v 5% 4.75 V VDC Supply AV3p3v 4% 3.17 V 4 12 VDC Load Supply AVn12p0v_load 10% 0.8 V 10.8 V µa 6 V/mS +12 VDC Load Supply AV12p0v_load 5% 11.4 V 0.8 V µa 6 V/mS +5 VDC Load Supply AV5p0v_load 5% 4.75 V 0.8 V 4 10 µa 2.5 V/mS +3.3 VDC Load Supply AV3p3v_load 4% 3.17 A 0.8 V 4 3 µa 1.5 V/mS 12 VDC Supply Current ACn12p0v N/A 1.5 A N/A +12 VDC Supply Current AC12p0v N/A 2.0 A N/A 7

8 Design Implementation Fusion analog voltage inputs will be configured with continuous monitoring of all inputs and load voltages. When power supplies reach the user-defined threshold values, flags will be generated. These flags will be passed to a state machine, which is used to control the power MOSFET transistors to control the power to the load. The state machine will enable control of the load supplies in two ways to cover both scenarios. A generic VHDL code will enable the user to switch between both scenarios. To implement the design, perform the following steps: 1. Generate voltage monitor blocks using SmartGen. 2. Generate gate driver blocks using SmartGen. 3. Configure the sample sequence and Flash memory. 4. Create the state machine. For more information, refer to the sample Libero IDE design project. Figure 11 shows the simplified block diagram of the power sequence control system. SYS_RESET NVM Blocks Analog_Inputs ADC Blocks To Gate Drivers Outputs State Machine for Voltage Sequence Control SYS_CLK Figure 11 Overview of the Power Sequence and Ramp-Rate Control System Generate Voltage/Current Monitors Using SmartGen Use SmartGen to generate the Voltage/Current monitors. The Analog System Builder in SmartGen enables you to configure an entire analog system. The following functions can be done: Choose the number of analog input channels to monitor. Choose the type of each input channel. Choose the number of analog output channels. Specify the placement of each channel. Set channel-specific options. Sequence the channels in the required sampling order. 8

9 Voltage Monitor offers a robust set of voltage monitoring capabilities. Using the SmartGen Voltage Monitor, you can configure all four input supplies and all four load supplies. Figure 12 shows the Voltage Monitor block for the 3.3 VDC supply. Figure 12 Voltage Monitor Block for the 3.3 VDC Supply 9

10 When the Current Monitor circuit is selected, two adjacent analog inputs (AV and AC) measure the voltage drop across a small external sense resistor. Figure 13 shows the Current and Voltage Monitor blocks for the +12 VDC supply. Figure 13 Current and Voltage Monitor Blocks for +12 VDC Supply Generate Gate Driver Blocks Using SmartGen The gate driver is the analog output coming from the analog system. It is used to drive the gate of an external MOSFET to turn it on or off. The gate driver is designed to work with external MOSFETs as a configurable current sink or source. Table 2 shows the output signal name and enable signal name for gate drivers. Figure 14 on page 11 shows the gate driver for the 12.0 VDC load supply. Table 2 The Gate Driver Signal Descriptions Signal Name Enable Signal Gate driver for 12 VDC load AVn12p0v_ON AVn12p0v_ENABLE Gate driver for +12 VDC load AV12p0v_ON AV12p0v_ENABLE Gate driver for +5 VDC load AV5p0v_ON AV5p0v_ENABLE Gate driver for +3.3 VDC load AV3p3v_ON AV3p3v_ENABLE 10

11 Figure 14 Gate Driver for the 12 VDC Load Supply See the "Appendix" on page 15 for details on other peripheral configurations. 11

Configure the Sample Sequence and Generate the Flash Memory Block Once all the peripherals are generated, set up the ADC sample sequence (Figure 15).

12 Configure the Sample Sequence and Generate the Flash Memory Block Once all the peripherals are generated, set up the ADC sample sequence (Figure 15). Figure 15 Sample Sequence Control Next, load the configuration data generated by the Analog System Builder into the Flash memory. This allows all the analog system components to be initialized by the Flash memory system at start-up. A Flash memory block can be generated by SmartGen. Create the State Machine The state machine is the heart of the power sequence controller. It allows you to power up and power down the load supplies according to the system needs. In this application note, there are two scenarios for power-up: Each load power supply has to reach a threshold level before the next supply is turned on. Each power supply is turned on after a fixed delay. The parameter USE_fixed_Time is used to switch between the two modes. 12

13 The simplified state machine for the first scenario is shown in Figure 16. Turn FPGA supply and reset all flags. No No No Is 12.0 V flag = 1? Is 12.0 V flag = 1? Is 5.0 V flag = 1? Is 3.3 V flag = 1? Yes Yes Yes Yes No Set flag to '1'. Set flag to '1'. Set flag to '1'. Set flag to '1'. Are all flags set to '1'? Yes No No No No No Is PwrUP '1'? Is 12.0 V load greater than threshold? Is 12.0 V load greater than threshold? Is 5.0 V load greater than threshold? Is 3.3 V load greater than threshold? Yes Yes Yes Yes Yes Turn on 12.0 V gate driver. Turn on 12.0 V gate driver. Turn on 5.0 V gate driver. Turn on 3.3 V gate driver. Monitor all supplies. No No No No No Is PwrUP '1'? Is 3.3 V load less than threshold? Is 5.0 V load less than threshold? Is 12.0 V load less than threshold? Is 12.0 V load less than threshold? Yes Yes Yes Yes Yes Turn off 3.3 V gate driver. Turn off 5.0 V gate driver. Turn off 12.0 V gate driver. Turn off 12.0 V gate driver. Go to reset. Figure 16 State Machine 13

14 Conclusion Fusion has all the features needed to implement a power sequencing and ramp-rate control master in a single chip. The SmartGen user interface and IP allows customers to implement their applications simply and quickly. With all these features tied to Flash FPGA logic, the power sequence and ramp-rate control management system can be completely customized by the user and all configuration parameters can be stored in the embedded Flash memory. Actel Fusion offers flexibility unmatched by any other power management control solution. Related Documents Datasheets Fusion Family of Mixed-Signal Flash FPGAs List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version ( /9.06*) Page /8.06 The High Thresholds for 3.3 VDC and 12 VDC were updated in Table 1. 7 Figure 5 was updated. 3 Figure 17 was updated. 15 Figure 22 was updated. 18 Figure 24 was updated. 19 Note: *The part number is located on the last page of the document. 14

15 Appendix Figure VDC Supply Monitor Figure VDC Supply Monitor 15

16 Figure VDC Supply Monitor 16

17 Figure VDC Supply Monitor 17

18 Figure VDC Load Supply Monitor Figure VDC Load Supply Monitor 18

19 Figure VDC Load Supply Monitor Figure VDC Load Supply Monitor 19

20 Figure VDC Gate Driver Figure VDC Gate Driver 20

21 Figure VDC Gate Driver Figure VDC Gate Driver 21

22 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. Actel Corporation 2061 Stierlin Court Mountain View, CA USA Phone Fax Actel Europe Ltd. Dunlop House, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone +44 (0) Fax +44 (0) Actel Japan EXOS Ebisu Bldg. 4F Ebisu Shibuya-ku Tokyo 150 Japan Phone Fax Actel Hong Kong Suite 2114, Two Pacific Place 88 Queensway, Admiralty Hong Kong Phone Fax /9.06

Live at Power-Up. Key Actel Benefits. The Time it Takes an. FPGA to Power Up has a. Significant Impact on. Effective System Design

Live at Power-Up. Key Actel Benefits. The Time it Takes an. FPGA to Power Up has a. Significant Impact on. Effective System Design The Time it Takes an FPGA to Power Up has a Significant Impact on Effective System Design and the Total System Cost Key Actel Benefits Level 0, Best in Class, Live at Power-Up (LAPU) Support Operational