Computer Organization: A Programmer's Perspective

Transcription

1 Computer Architecture and The Memory Hierarchy Oren Kapah Typical Computer Architecture CPU chip PC (Program Counter) register file AL U Main Components CPU Main Memory Input/Output Devices Buses bus interface I/O Bridge main memory I/O bus USB controller graphics adapter disk controller mouse keyboard monitor disk 2

2 Typical Computer Architecture CPU chip PC (Program Counter) register file A L U Main Components CPU Main Memory Input/Output Devices Buses bus interface System bus I/O Bridge Memory bus main memory I/O bus USB controller graphics adapter disk controller mouse keyboard monitor disk 3 Bus Bus: Electrical conduit carrying bits back and forth Serial bus: One bit after another Serial port, RS232, USB (Universal Serial Bus) Parallel bus: X bits in parallel Faster, but requires more lines (line per bit) Older printers, hardware buses in your computer For simplicity: X = word size i.e., buses carry W bits in parallel (W: Word size in bits) Possible to have multi-word buses, etc. Buses often have control signals e.g., letting receiver know when to expect bits e.g., setting intended recipient 4

3 Typical Computer Architecture CPU chip PC (Program Counter) register file AL U Main Components CPU Main Memory Input/Output Devices Buses bus interface I/O Bridge main memory I/O bus USB controller graphics adapter disk controller mouse keyboard monitor disk 5 Input/Output Devices Connections to external world Each device connected to bus by either controller or adapter Controller: chips in device or on motherboard Adapter: cards that plug into slot on motherboard Devices often have their own processing capabilities Do some processing on-board Alert CPU when ready (via interrupt) This parallelizes processing 6

4 Typical Computer Architecture CPU chip PC (Program Counter) register file AL U Main Components CPU Main Memory Input/Output Devices Buses bus interface I/O Bridge main memory I/O bus USB controller graphics adapter disk controller mouse keyboard monitor disk 7 Typical Computer Architecture CPU chip PC (Program Counter) register file AL U CPU Algorithm: Read instruction from address in PC Interpret bits in instruction Perform instruction using ALU Update PC (sometimes based on instruction) Go to beginning bus interface I/O Bridge main memory I/O bus USB controller graphics adapter disk controller mouse keyboard monitor disk 8

5 Machine-Level Code Representation Encode Program as Sequence of Instructions Each simple operation Arithmetic operation Read or write memory Conditional branch Instructions encoded as bytes Alpha s, Sun s, Mac s use 4 byte instructions» Reduced Instruction Set Computer (RISC) PC s use variable length instructions» Complex Instruction Set Computer (CISC) Different instruction types and encodings for different machines Most code not binary compatible Programs are Byte Sequences Too! 9 Representing Instructions int sum(int x, int y) { return x+y; For this example, Alpha & Sun use two 4-byte instructions Use differing numbers of instructions in other cases PC uses 7 instructions with lengths, 2, and 3 bytes Alpha sum FA 6B Sun sum 8 C3 E PC sum E5 8B 45 C EC 5D C3 Different machines use totally different instructions and encodings

6 CPU Instructions Stored in memory, like any other collections of bits Examples: Load/Store value in main memory, registers Copy contents of registers to ALU, perform some math operation Extract new address from register, copy to PC (i.e., jump) Check condition, store result in one of the registers Conditional jump... Typical Computer Architecture CPU chip PC (Program Counter) register file AL U Main Components CPU Main Memory Input/Output Devices Buses bus interface I/O Bridge main memory I/O bus USB controller graphics adapter disk controller mouse keyboard monitor disk 2

7 There are many types of memories Volatile: Lose contents when power turned off RAM Non-volatile: Maintain memory after power turned off BIOS, ROM Firmware, Flash memory, EEPROM,... Hard disk Magnetic tapes, CD-Roms, CD-RW, DVD-RW,... Memories vary in access speed, cost In general, faster == more expensive (per byte) 3 Executing Hello, World () User types./hello in command-line shell (2) Shell executes a series of instructions, that ultimately do: (3) Identify a file called hello on disk a sequence of bytes Representing machine language, instructions and data for CPU (4) Load contents of file to main memory Each byte read and stored in some memory location In old machines, CPU had to be involved in this Now, use DMA to do this without involving CPU DMA: Direct Memory Access Let CPU know when ready (interrupt pin on CPU) (5) Address of first instruction of file loaded into PC (6) CPU begins executing code from this instruction (7) To display, CPU sends string data to monitor I/O device (8) When done, OS loads address of own instructions into PC 4

8 שאלות? 5 Random-Access Memory (RAM) Key features RAM is packaged as a chip. Basic storage unit is a cell (one bit per cell). Multiple RAM chips form a memory. Static RAM (SRAM) Each cell stores bit with a six-transistor circuit. Retains value indefinitely, as long as it is kept powered. Relatively insensitive to disturbances such as electrical noise. Faster and more expensive than DRAM. Dynamic RAM (DRAM) Each cell stores bit with a capacitor and transistor. Value must be refreshed every - ns. Sensitive to disturbances. Slower and cheaper than SRAM. 6

9 SRAM vs DRAM Summary Transistors. Access per bit time Persist? Sensitive? Cost Applications SRAM 6 X Yes No x cache memories DRAM X No Yes X Main memories, frame buffers 7 Conventional DRAM Organization d x w DRAM: dw total bits organized as d supercells of size w bits 6 x 8 DRAM chip cols 2 3 (to CPU) memory controller 2 bits / addr 8 bits / data rows 2 3 supercell (2,) internal row buffer 8

10 Reading DRAM Supercell (2,) Step (a): Row access strobe (RAS) selects row 2. Step (b): Row 2 copied from DRAM array to row buffer. 6 x 8 DRAM chip memory controller RAS = 2 2 / addr rows 2 cols / data 3 internal row buffer 9 Reading DRAM Supercell (2,) Step 2(a): Column access strobe (CAS) selects column. Step 2(b): Supercell (2,) copied from buffer to data lines, and eventually back to the CPU. 6 x 8 DRAM chip To CPU memory controller CAS = 2 / addr rows 2 cols 2 3 supercell (2,) 8 / data 3 supercell (2,) internal row buffer internal buffer 2

11 Memory Modules addr (row = i, col = j) : supercell (i,j) DRAM DRAM 7 64 MB memory module consisting of eight 8Mx8 DRAMs bits bits bits 4-47 bits bits 24-3 bits 6-23 bits 8-5 bits bit doubleword at main memory address A Memory controller 64-bit doubleword 2 Enhanced DRAMs Fast page mode DRAM (FPM DRAM) Access contents of row with [RAS, CAS, CAS, CAS, CAS] Instead of [(RAS,CAS), (RAS,CAS), (RAS,CAS), (RAS,CAS)]. Extended data out DRAM (EDO DRAM) Enhanced FPM DRAM with more closely spaced CAS signals. Synchronous DRAM (SDRAM) Driven with rising clock edge instead of asynchronous control signals. Double data-rate synchronous DRAM (DDR SDRAM) Enhancement of SDRAM that uses both clock edges as control signals. Video RAM (VRAM) Like FPM DRAM, but output is produced by shifting row buffer Dual ported (allows concurrent reads and writes) 22

12 Nonvolatile Memories DRAM and SRAM are volatile memories Lose information if powered off. Nonvolatile memories retain value even if powered off. Generic name is read-only memory (ROM). Misleading because some ROMs can be read and modified. Types of ROMs Programmable ROM (PROM) Eraseable programmable ROM (EPROM) Electrically eraseable PROM (EEPROM) Flash memory Firmware Program stored in a ROM Boot time code, BIOS (basic input/ouput system) graphics cards, disk controllers. 23 Typical Bus Structure Connecting CPU and Memory A bus is a collection of parallel wires that carry address, data, and control signals. Buses are typically shared by multiple devices. CPU chip register file ALU system bus memory bus bus interface I/O bridge main memory 24

13 Memory Read Transaction () CPU places address A on the memory bus. register file Load operation: movl A, %eax %eax ALU bus interface I/O bridge A main memory x A 25 Memory Read Transaction (2) Main memory reads A from the memory bus, retrieves word x, and places it on the bus. register file Load operation: movl A, %eax %eax ALU I/O bridge main memory x bus interface x A 26

14 Memory Read Transaction (3) CPU read word x from the bus and copies it into register %eax. %eax register file x AL U Load operation: movl A, %eax I/O bridge main memory bus interface x A 27 Memory Write Transaction () CPU places address A on bus. Main memory reads it and waits for the corresponding data word to arrive. %eax register file y AL U Store operation: movl %eax, A bus interface I/O bridge A main memory A 28

15 Memory Write Transaction (2) CPU places data word y on the bus. %eax register file y AL U Store operation: movl %eax, A bus interface I/O bridge y main memory A 29 Memory Write Transaction (3) Main memory read data word y from the bus and stores it at address A. %eax register file y AL U Store operation: movl %eax, A I/O bridge main memory bus interface y A 3

16 Disk Geometry Disks consist of platters, each with two surfaces. Each surface consists of concentric rings called tracks. Each track consists of sectors separated by gaps. tracks surface track k gaps spindl e sectors 3 Disk Geometry (Multiple-Platter View) Aligned tracks form a cylinder. cylinder k surface surface surface 2 surface 3 surface 4 surface 5 platter platter platter 2 spindle 32

17 Disk Capacity Capacity: maximum number of bits that can be stored. Vendors express capacity in units of gigabytes (GB), where GB = ^9. Capacity is determined by these technology factors: Recording density (bits/in): number of bits that can be squeezed into a inch segment of a track. Track density (tracks/in): number of tracks that can be squeezed into a inch radial segment. Areal density (bits/in2): product of recording and track density. Modern disks partition tracks into disjoint subsets called recording zones Each track in a zone has the same number of sectors, determined by the circumference of innermost track. Each zone has a different number of sectors/track 33 Computing Disk Capacity Capacity = (# bytes/sector) x (avg. # sectors/track) x (# tracks/surface) x (# surfaces/platter) x (# platters/disk) Example: 52 bytes/sector 3 sectors/track (on average) 2, tracks/surface 2 surfaces/platter 5 platters/disk Capacity = 52 x 3 x 2 x 2 x 5 = 3,72,, = 3.72 GB 34

18 Disk Operation (Single-Platter View) The disk surface spins at a fixed rotational rate The read/write head is attached to the end of the arm and flies over the disk surface on a thin cushion of air. spindl e spindl e spindl e By moving radially, the arm can position the read/write head over any track. 35 Disk Operation (Multi-Platter View) read/write heads move in unison from cylinder to cylinder arm spindle 36

19 Disk Access Time Average time to access some target sector approximated by : Taccess = Tavg seek + Tavg rotation + Tavg transfer Seek time (Tavg seek) Time to position heads over cylinder containing target sector. Typical Tavg seek = 9 ms Rotational latency (Tavg rotation) Time waiting for first bit of target sector to pass under r/w head. Tavg rotation = /2 x /RPMs x 6 sec/ min Transfer time (Tavg transfer) Time to read the bits in the target sector. Tavg transfer = /RPM x /(avg # sectors/track) x 6 secs/ min. 37 Disk Access Time Example Given: Rotational rate = 7,2 RPM Average seek time = 9 ms. Avg # sectors/track = 4. Derived: Tavg rotation = /2 x (6 secs/72 RPM) x ms/sec = 4 ms. Tavg transfer = 6/72 RPM x /4 secs/track x ms/sec =.2 ms Taccess = 9 ms + 4 ms +.2 ms Important points: Access time dominated by seek time and rotational latency. First bit in a sector is the most expensive, the rest are free. SRAM access time is about 4 ns/doubleword, DRAM about 6 ns Disk is about 4, times slower than SRAM, 2,5 times slower then DRAM. 38

20 Logical Disk Blocks Modern disks present a simpler abstract view of the complex sector geometry: The set of available sectors is modeled as a sequence of b-sized logical blocks (,, 2,...) Mapping between logical blocks and actual (physical) sectors Maintained by hardware/firmware device called disk controller. Converts requests for logical blocks into (surface,track,sector) triples. Allows controller to set aside spare cylinders for each zone. Accounts for the difference in formatted capacity and maximum capacity. 39 I/O Bus CPU chip register file AL U system bus memory bus bus interface I/O bridge main memory USB controller graphics adapter I/O bus disk controller Expansion slots for other devices such as network adapters. mouse keyboard monitor disk 4

21 Reading a Disk Sector () CPU chip register file AL U CPU initiates a disk read by writing a command, logical block number, and destination memory address to a port (address) associated with disk controller. bus interface main memory I/O bus USB controller graphics adapter disk controller mouse keyboard monitor disk 4 Reading a Disk Sector (2) CPU chip register file AL U Disk controller reads the sector and performs a direct memory access (DMA) transfer into main memory. bus interface main memory I/O bus USB controller graphics adapter disk controller mouse keyboard monitor disk 42

22 Reading a Disk Sector (3) CPU chip register file AL U When the DMA transfer completes, the disk controller notifies the CPU with an interrupt (i.e., asserts a special interrupt pin on the CPU) bus interface main memory I/O bus USB controller graphics adapter disk controller mouse keyboard monitor disk 43 Storage Trends SRAM metric :98 $/MB 9,2 2, access (ns) metric :98 DRAM $/MB 8, , access (ns) typical size(mb) , metric :98 Disk $/MB , access (ms) typical size(mb) 6, 9, 9, (Culled from back issues of Byte and PC Magazine) 44

23 ns CPU Clock Rates :98 processor Pent P-III clock rate(mhz) cycle time(ns), The CPU-Memory Gap The increasing gap between DRAM, disk, and CPU speeds.,,,,,,,,, year Disk seek time DRAM access time SRAM access time CPU cycle time 46

24 שאלות? 47 Locality Principle of Locality: Programs tend to reuse data and instructions near those they have used recently, or that were recently referenced themselves. Temporal locality: Recently referenced items are likely to be referenced in the near future. Spatial locality: Items with nearby addresses tend to be referenced close together in time. Locality Example: Data Reference array elements in succession (stride- reference pattern): Reference sum each iteration: Temporal locality Instructions Reference instructions in sequence: Spatial locality Cycle through loop repeatedly: Temporal locality Spatial locality sum = ; for (i = ; i < n; i++) sum += a[i]; return sum; 48

25 Locality Example Claim: Being able to look at code and get a qualitative sense of its locality is a key skill for a professional programmer. Question: Does this function have good locality? int sumarrayrows(int a[m][n]) { int i, j, sum = ; for (i = ; i < M; i++) for (j = ; j < N; j++) sum += a[i][j]; return sum 49 Locality Example Question: Does this function have good locality? int sumarraycols(int a[m][n]) { int i, j, sum = ; for (j = ; j < N; j++) for (i = ; i < M; i++) sum += a[i][j]; return sum 5

26 Locality Example Question: Can you permute the loops so that the function scans the 3-d array a[] with a stride- reference pattern (and thus has good spatial locality)? int sumarray3d(int a[m][n][n]) { int i, j, k, sum = ; for (i = ; i < M; i++) for (j = ; j < N; j++) for (k = ; k < N; k++) sum += a[k][i][j]; return sum 5 Memory Hierarchies Some fundamental and enduring properties of hardware and software: Fast storage technologies cost more per byte and have less capacity. The gap between CPU and main memory speed is widening. Well-written programs tend to exhibit good locality. These fundamental properties complement each other beautifully. They suggest an approach for organizing memory and storage systems known as a memory hierarchy. 52

27 An Example Memory Hierarchy Smaller, faster, and costlier (per byte) storage devices L2: L: L: registers on-chip L cache (SRAM) off-chip L2 cache (SRAM) CPU registers hold words retrieved from L cache. L cache holds cache lines retrieved from the L2 cache memory. L2 cache holds cache lines retrieved from main memory. Larger, slower, and cheaper (per byte) storage devices L4: L3: main memory (DRAM) local secondary storage (local disks) Main memory holds disk blocks retrieved from local disks. Local disks hold files retrieved from disks on remote network servers. L5: remote secondary storage (distributed file systems, Web servers) 53 Caches Cache: A smaller, faster storage device that acts as a staging area for a subset of the data in a larger, slower device. Fundamental idea of a memory hierarchy: For each k, the faster, smaller device at level k serves as a cache for the larger, slower device at level k+. Why do memory hierarchies work? Programs tend to access the data at level k more often than they access the data at level k+. Thus, the storage at level k+ can be slower, and thus larger and cheaper per bit. Net effect: A large pool of memory that costs as much as the cheap storage near the bottom, but that serves data to programs at the rate of the fast storage near the top. 54

28 Caching in a Memory Hierarchy Level k: Smaller, faster, more expensive device at level k caches a subset of the blocks from level k+ 4 Data is copied between levels in block-sized transfer units Level k+: Larger, slower, cheaper storage device at level k+ is partitioned into blocks. 55 General Caching Concepts Level k+: Level k: 4 2 Request * * Request * Program needs object d, which is stored in some block b. Cache hit Program finds b in the cache at level k. E.g., block 4. Cache miss b is not at level k, so level k cache must fetch it from level k+. E.g., block 2. If level k cache is full, then some current block must be replaced (evicted). Which one is the victim? Placement policy: where can the new block go? E.g., b mod 4 Replacement policy: which block should be evicted? E.g., LRU 56

29 General Caching Concepts Types of cache misses: Cold (compulsary) miss Cold misses occur because the cache is empty. Conflict miss Most caches limit blocks at level k+ to a small subset (sometimes a singleton) of the block positions at level k. E.g. Block i at level k+ must be placed in block (i mod 4) at level k+. Conflict misses occur when the level k cache is large enough, but multiple data objects all map to the same level k block. E.g. Referencing blocks, 8,, 8,, 8,... would miss every time. Capacity miss Occurs when the set of active cache blocks (working set) is larger than the cache. 57 Examples of Caching in the Hierarchy Cache Type What Cached Where Cached Latency (cycles) Managed By Registers 4-byte word CPU registers Compiler TLB Address translations On-Chip TLB Hardware L cache 32-byte block On-Chip L Hardware L2 cache 32-byte block Off-Chip L2 Hardware Virtual Memory 4-KB page Main memory Hardware + OS Buffer cache Parts of files Main memory OS Network buffer cache Parts of files Local disk,, AFS/NFS client Browser cache Web pages Local disk,, Web browser Web cache Web pages Remote server disks,,, Web proxy server 58

30 Cache Memories Cache memories are small, fast SRAM-based memories managed automatically in hardware. Hold frequently accessed blocks of main memory CPU looks first for data in L, then in L2, then in main memory. Typical bus structure: CPU chip register file L cache AL U cache bus system bus memory bus L2 cache bus interface I/O bridge main memor y 59 Inserting an L Cache Between the CPU and Main Memory The transfer unit between the CPU register file and the cache is a 4-byte block. line line The transfer unit between the cache and main memory is a 4-word block (6 bytes). block block 2 block 3 a b c d... p q r s... w x y z... The tiny, very fast CPU register file has room for four 4-byte words. The small fast L cache has room for two 4-word blocks. The big slow main memory has room for many 4-word blocks. 6

31 General Organization of a Cache Memory Cache is an array of sets. valid bit per line t tag bits per line B = 2 b bytes per cache block Each set contains one or more lines. Each line holds a block of data. set : valid valid tag tag B B E lines per set valid tag B S = 2 s sets set : valid tag B valid tag B set S-: valid tag B Cache size: C = B x E x S data bytes 6 Addressing Caches Address A: t bits s bits b bits set : v v tag tag B B m- <tag> <set index> <block offset> set : set S-: v v v v tag tag tag tag B B B B The word at address A is in the cache if the tag bits in one of the <valid> lines in set <set index> match <tag>. The word contents begin at offset <block offset> bytes from the beginning of the block. 62

32 Direct-Mapped Cache Simplest kind of cache Characterized by exactly one line per set. set : valid tag cache block E= lines per set set : valid tag cache block set S-: valid tag cache block 63 Accessing Direct-Mapped Caches Set selection Use the set index bits to determine the set of interest. set : valid tag cache block selected set set : valid tag cache block t bits s bits b bits set S-: valid tag cache block m- tag set index block offset 64

33 Accessing Direct-Mapped Caches Line matching and word selection Line matching: Find a valid line in the selected set with a matching tag Word selection: Then extract the word =? () The valid bit must be set selected set (i): w w w 2 w 3 (2) The tag bits in the cache line must match the tag bits in the address m- =? t bits s bits b bits i tag set index block offset (3) If () and (2), then cache hit, and block offset selects starting byte. 65 Direct-Mapped Cache Simulation t= s=2 b= x xx x M=6 byte addresses, B=2 bytes/block, S=4 sets, E= entry/set Address trace (reads): [ 2 ], [ 2 ], 3 [ 2 ], 8 [ 2 ], [ 2 ] () [ 2 ] (miss) v tag data m[] m[] 66

34 Direct-Mapped Cache Simulation t= s=2 b= x xx x M=6 byte addresses, B=2 bytes/block, S=4 sets, E= entry/set Address trace (reads): [ 2 ], [ 2 ], 3 [ 2 ], 8 [ 2 ], [ 2 ] () [ 2 ] (miss) v tag data m[] M[-] m[] 67 Direct-Mapped Cache Simulation t= s=2 b= x xx x M=6 byte addresses, B=2 bytes/block, S=4 sets, E= entry/set Address trace (reads): [ 2 ], [ 2 ], 3 [ 2 ], 8 [ 2 ], [ 2 ] (2) [ 2 ] (hit!) v tag data m[] M[-] m[] 68

35 Direct-Mapped Cache Simulation t= s=2 b= x xx x M=6 byte addresses, B=2 bytes/block, S=4 sets, E= entry/set Address trace (reads): [ 2 ], [ 2 ], 3 [ 2 ], 8 [ 2 ], [ 2 ] () [ 2 ] (miss) v tag data m[] M[-] m[] (3) 3 [ 2 ] (miss) v tag data m[] M[-] m[] m[3] M[2-3] m[2] 69 Direct-Mapped Cache Simulation t= s=2 b= x xx x M=6 byte addresses, B=2 bytes/block, S=4 sets, E= entry/set Address trace (reads): [ 2 ], [ 2 ], 3 [ 2 ], 8 [ 2 ], [ 2 ] () [ 2 ] (miss) v tag data m[] M[-] m[] (3) 3 [ 2 ] (miss) v tag data m[] M[-] m[] m[3] M[2-3] m[2] (4) v tag data m[9] M[8-9] m[8] 8 [ 2 ] (miss) M[2-3] 7

36 Direct-Mapped Cache Simulation t= s=2 b= x xx x M=6 byte addresses, B=2 bytes/block, S=4 sets, E= entry/set Address trace (reads): [ 2 ], [ 2 ], 3 [ 2 ], 8 [ 2 ], [ 2 ] () [ 2 ] (miss) v tag data m[] M[-] m[] (3) 3 [ 2 ] (miss) v tag data m[] M[-] m[] m[3] M[2-3] m[2] (4) v tag data m[9] M[8-9] m[8] 8 [ 2 ] (miss) M[2-3] (5) [ 2 ] (miss) v tag data m[] M[-] m[] m[3] M[2-3] m[2] 7 Why Use Middle Bits as Index? 4-line Cache High-Order Bit Indexing Middle-Order Bit Indexing High-Order Bit Indexing Adjacent memory lines would map to same cache entry Poor use of spatial locality Middle-Order Bit Indexing Consecutive memory lines map to different cache lines Can hold C-byte region of address space in cache at one time 72

37 Set Associative Caches Characterized by more than one line per set set : valid tag cache block valid tag cache block E=2 lines per set set : valid tag cache block valid tag cache block set S-: valid tag cache block valid tag cache block 73 Accessing Set Associative Caches Set selection identical to direct-mapped cache set : valid valid tag tag cache block cache block Selected set set : valid valid tag tag cache block cache block t bits s bits b bits set S-: valid valid tag tag cache block cache block m- tag set index block offset 74

38 Accessing Set Associative Caches Line matching and word selection must compare the tag in each valid line in the selected set. =? () The valid bit must be set selected set (i): w w w 2 w 3 (2) The tag bits in one of the cache lines must match the tag bits in the address m- =? t bits s bits b bits i tag set index block offset (3) If () and (2), then cache hit, and block offset selects starting byte. 75 Multi-Level Caches Options: separate data and instruction caches, or a unified cache Processor Regs L d- cache L i-cache Unified L2 Cache Memory disk size: speed: $/Mbyte: line size: 2 B 3 ns 8 B 8-64 KB 3 ns 32 B -4MB SRAM 6 ns $/MB 32 B 28 MB DRAM 6 ns $.5/MB 8 KB 3 GB 8 ms $.5/MB larger, slower, cheaper 76

39 Intel Pentium Cache Hierarchy Regs. L Data cycle latency 6 KB 4-way assoc Write-through 32B lines L Instruction 6 KB, 4-way 32B lines L2 Unified 28KB--2 MB 4-way assoc Write-back Write allocate 32B lines Main Memory Up to 4GB Processor Chip 77 Cache Performance Metrics Miss Rate Fraction (percent) of memory references not found in cache Typical numbers (misses/references): 3-% for L can be quite small (e.g., < %) for L2, depending on size, etc. Hit Time Time to deliver a line in the cache to the processor (includes time to determine whether the line is in the cache) Typical numbers: clock cycle for L 3-8 clock cycles for L2 Miss Penalty Additional time required because of a miss Typically 25- cycles for main memory 78

40 Writing Cache Friendly Code Repeated references to variables are good (temporal locality) Stride- reference patterns are good (spatial locality) Examples: cold cache, 4-byte words, 4-word cache blocks int sumarrayrows(int a[m][n]) { int i, j, sum = ; int sumarraycols(int a[m][n]) { int i, j, sum = ; for (i = ; i < M; i++) for (j = ; j < N; j++) sum += a[i][j]; return sum; for (j = ; j < N; j++) for (i = ; i < M; i++) sum += a[i][j]; return sum; Miss rate = /4 = 25% Miss rate = % 79 The Memory Mountain Read throughput (read bandwidth) Number of bytes read from memory per second (MB/s) Memory mountain Measured read throughput as a function of spatial and temporal locality. Compact way to characterize memory system performance. 8

41 Memory Mountain Test Function /* The test function */ void test(int elems, int stride) { int i, result = ; volatile int sink; for (i = ; i < elems; i += stride) result += data[i]; sink = result; /* So compiler doesn't optimize away the loop */ /* Run test(elems, stride) and return read throughput (MB/s) */ double run(int size, int stride, double Mhz) { double cycles; int elems = size / sizeof(int); test(elems, stride); /* warm up the cache */ cycles = fcyc2(test, elems, stride, ); /* call test(elems,stride) */ return (size / stride) / (cycles / Mhz); /* convert cycles to MB/s */ 8 Memory Mountain Main Routine /* mountain.c - Generate the memory mountain. */ #define MINBYTES ( << ) /* Working set size ranges from KB */ #define MAXBYTES ( << 23) /*... up to 8 MB */ #define MAXSTRIDE 6 /* Strides range from to 6 */ #define MAXELEMS MAXBYTES/sizeof(int) int data[maxelems]; /* The array we'll be traversing */ int main() { int size; /* Working set size (in bytes) */ int stride; /* Stride (in array elements) */ double Mhz; /* Clock frequency */ init_data(data, MAXELEMS); /* Initialize each element in data to */ Mhz = mhz(); /* Estimate the clock frequency */ for (size = MAXBYTES; size >= MINBYTES; size >>= ) { for (stride = ; stride <= MAXSTRIDE; stride++) printf("%.f\t", run(size, stride, Mhz)); printf("\n"); exit(); 82

42 8m 4m 2m 24k 52k 256k 28k 64k 32k 6k 8k 4k 2k k read througput (MB/s) s5 8m s3 2m s 52k s9 28k s7 32k s5 8k s3 2k s read throughput (MB/s) The Memory Mountain 2 8 L Pentium III Xeon 55 MHz 6 KB on-chip L d-cache 6 KB on-chip L i-cache 52 KB off-chip unified L2 cache 6 Slopes of Spatial Locality 4 2 xe L2 Ridges of Temporal Locality mem stride (words) working set size (bytes) 83 Ridges of Temporal Locality Slice through the memory mountain with stride= illuminates read throughputs of different caches and memory 2 main memory region L2 cache region L cache region working set size (bytes) 84

43 read throughput (MB/s) A Slope of Spatial Locality Slice through memory mountain with size=256kb shows cache block size one access per cache line 3 2 s s2 s3 s4 s5 s6 s7 s8 s9 s s s2 s3 s4 s5 s6 stride (words) 85 Matrix Multiplication Example Major Cache Effects to Consider Total cache size Exploit temporal locality and keep the working set small (e.g., by using blocking) Block size Exploit spatial locality Description: Multiply N x N matrices O(N3) total operations Accesses N reads per source element N values summed per destination but may be able to hold in register /* ijk */ Variable sum for (i=; i<n; i++) { held in register for (j=; j<n; j++) { sum =.; for (k=; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum; 86

44 Miss Rate Analysis for Matrix Multiply Assume: Line size = 32B (big enough for 4 64-bit words) Matrix dimension (N) is very large Approximate /N as. Cache is not even big enough to hold multiple rows Analysis Method: Look at access pattern of inner loop k j j i k i A B C 87 Layout of C Arrays in Memory C arrays allocated in row-major order each row in contiguous memory locations Stepping through columns in one row: for (i = ; i < N; i++) sum += a[][i]; accesses successive elements if block size (B) > 4 bytes, exploit spatial locality compulsory miss rate = 4 bytes / B Stepping through rows in one column: for (i = ; i < n; i++) sum += a[i][]; accesses distant elements no spatial locality! compulsory miss rate = (i.e. %) 88

45 Matrix Multiplication (ijk) /* ijk */ for (i=; i<n; i++) { for (j=; j<n; j++) { sum =.; for (k=; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum; Inner loop: (i,*) (*,j) (i,j) A B C Row-wise Columnwise Fixed Misses per Inner Loop Iteration: A B C Matrix Multiplication (jik) /* jik */ for (j=; j<n; j++) { for (i=; i<n; i++) { sum =.; for (k=; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum Inner loop: (*,j) (i,j) (i,*) A B C Misses per Inner Loop Iteration: Row-wise Columnwise Fixed A B C

46 Matrix Multiplication (kij) /* kij */ for (k=; k<n; k++) { for (i=; i<n; i++) { r = a[i][k]; for (j=; j<n; j++) c[i][j] += r * b[k][j]; Inner loop: (i,k) (k,*) A B C (i,*) Fixed Row-wise Row-wise Misses per Inner Loop Iteration: A B C Matrix Multiplication (ikj) /* ikj */ for (i=; i<n; i++) { for (k=; k<n; k++) { r = a[i][k]; for (j=; j<n; j++) c[i][j] += r * b[k][j]; Inner loop: (i,k) (k,*) A B C (i,*) Fixed Row-wise Row-wise Misses per Inner Loop Iteration: A B C

47 Matrix Multiplication (jki) /* jki */ for (j=; j<n; j++) { for (k=; k<n; k++) { r = b[k][j]; for (i=; i<n; i++) c[i][j] += a[i][k] * r; Inner loop: (*,k) (*,j) (k,j) A B C Misses per Inner Loop Iteration: Column - wise Fixed Columnwise A B C Matrix Multiplication (kji) /* kji */ for (k=; k<n; k++) { for (j=; j<n; j++) { r = b[k][j]; for (i=; i<n; i++) c[i][j] += a[i][k] * r; Inner loop: (*,k) (*,j) (k,j) A B C Columnwise Fixed Columnwise Misses per Inner Loop Iteration: A B C... 94

48 Cycles/iteration Summary of Matrix Multiplication ijk (& jik): 2 loads, stores misses/iter =.25 kij (& ikj): 2 loads, store misses/iter =.5 jki (& kji): 2 loads, store misses/iter = 2. for (i=; i<n; i++) { for (j=; j<n; j++) { sum =.; for (k=; k<n; k++) sum += a[i][k] * b[k][j]; c[i][j] = sum; for (k=; k<n; k++) { for (i=; i<n; i++) { r = a[i][k]; for (j=; j<n; j++) c[i][j] += r * b[k][j]; for (j=; j<n; j++) { for (k=; k<n; k++) { r = b[k][j]; for (i=; i<n; i++) c[i][j] += a[i][k] * r; 95 Pentium Matrix Multiply Performance kji jki kij ikj jik ijk Miss rates are helpful but not perfect predictors. Code scheduling matters, too Array size (n) 96

49 Improving Temporal Locality by Blocking Example: Blocked matrix multiplication block (in this context) does not mean cache block. Instead, it mean a sub-block within the matrix. Example: N = 8; sub-block size = 4 A A 2 B B 2 C C 2 A 2 A 22 X B 2 B 22 = C 2 C 22 Key idea: Sub-blocks (i.e., A xy ) can be treated just like scalars. C = A B + A 2 B 2 C 2 = A B 2 + A 2 B 22 C 2 = A 2 B + A 22 B 2 C 22 = A 2 B 2 + A 22 B Blocked Matrix Multiply (bijk) for (jj=; jj<n; jj+=bsize) { for (i=; i<n; i++) for (j=jj; j < min(jj+bsize,n); j++) c[i][j] =.; for (kk=; kk<n; kk+=bsize) { for (i=; i<n; i++) { for (j=jj; j < min(jj+bsize,n); j++) { sum =. for (k=kk; k < min(kk+bsize,n); k++) { sum += a[i][k] * b[k][j]; c[i][j] += sum; 98

50 Cycles/iteration Blocked Matrix Multiply Analysis Innermost loop pair multiplies a X bsize sliver of A by a bsize X bsize block of B and accumulates into X bsize sliver of C Loop over i steps through n row slivers of A & C, using same B Innermost Loop Pair for (i=; i<n; i++) { for (j=jj; j < min(jj+bsize,n); j++) { sum =. for (k=kk; k < min(kk+bsize,n); k++) { sum += a[i][k] * b[k][j]; kk jj c[i][j] += sum; i kk A B C jj i row sliver accessed bsize times block reused n times in succession Update successive elements of sliver 99 Pentium Blocked Matrix Multiply Performance Blocking (bijk and bikj) improves performance by a factor of two over unblocked versions (ijk and jik) relatively insensitive to array size kji jki kij ikj jik ijk bijk (bsize = 25) bikj (bsize = 25) Array size (n)

51 Concluding Observations Programmer can optimize for cache performance How data structures are organized How data are accessed Nested loop structure Blocking is a general technique All systems favor cache friendly code Getting absolute optimum performance is very platform specific Cache sizes, line sizes, associativities, etc. Can get most of the advantage with generic code Keep working set reasonably small (temporal locality) Use small strides (spatial locality) שאלות? 2