Memory and Disk Systems

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1 COMP 212 Computer Organization & Architecture Re-Cap of Lecture #3 Cache system is a compromise between COMP 212 Fall 2008 Lecture 4 Memory and Disk Systems More memory system capacity Faster access speed Cost Memory System is Hierarchical Speed:» Registers > Cache > RAM > Hard Disk > Optical Storages Cost: other way around Comp 212 Computer Org & Arch 1 Z. Li, 2008 Comp 212 Computer Org & Arch 2 Z. Li, 2008 Re-Cap of Lecture #3 Addressing If partition mem address into blocks, then higher bits correspond to block address, lower bits correspond to word locations within the block Example,» 8 bit address space, give us 2 8 = 256 word address» If we group 4 word into a block, then we have 2 6 = 64 blocks.» Word address: (69h)-> block address (1Bh)» Conversion between hex and binary: group binary in 4 bits blocks, each 4 bit block correspond to a hex number Direct Cache Mapping Re-Cap of Lecture #3 each mem block has a fixed cache line location, and each cache line is mapped to fixed locations in memory, e.g. Tag s-r Line or Slot r Word w We have 2 14 cache lines, but 2 22 mem blocks. Cache hit/miss? Check Tag, if mem request tag does not matches that in cache line, a miss. Pros/Cons: Simple to implement, but not flexible. Comp 212 Computer Org & Arch 3 Z. Li, 2008 Comp 212 Computer Org & Arch 4 Z. Li, 2008

2 Associative Cache Mapping Re-Cap of Lecture #3 each mem block can reside in any cache line, e.g. Tag 22 bit We have 2 14 cache lines, but 2 22 mem blocks. Cache hit/miss? Check Tag with all cache line tags, if requested mem block tag does not exists, a miss. Pros/Cons: flexible, can support complex cache replacement Word 2 bit algorithms, but expensive to implement (comparing all cache lines tags) Re-Cap of Lecture #3 Set Associative Cache Mapping: A compromise between direct and associative mapping Cache line addressable by cache set Each cache set contains k cache lines, called k-way set associative cache. Mem address mapped to tag, cache set address, and word addr. Tag 9 bit Cache Set 13 bit Word 2 bit Comp 212 Computer Org & Arch 5 Z. Li, 2008 Comp 212 Computer Org & Arch 6 Z. Li, 2008 Cache Replacement algorithms When there s a cache miss, a new memory block is loaded into the cache, we need replace cache content Cache Performance (spill over from lec #3) If direct mapping, don t have a choice, the new block has a fixed location in cache If set associative mapping, need to choose which line in a set to replace In associative mapping, more choices, larger space to choose from. Typically hardware implemented, no CPU involvement. Comp 212 Computer Org & Arch 7 Z. Li, 2008 Comp 212 Computer Org & Arch 8 Z. Li, 2008

3 Replacement algorithms Algorithms used Least Recently used (LRU)» e.g. in 2 way set associative cache, which of the 2 block is lru? First in first out (FIFO) replace block that has been in cache longest Least frequently used replace block which has had fewest hits Write Policy Memory data consistency issue no free lunch theorem. When replace cache line, if cache data changed, before it is replaced, need to write back to corresponding memory location When IO modified memory word via DMA, cache word becomes invalid, need to reload into cache Multi-core CPU with its own cache: cache word invalid if changed by one of the CPU Random Generate a random number to determine which one to replace Comp 212 Computer Org & Arch 9 Z. Li, 2008 Comp 212 Computer Org & Arch 10 Z. Li, 2008 Write through All writes go to main memory as well as cache Multiple CPUs can monitor main memory traffic to keep local (to CPU) cache up to date Problem: Many writes to memory Lots of traffic on bus Write back Purpose is to minimize write operations on BUS When a cache line is updated, a bit is set to indicate that At the time of cache line replacement, only write to memory those lines updated. Average cache update is 15%, but for vector computing, 33%, matrix transposition, 50%. Write involves a line instead of a word, so only if a cache word gets written multiple times before replacement, can make it profitable Comp 212 Computer Org & Arch 11 Z. Li, 2008 Comp 212 Computer Org & Arch 12 Z. Li, 2008

Example Memory write is 32 bit, takes 30ns Cache line is 16 byes, 196bits Average word writes per replacement is 12 times How will write back save BUS time than write thru?

4 Example Memory write is 32 bit, takes 30ns Cache line is 16 byes, 196bits Average word writes per replacement is 12 times How will write back save BUS time than write thru? Solutions Write thru: 12 x 30 = 360ns / replacement cycle Write back: (196/32)x30 = 240ns / replacement cycle Cache Performance Cost per bits for a two level cache system C1: cost for cache per bit C2: cost of mem per bit S1: cache size S2: mem size What is the average cost per bit? C1* S1+ C2 * S2 S1+ S2 Comp 212 Computer Org & Arch 13 Z. Li, 2008 Comp 212 Computer Org & Arch 14 Z. Li, 2008 Cache Performance - Cost Cache Performance Access Consider the following 2 level system: Cache hit ratio is h, i.e, prob of a memory word access is in cache Time to access a word in L1 and L2 cache: T1, T2. What is the average word access time? Ts = h * T1+ (1 h) * ( T1+ T 2) T1 1 = Ts T 2 1+ (1 h) T1 We want T1/Ts to be close to 1.0 Comp 212 Computer Org & Arch 15 Z. Li, 2008 Comp 212 Computer Org & Arch 16 Z. Li, 2008

Cache access as function of hit ratio Hit ratio vs data access locality Different program has different access locality characteristics What is the cache size affecting the hit ratio?

Li, 2008 Cache System Performance: Re-Cap of Lecture #3 What are the cache replacement algorithms?» LRU, FIFO, LFU, Random What is the difference between write back and write thru?

5 Cache access as function of hit ratio Hit ratio vs data access locality Different program has different access locality characteristics What is the cache size affecting the hit ratio? If no locality, totally proportional to the S1/S2 ratio Comp 212 Computer Org & Arch 17 Z. Li, 2008 Comp 212 Computer Org & Arch 18 Z. Li, 2008 Cache System Performance: Re-Cap of Lecture #3 What are the cache replacement algorithms?» LRU, FIFO, LFU, Random What is the difference between write back and write thru? Memory and Disk System (mostly informational) When will write back be better than write thru? What is the cost per bit of a k-level cache system? What is the average access time for a k-level cache system? Comp 212 Computer Org & Arch 19 Z. Li, 2008 Comp 212 Computer Org & Arch 20 Z. Li, 2008

6 Semiconductor Memory Types RAM, ROM, EPROM, EEPROM FalshMem RAM RAM Prob the most important type for Computer Misnamed as all semiconductor memory is random access Support multiple read/write Volatile need refresh, provides temporary storage Can be Static or Dynamic, will discuss in more detail later Comp 212 Computer Org & Arch 21 Z. Li, 2008 Comp 212 Computer Org & Arch 22 Z. Li, 2008 Memory Cell Operation (conceptually) Dynamic RAM Structure Simple, bits stored as charge in capacitors, Uses only 1 transistor and 1 capacitor Charges leak, need refreshing even when Mem cell need to be selected by address line When write, the state of mem cell is changed When read, just sensing. powered Recharge cycles make it slow Comp 212 Computer Org & Arch 23 Z. Li, 2008 Comp 212 Computer Org & Arch 24 Z. Li, 2008

7 Transistor Operation When there s no voltage on address line, the transistor is disconnected Use addr line to switch on/off DRAM Operation Requires some Physics background to understand Will explain intuitively, don t panic, Address line active when bit read or written Addr line controls the current flow on the line If no voltage on addr line, bit line and capacitor not connected Write Voltage to bit line» High for 1 low for 0 Then signal address line» Transfers charge to capacitor Comp 212 Computer Org & Arch 25 Z. Li, 2008 Comp 212 Computer Org & Arch 26 Z. Li, 2008 DRAM Operation Read Address line selected» transistor turns on Charge from capacitor fed via bit line to sense amplifier» Compares with reference value to determine 0 or 1 Capacitor charge must be restored Static RAM Structure Bits stored as voltages on bit line B and B complement S-R latch, will cover later in digital logic part. No charges to leak, no refreshing needed when powered More complex construction 6 transistors to implement Comp 212 Computer Org & Arch 27 Z. Li, 2008 Comp 212 Computer Org & Arch 28 Z. Li, 2008

8 Static RAM More Complex Implementations Requires more transistors More expensive Does not need refresh circuits, so Operates faster Can be used as cache Transistor arrangement gives stable logic state Address line transistors T 5 T 6 are switches State 1 C 1 high, C 2 low T 1 T 4 off, T 2 T 3 on State 0 C 2 high, C 1 low T 2 T 3 off, T 1 T 4 on Write apply value to B & compliment to B Read value is on line B Static RAM Operation Comp 212 Computer Org & Arch 29 Z. Li, 2008 Comp 212 Computer Org & Arch 30 Z. Li, 2008 SRAM & DRAM Summary Both volatile Power needed to preserve data Dynamic cell Simpler to build, less expensive, smaller and denser : more bits per silicon area Needs refresh circuits Used as Main Mem. Static Read Only Memory (ROM) Permanent storage Nonvolatile, does not require power Typically used to store Microprogramming (see later) Library subroutines Systems programs (BIOS) Function tables Faster More expensive Used as Cache Comp 212 Computer Org & Arch 31 Z. Li, 2008 Comp 212 Computer Org & Arch 32 Z. Li, 2008

9 Types of ROM Types of ROM ROM Customer built, Hardwired, very expensive for small runs PROM - Programmable (once) Needs special equipment to program» Erase whole memory electrically Read mostly Erasable Programmable (EPROM) - optical» Erased by UV, very slow, takes 20 min, e.g. Electrically Erasable (EEPROM)» Takes much longer to write than read, but faster than EPROM» More expensive than EPROM Flash memory: in between EPROM & EEPROM in cost» Erase electrically,» Can only erase blocks of mem» Less expensive than EEPROM. Comp 212 Computer Org & Arch 33 Z. Li, 2008 Comp 212 Computer Org & Arch 34 Z. Li, 2008 Organisation of DRAM We can have memory chips of 2 W word and k bits for each word, for a total of k*2 W bits. Organization of Memory E.g. 4M word of 4 bits A 16Mbit chip can be organised as a 2048 x 2048 x 4bit array, k=4, W=22. Address by column and row selection, 11 each Reduces number of address pins» Multiplex row address and column address» 11 pins to column/row address (2 11 =2048), Comp 212 Computer Org & Arch 35 Z. Li, 2008 Comp 212 Computer Org & Arch 36 Z. Li, 2008

Typical 16 Mb DRAM (4M x 4bits) Logic row/col selection 16Mbit (4M x 4bit) Packaging A0~A10: address line RAS: row selection Address lines Data lines CAS: col selection WE: write enable OE: output

Li, 2008 Advanced DRAM Organization Synch RAM DRAM is async, mem access need to wait SRAM sync with system clock RAM Bus Not using RAS, CAS, R/W enable and CE typical in DRAM Request via a

10 Typical 16 Mb DRAM (4M x 4bits) Logic row/col selection 16Mbit (4M x 4bit) Packaging A0~A10: address line RAS: row selection Address lines Data lines CAS: col selection WE: write enable OE: output enable Vcc: power supply Vss: ground Refresh Comp 212 Computer Org & Arch 37 Z. Li, 2008 CE: chip enable Comp 212 Computer Org & Arch 38 Z. Li, 2008 Advanced DRAM Organization Synch RAM DRAM is async, mem access need to wait SRAM sync with system clock RAM Bus Not using RAS, CAS, R/W enable and CE typical in DRAM Request via a asynchronous block request Communicated over a Bus Synchronous DRAM (SDRAM) Access is synchronized with an external clock Address is presented to RAM RAM finds data (CPU waits in conventional DRAM) Since SDRAM moves data in time with system clock, CPU knows when data will be ready CPU does not have to wait, it can do something else Burst mode allows SDRAM to set up stream of data and fire it out in block DDR-SDRAM sends data twice per clock cycle Comp 212 Computer Org & Arch 39 Z. Li, 2008 Comp 212 Computer Org & Arch 40 Z. Li, 2008

IBM 64Mb Sync DRAM Block Diagram RAMBUS Diagram 8-bit Data lines Address lines Asynchronous block protocol 480ns access time 16 data lines, address up to 320

Li, 2008 RAMBUS Adopted by Intel for Pentium & Itanium Main competitor to Sync DRAM Vertical package all pins on one side DDR SDRAM SDRAM can only send data

11 IBM 64Mb Sync DRAM Block Diagram RAMBUS Diagram 8-bit Data lines Address lines Asynchronous block protocol 480ns access time 16 data lines, address up to 320 DRAM chips. Comp 212 Computer Org & Arch 41 Z. Li, 2008 Comp 212 Computer Org & Arch 42 Z. Li, 2008 RAMBUS Adopted by Intel for Pentium & Itanium Main competitor to Sync DRAM Vertical package all pins on one side DDR SDRAM SDRAM can only send data once per clock Double-data-rate (DDR) SDRAM can send data twice per clock cycle Asynchronous block protocol 480ns access time Then 1.6 Gbps Comp 212 Computer Org & Arch 43 Z. Li, 2008 Comp 212 Computer Org & Arch 44 Z. Li, 2008

12 Mitsubishi Cache DRAM Summary of RAMs Integrates small Static RAM cache (16 kb) onto generic DRAM chip Used as true cache 64-bit lines Effective for ordinary random access To support serial access of block of data E.g. refresh bit-mapped screen» Cache DRAM can pre-fetch data from DRAM into SRAM buffer Dynamic RAM Analog technology, use capacitor voltage to indicate bit Need refresh, slow Easier to implement, denser solution Static RAM Use transistor state to store bit, need more transistors per bit No need to refresh, fast More expensive» Subsequent accesses solely to SRAM Comp 212 Computer Org & Arch 45 Z. Li, 2008 Comp 212 Computer Org & Arch 46 Z. Li, 2008 Summary of RAMs DRAM organization DRAM:» Widely used» 2D bit array, addressed by row and column address lines» Have refresh circuits External Memory (Disk) System Advanced DRAM organization» Sync DRAM: sync with system clock operation, no wait» RAM BUS: block transfer protocol, bus implementation.» DDR Sync RAM, aka, DDR SRAM, double the data access rate of SRAM» Cache DRAM: local static RAM cache. Comp 212 Computer Org & Arch 47 Z. Li, 2008 Comp 212 Computer Org & Arch 48 Z. Li, 2008

Types of External Memory Magnetic Disk (Hard Disk) RAID Removable Optical Disk CD-ROM CD-Recordable (CD-R) Physics of Magnetic Disk Disk substrate coated with magnetizable material (iron oxide rust)

13 Types of External Memory Magnetic Disk (Hard Disk) RAID Removable Optical Disk CD-ROM CD-Recordable (CD-R) Physics of Magnetic Disk Disk substrate coated with magnetizable material (iron oxide rust) Substrate, or body of the disk can be glass, steel, aluminium. Operates by magnetizing the elements on disk surface CD-R/W DVD Magnetic Tape Comp 212 Computer Org & Arch 49 Z. Li, 2008 Comp 212 Computer Org & Arch 50 Z. Li, 2008 Moving over magnetic Field generate current Inductive Write MR Read Write current Direction change N-S pattern Read and Write Mechanisms Recording & retrieval via conductive coil called a head May be single read/write head or separate ones During read/write, head is stationary, disk rotates Magnetic patterns Comp 212 Computer Org & Arch 51 Z. Li, 2008 Comp 212 Computer Org & Arch 52 Z. Li, 2008

Write Mechanisms Write Current through coil produces magnetic field Pulses sent to head Magnetic pattern recorded on surface below Read Mechanisms Read (traditional) Magnetic field moving relative to

Electrical resistance depends on direction of magnetic field, so the polarization patterns can be read as different voltage values. Comp 212 Computer Org & Arch 53 Z.

14 Write Mechanisms Write Current through coil produces magnetic field Pulses sent to head Magnetic pattern recorded on surface below Read Mechanisms Read (traditional) Magnetic field moving relative to coil produces current, The same physics as write So use the same head for read and write Read (contemporary) Separate read head, close to write head Partially shielded magneto-resistive (MR) sensor Electrical resistance depends on direction of magnetic field, so the polarization patterns can be read as different voltage values. Comp 212 Computer Org & Arch 53 Z. Li, 2008 Comp 212 Computer Org & Arch 54 Z. Li, 2008 Disk Data Organization and Layout Disk Layout Methods Diagram Concentric rings or tracks Gaps between tracks Reduce gap to increase capacity Same number of bits per track (variable packing density) Constant angular velocity Tracks divided into sectors Minimum block size is one sector May have more than one sector per block Comp 212 Computer Org & Arch 55 Z. Li, 2008 Comp 212 Computer Org & Arch 56 Z. Li, 2008

Disk Velocity Disk Characteristics Constant angular velocity (CAV) Gives pie shaped sectors and concentric tracks Individual tracks and sectors addressable Move head to given track and wait for given

15 Disk Velocity Disk Characteristics Constant angular velocity (CAV) Gives pie shaped sectors and concentric tracks Individual tracks and sectors addressable Move head to given track and wait for given sector Waste of space on outer tracks» Lower data density Multi-zone recording: Each zone has fixed bits per track More complex circuitry Comp 212 Computer Org & Arch 57 Z. Li, 2008 Comp 212 Computer Org & Arch 58 Z. Li, 2008 Fixed/Movable Head Disk Fixed head One read write head per track Heads mounted on fixed ridged arm Movable head One read write head per side Mounted on a movable arm Removable or Not Removable disk Can be removed from drive and replaced with another disk Provides unlimited storage capacity Easy data transfer between systems Nonremovable disk Permanently mounted in the drive Comp 212 Computer Org & Arch 59 Z. Li, 2008 Comp 212 Computer Org & Arch 60 Z. Li, 2008

Multiple Platters One head per side Heads are joined and aligned Aligned tracks on each platter form cylinders Data is striped by cylinder reduces head movement Increases speed (transfer rate) Disk

16 Multiple Platters One head per side Heads are joined and aligned Aligned tracks on each platter form cylinders Data is striped by cylinder reduces head movement Increases speed (transfer rate) Disk Performance - Speed Track-Track Seek time Moving head to correct track (Rotational) latency Waiting for data to rotate under head, related to rpm: 1/(2*rpm) Access time = Seek + Latency Transfer time: how fast data can be read /write from disk T = b / (rpm*n): b, bytes to be transferred, rpm, rotation speed, N: bytes per track. Comp 212 Computer Org & Arch 61 Z. Li, 2008 Comp 212 Computer Org & Arch 62 Z. Li, 2008 Disk I/O Performance Factors RAID RAID = Redundant Array of Independent Disks Set of physical disks viewed as single logical drive by O/S Data distributed across physical drives Can use redundant capacity to store parity information Total time: T = T seek + 1/ (2*rpm) + b / (rpm*n) Disk spin speed: rpm for error correction RAID0~6 for different levels of redundancy Disk data density: N bytes per track T seek : how fast to locate a track. Comp 212 Computer Org & Arch 63 Z. Li, 2008 Comp 212 Computer Org & Arch 64 Z. Li, 2008

system Comp 212 Computer Org & Arch 65 Z. Li, 2008 Comp 212 Computer Org & Arch 66 Z.

17 RAID RAID 0, 1, 2 RAID 0: No redundancy, 1-1 match between logic and physical disks RAID 1: Mirrored disk, 1-2 match between logic and physical disks RAID 2: Error correction coded, 4 logical disk mapped to 7 physical disk via Hamming coding RAID 3~6: More complex system Comp 212 Computer Org & Arch 65 Z. Li, 2008 Comp 212 Computer Org & Arch 66 Z. Li, 2008 CD Operation Optical Disk and Magnetic Tapes Reflect lights differently at Pits and lands Comp 212 Computer Org & Arch 67 Z. Li, 2008 Comp 212 Computer Org & Arch 68 Z. Li, 2008

18 Optical Storage CD-ROM Originally for audio 650Mbytes giving over 70 minutes audio Polycarbonate coated with highly reflective coat, usually aluminium Data stored as pits Read by reflecting laser How about Random Access on CD-ROM? Difficult Move head to rough position Set correct speed Read address Adjust to required location (Yawn!) Constant packing density Constant linear velocity, variable rotation velocity Comp 212 Computer Org & Arch 69 Z. Li, 2008 Comp 212 Computer Org & Arch 70 Z. Li, 2008 Other Optical Storage CD-Recordable (CD-R) WORM Now affordable Compatible with CD-ROM drives CD-RW Erasable Getting cheaper Mostly CD-ROM drive compatible DVD - what s in a name? Digital Video Disk Used to indicate a player for movies» Only plays video disks Digital Versatile Disk Used to indicate a computer drive» Will read computer disks and play video disks Dogs Veritable Dinner Officially - nothing!!! Comp 212 Computer Org & Arch 71 Z. Li, 2008 Comp 212 Computer Org & Arch 72 Z. Li, 2008

19 DVD - technology Magnetic Tape Multi-layer Very high capacity (4.7G per layer) Full length movie on single disk Using MPEG compression Finally standardized (honest!) Serial access Slow Very cheap Backup and archive Movies carry regional coding Next generation: BlueRay. Comp 212 Computer Org & Arch 73 Z. Li, 2008 Comp 212 Computer Org & Arch 74 Z. Li, 2008 Summary of Lecture #4 Mostly informational, do not need to memorize all those technical details But be able to appreciate the underlying physics and technology that makes computer possible Internal Memory Types: RAM, ROM, EPROM, EEPROM, FlashMem Summary of Lecture #4 External Memory Types: Magnetic Disk, Optical Disk, Magnetic Tape What affects the Disk performance?» Seek time» Rotation latency» Density Difference between Static and Dynamic RAM» Capacitor vs transistor state based» Refresh or not refresh» Cost Comp 212 Computer Org & Arch 75 Z. Li, 2008 Comp 212 Computer Org & Arch 76 Z. Li, 2008

20 Summary of Lecture #4 Review questions: 5.4, 6.7 Homework #1 question #4: Consider a disk system with average track seek time T seek =8ms, rotation speed of 7200 rpm, number of bytes per sector 512, and number of sector per track 800, what is the average access time to read 4KB data? Comp 212 Computer Org & Arch 77 Z. Li, 2008

Semiconductor Memory Types Microprocessor Design & Organisation HCA2102

Semiconductor Memory Types Microprocessor Design & Organisation HCA2102 Internal & External Memory Semiconductor Memory RAM Misnamed as all semiconductor memory is random access Read/Write Volatile Temporary