ECC Approach for Correcting Errors Not Handled by RAID Recovery

Transcription

1 ECC Approach for Correcting Errors Not Handled by RAID Recovery Jeff Yang Siliconmotion Flash Memory Summit 27 Note: All the material are the concept proof and simulation.s It is not the real Siliconmotion s fianl product.

2 Troditional Error recovery flow Flash Memory Summit 23 Flash Memory Summit 27 2

3 3D NAND Challenges Each 3D generation will increase the layer number by 3~5%. High-aspect ratio channel hole etch. Cell current reduction is seriously concerned. Reduce the read-voltage to improve the read-count (degradation the read-disturbance) make cell current worse. Different cell characteristics for each WL. (program-speed, cell-tocell interference, retention) Poor retention characteristics. Not easy to screen out some defects Especially on bit-column related defect. Flash Memory Summit 27 Ref: Evolution of NAND flash memory: from 2D to 3D 27 IMW 3

4 RAID is good, but. Put the data from the same failure range into the different RAID protection group. Add more write overhead, because the additional parity will be written. If the failure range cross the block, a plan based protection range is needed. Ch Ch Ch2 Ch3 Super-page bundle Plane Plane Plane Plane Plane Plane Plane Plane 2.5% overhead Ch Super-page bundle Plane Plane 5% overhead in single chip applications Flash Memory Summit 27 4

5 A read back verify scheme 2 TLC region Copy the data from SLC to TLC without RAID SLC region Write to the SLC first, with RAID protection Write channel Buffer for DATA Read channel NAND interface Controller 3 Read back check If error bit is few, program successfully. Plane Plane Plane Plane Plane Plane The SLC to TLC internal copy will be use to accelerate the write performance and power saving. (cause some random error bit.) If the TLC write complete, there is still a probability on TLC read fail from read-disturbance, X-temp, or Data-retention. Flash Memory Summit 27 5

6 Bit column related Failure Flash Memory Summit 27 6

7 Bit column related Failure(Zoom-in) Flash Memory Summit 27 7

8 Column fail after Low P/E cycle Flash Memory Summit 27 8

9 Column fail after median P/E cycle Flash Memory Summit 27 9

10 Column fail after high P/E cycle Flash Memory Summit 27

11 Vth plot after the P/E cycle A B C D E F G Lower Middle Upper Flash Memory Summit 27

12 Erase Vth plot after the P/E cycle PV PV3 PV4 PV5 PV6 PV7 Lower Middle Upper Flash Memory Summit 27 2

13 PV Vth plot after the P/E cycle PV PV3 PV4 PV5 PV6 PV7 Lower Middle Upper Flash Memory Summit 27 3

14 PV2 Vth plot after the P/E cycle PV PV3 PV4 PV5 PV6 PV7 Lower Middle Upper Flash Memory Summit 27 4

15 PV3 Vth plot after the P/E cycle PV PV3 PV4 PV5 PV6 PV7 Lower Middle Upper Flash Memory Summit 27 5

16 PV4 Vth plot after the P/E cycle PV PV3 PV4 PV5 PV6 PV7 Lower Middle Upper Flash Memory Summit 27 6

17 PV5 Vth plot after the P/E cycle PV PV3 PV4 PV5 PV6 PV7 Lower Middle Upper Flash Memory Summit 27 7

18 PV6 Vth plot after the P/E cycle PV PV3 PV4 PV5 PV6 PV7 Lower Middle Upper Flash Memory Summit 27 8

19 PV7 Vth plot after the P/E cycle PV PV3 PV4 PV5 PV6 PV7 Lower Middle Upper Flash Memory Summit 27 9

20 UBER Soft-decoding vs. HRE These strong error(high reliability error, HRE) is grow with the P/E. HRE will dominate the LDPC engine s decoding capability. These kinds of HRE is predictable and recordable..e+4 Error profile Strong-Error simulation.e+3 HRE.E-4.E+2.E-6.E-8.E-.E-2.E-4.E-6.. Flash Memory Summit 27 RBER hre hre5 hre hre5 hre2 hre25.e+.e+ Sign Soft Soft 2

21 Caching system to record the high frequency HRE location DSP-engine Blk# pg# Chk# HRE-loc 7 22 x x xa x2d3. compare the HRE location. 2. if: loc hit, cnt else: 4. if: the buffer full, remove the oldest loc, with smallest cnt 5. record the HRE-loc. Flash Memory Summit 27 cnt HRE Identifier Yes If HRE# > threshold 5 Channel value Buffer -sign 2-soft Hard-decision result 2 3 LDPC decoder 2

22 When HRE cause the Decoding fail DSP-engine After the Vth-tracking to get the proper error profile Blk# pg# Chk# HRE-loc 7 22 x x xa x2d3 cnt Fix LLR value on the HRE location Channel value buffer Hard-decision result 5 Re-decoding LDPC decoder Yes 3 Chunk address match Decode done, but uncorrectable 2 Flash Memory Summit 27 22

23 FER KB LDPC simulation result.e+ RBER vs. FER.E-.E-2.E-3.E-4.E-5.E RBER AWGN add 5bit HRE 5bit HRE fixed bit HRE fixed The HRE location will be logged. Flash Memory Summit 27 RBER=.25% with 5bit HRE: ~99.9% become correctable. RBER =.25% with bit HRE: ~98% become correctable. 23

24 HRE aware iterative decoding Hard decoding Moving Read (Using read-retry table) Soft-decoding (Iterative decoding) HRE aware iterative decoding RAID protection (addition parity) DISK Rescue Flash Memory Summit 27 24

25 Thanks Q&A Flash Memory Summit 27 25