LVDS Product. +3.3V LVDS 60Bit Flat Panel Display (FPD) Receiver 135MHz
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1 LVDS Product DTC30LM36 (Rev. 1.1) REVISED AUGUST V LVDS 60Bit Flat Panel Display (FPD) Receiver 135MHz General Description Features The DTC30LM36 receiver is designed to support Wide frequency range Dual/Single link transmissions between Host and Flat Dual IN / Dual Out Mode: 8-135MHz (CLKOUT) Panel Display up to 1080p and QXGA resolutions. It Dual IN / Single Out Mode: MHz (CLKOUT) Supports 480i ~ 1080p and VGA ~QXGA receives and converts LVDS (Low Voltage Differential Power down mode Signal) data streams back into 67 bits of CMOS/TTL data Single 3.3V supply with either falling edge or rising edge clock for convenient PLL requires No external components Flexible Input/Output Options interface with a variety of LCD panel controllers. 1. Single/Dual LVDS port IN, Single/Dual TTL port OUT 2. Double Clock Edge output option When using a 135 MHz clock and dual link transmission, 3. Output Port Switch the data throughput is 1.1 Gbytes/sec with an effective 4. 1 or 2 Clock input option TTL clock edge selectable data rate of 945 Mbps per LVDS channel. This chipset is Flexible TTL clock output offset an ideal means to solve EMI and cable size problems 2 Output data mapping for simplifying PCB layout associated with wide, high speed TTL interfaces. 144 pin LQFP Package Pin Compatible with Thine THC63LVD1024 Block Diagram DTC30LM DOESTEK Co., Ltd.
2 PIN OUT 108 PLLGND 107 PLLVCC 106 VCC 105 CONT CONT DE 102 VSYNC 101 HSYNC 100 B19 99 B18 98 GND 97 VCC 96 B17 95 B16 94 B15 93 B14 92 B13 91 B12 90 B11 89 GND 88 VCC 87 B10 86 G19 85 G18 84 G17 83 G16 82 G15 81 GND 80 VCC 79 G14 78 G13 77 G12 76 G11 75 G10 74 R19 73 R18 LVDSGND 109 RA1-110 RA RB1-112 RB LVDSVCC 114 LVDSGND 115 RC1-116 RC RCLK1-118 RCLK LVDSVCC 120 LVDSGND 121 RD1-122 RD RE1-124 RE LVDSVCC 126 LVDSGND 127 RA2-128 RA RB2-130 RB LVDSVCC 132 LVDSGND 133 RC2-134 RC RCLK2-136 RCLK LVDSVCC 138 LVDSGND 139 RD2-140 RD RE2-142 RE SEL R17 71 GND 70 VCC 69 R16 68 R15 67 R14 66 R13 65 R12 64 R11 63 R10 62 CLKGND 61 CLKVCC 60 CLKOUT 59 GND 58 GND 57 VCC 56 CONT22 55 CONT21 54 GND 53 VCC 52 B29 51 B28 50 B27 49 B26 48 B25 47 GND 46 VCC 45 B24 44 B23 43 B22 42 B21 41 B20 40 G29 39 GND 38 VCC 37 G28 PLLGND 1 PLLVCC 2 MODE3 3 /PDN 4 MODE0 5 MODE1 6 DK 7 R_FB 8 OE 9 MODE2 10 MAP 11 VCC 12 GND 13 R20 14 R21 15 R22 16 R23 17 R24 18 R25 19 R26 20 VCC 21 GND 22 R27 23 R28 24 R29 25 G20 26 G21 27 VCC 28 VCC 29 GND 30 G22 31 G23 32 G24 33 G25 34 G26 35 G DOESTEK Co., Ltd.
3 PACKAGE DOESTEK Co., Ltd.
4 Pin Description Pin Name Pin # Type Description RA1+, RA1-111,110 RB1+, RB1-113,112 RC1+, RC1-117,116 RD1+, RD1-123,122 RE1+, RE1-125,124 LVDS IN 1 st Link. 1 st Pixel input data in Dual-Link Input Mode option. RCLK1+, RCLK1-119,118 LVDS IN 1 st Link. LVDS Clock input. RA2+, RA2-129,128 RB2+, RB2-131,130 RC2+, RC2-135,134 RD2+, RD2-141,140 RE2+, RE2-143,142 LVDS IN 2 nd Link. 2 nd Pixel input data in Dual-Link Input Mode option. RCLK2+, RCLK2-137,136 LVDS IN 2 nd Link. LVDS Clock input. R19~R , G19~G , B19~B10 100, 99, 96-90, 87 R29~R , G29~G20 40, 37-31, 27, 26 B29~B , OUT OUT 1 st Pixel, TTL level Data Outputs. 2 nd Pixel, TTL level Data Outputs. CONT11,CONT12 104, 105 OUT TTL level Control Data Outputs. CONT21,CONT22 55, 56 DE 103 OUT TTL level Data Enable Output. VSYNC 102 OUT TTL level Vsync Output. HSYNC 101 OUT TTL level Hsync Output. CLKOUT 60 OUT TTL level Clock Output. /PDN 4 IN Power down and Output Control.(Table1) H: Normal operation L: Power down MODE1,MODE0 6,5 IN Pixel Data Mode Mode1 Mode0 Mode H H Single Link(Single-in/Single-Out) H L Single Link(Single-in/Dual-Out) L H Dual Link (Dual-in/Single-Out) L L Dual Link (Dual-in/Dual-Out) DOESTEK Co., Ltd.
5 Pin Name Pin # Type Description Output Clock Delay Timing Select Option. MODE[1:0] DK Offset DK 7 IN X L 0 M H tdout tdout t DOUT = Output Data Cycle R_FB 8 IN OE 9 IN MODE2 10 IN MAP 11 IN MODE3 3 IN SEL 144 IN Output Clock Triggering Edge Select. H : Rising edge L : Falling edge Output Enable Option.(Table1) H : Output enable L : Output disable DDR function Enable Option. The use of this function depends on the setting of MODE<1:0> : MODE<1:0>=LH(Dual-in/Single-out Mode) H: DDR(Double Edge Output) function enable. L: DDR(Double Edge Output) function disable. MODE<1:0>=Other Must be tied to GND LVDS mapping table select.(see Fig 11, 12 and Tables 2~ 9) H : Mapping Mode1 L : Mapping Mode2 Output Port Switch Option. The use of this function depends on the setting of MODE<1:0> : MODE<1:0>=LH(Dual-in/Single-out Mode) H : Port Switch Disable L : Port Switch Enable LVDS 2 nd Port Clock input control option H or Open : 2 nd Port Clock Enable. L : 2 nd Port Clock Disable. VCC GND LVDSVCC LVDSGND 12, 21, 28, 29, 38, 46, 53, 57, 70, 80, 88, 97, , 22, 30, 39, 47, 54, 58, 59, 71, 81, 89, , 120, 126, 132, , 115, 121, 127, 133, 139 Power Ground Power Ground Power Supply Pins for TTL inputs and digital circuitry. Ground Pins of TTL inputs and digital circuitry. Power Supply Pins for LVDS Inputs. Ground Pins for LVDS Inputs. PLLVCC 2, 107 Power Power Supply Pins for PLL circuitry. PLLGND 1, 108 Ground Ground Pins for PLL circuitry. CLKVCC 61 Power Power Supply Pins for TTL output of CLKOUT. CLKGND 62 Ground Ground Pins for TTL output of CLKOUT DOESTEK Co., Ltd.
6 Absolute Maximum Ratings Supply voltage ( V CC ) -0.3V ~ +4.0V CMOS / TTL Input Voltage. -0.3V ~ ( V CC + 0.3V ) LVDS Driver Output Voltage. -0.3V ~ ( V CC + 0.3V ) Output Current. Junction Temperature. -30mA ~ 30mA +125 C Storage Temperature Range. -55 C ~ 125 C Lead Temperature ( Soldering, 4sec ) +260 C Maximum Power Dissipation 2.5W Note: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of Electrical Characteristics specify conditions for device operation DOESTEK Co., Ltd.
7 Recommended Operating Conditions Parameter Min Typ Max Units All Supply Voltage V Operating Ambient Temperature C MODE<1:0> = LL Dual-in / Dual-out LVDS Input MHz Output MHz Single Edge Output LVDS Input MHz MODE<1:0> = LH ( MODE2 = L ) Output MHz Clock Dual-in / Single-out Double Edge Output LVDS Input MHz Frequency ( MODE2 = H ) Output MHz MODE<1:0> = HL Single-in / Dual-out MODE<1:0> = HH Single-in / Single-out LVDS Input MHz Output MHz LVDS Input MHz Output MHz Differential CLKIN High Time(t RCIH )(Fig1) t 2 RCIP 7 t 5 RCIP 7 ns Differential CLKIN Low Time(t RCIL )(Fig1) t 2 RCIP 7 t 5 RCIP 7 ns Figure 1. Differential CLKIN DOESTEK Co., Ltd.
8 Electrical Characteristics CMOS / TTL DC SPECIFICATIONS V CC = VCC=PLLVCC=LVDSVCC=CLKVCC Symbol Parameter Conditions Min Typ Max Units V IH High Level Input Voltage /PDN, MODE[3:0], 2.0 V CC V V IL Low Level Input Voltage R_FB, OE, MAP GND 0.8 V V IH3 High Level Input Voltage 0.8 V CC V CC V V IM3 Middle Level Input Voltage 3-Level Inputs(DK Pin) 0.4 V CC 0.6 V CC V V IL3 Low Level Input Voltage GND 0.2 V CC V V OH High Level Output Voltage I OH = -8mA 2.4 V V OL Low Level Output Voltage I OL = 8mA 0.4 V I IN Input Current GND V IN V CC ±10 µa I IL3 3-Level Input Leakage Current GND V IN V CC ±10 µa LVDS Receiver DC Specifications V CC = VCC=PLLVCC=LVDSVCC=CLKVCC Symbol Parameter Conditions Min Typ Max Units V TH Differential Input High Threshold V IC = 1.2V 100 mv V TL Differential Input Low Threshold V IC = 1.2V -100 mv I IN Input Current V IN = 2.4V / 0V ±10 µa DOESTEK Co., Ltd.
9 Electrical Characteristics (Continued) SUPPLY CURRENT V CC = VCC=PLLVCC=LVDSVCC=CLKVCC Symbol Parameter Conditions Typ Max Units MODE<1:0> = HH Single-in/Single-out MODE2 = L CLKOUT=65MHz 139 ma CLKOUT=85MHz 172 ma CLKOUT=135MHz 252 ma MODE<1:0> = HL Single-in/Dual-out CLKOUT=32.5MHz 127 ma CLKOUT=42.5MHz 155 ma CLKOUT=67.5MHz 226 ma I RCCW Receiver Supply Current ( Worst Case Pattern ) Fig2. CL = 8pF MODE<1:0> = LH Dual-in/Single out MODE2 = L, MODE3 = H DDR Output Off (SEL = L) MODE<1:0> = LH Dual-in/ Single-out MODE2 = H, MODE3 = H DDR Output On (SEL = L) MODE<1:0> = LL Dual-in/Dual-out (SEL = L) CLKOUT=65MHz 148 ma CLKOUT=85MHz 174 ma CLKOUT=135MHz 242 ma CLKOUT=150MHz 263 ma CLKOUT=32.5MHz 141 ma CLKOUT=42.5MHz 166 ma CLKOUT=67.5MHz 231 ma CLKOUT=75MHz 251 ma CLKOUT=65MHz 242 ma CLKOUT=85MHz 299 ma CLKOUT=135MHz 442 ma I RCCS Receiver Power Down Supply Current /PDN = L 50 µa * Figure 2. Worst case pattern DOESTEK Co., Ltd.
10 Switching Characteristics V CC = VCC=PLLVCC=LVDSVCC=CLKVCC Symbol Parameter Min. Typ. Max. Units t RCP CLKOUT Period (Fig 4) 6.67 T 250 ns t RCH CLKOUT High Time (Fig 4) ns t RCL CLKOUT Low Time (Fig 4) ns t DOUT TTL Data OUT Period (Fig 5,6) 6.67 T 250 ns t RS TTL Data Setup to CLKOUT (Fig 5,6) 0.45t RCP t RH TTL Data Hold to CLKOUT (Fig 5,6) 0.45t RCP ns ns t TLH TTL Low to High Transition Time (Fig 3) ns t THL TTL High to Low Transition Time (Fig 3) ns t RCIP CLKIN Period (Fig 1) ns t SK Receiver Skew Margin (Fig 7) t RCIP = 85MHz ps t RIP1 Input Data Position 0 (Fig 7) -t SK 0 +t SK ps t RIP0 Input Data Position 1 (Fig 7) ns t RIP6 Input Data Position 2 (Fig 7) ns t RIP5 Input Data Position 3 (Fig 7) ns t RIP4 Input Data Position 4 (Fig 7) ns t RIP3 Input Data Position 5 (Fig 7) ns t RIP2 Input Data Position 6 (Fig 7) ns t RPLL PLL Lock Set Time (Fig 8) 10.0 ms t RCD t DEINT t DEH t DEL RCLK +/- to CLKOUT Delay (Fig 9) MODE<1:0>=LL, Dual-in, Dual-out MODE<1:0>=HL (Single IN/Dual OUT Mode) Only DE input period (Fig 10) DE input High time (Fig 10) DE input Low time (Fig 10) 4t RCIP 2t RCIP 2t RCIP 4t RCIP +8.3ns t RCIP *(2n) n=integer ns ns ns ns DOESTEK Co., Ltd.
11 AC Timing Diagrams Figure 3. CMOS/TTL Output Load and Transition Time Figure 4. CLKOUT Period and High/Low Time Figure 5. CLKOUT Position and Setup/Hold Timing DOESTEK Co., Ltd.
12 Figure 6. CLKOUT Position and Setup/Hold Timing for Double Edge Output Mode MODE<1:0>=LH, MODE2=H Figure 7. LVDS Input Data Position Note: 1) V diff = (Ryx+) (Ryx-),.. (RCLKy+) (RCLKy-) DOESTEK Co., Ltd.
13 Figure 8. PLL Lock Set Time Figure 9. RCLK to CLKOUT delay (Latency) Figure 10. DE Input Timing for Single In, Dual Out Mode Option DOESTEK Co., Ltd.
14 Power Down and Output Enable Control Table 1 : Output Control /PDN R_FB OE Data Outputs Clock Outputs Hi-Z Hi-Z All 0 Fixed Low Hi-Z Hi-Z All 0 Fixed Low Hi-Z Hi-Z Data Out Negative Clock Hi-Z Hi-Z Data Out Positive Clock Output Data Mapping Table 2 : Output Color Data naming rule X Y Z Description X = R X = G X = B Red Color Data Green Color Data Blue Color Data Y = None Y = O Y = E Dual Pixel Single Pixel 1 st Pixel Data 2 nd Pixel Data Z = 0 ~ 9 Bit number 0 : LSB (Least significant Bit) 9 : MSB (Most Significant Bit) DOESTEK Co., Ltd.
15 Output Data Mapping (Continued) Table 3 : TTL / CMOS Output Data Mapping (Single-out mode, MODE0 = H) Data Signals Receiver Output Pin Names 30 Bit 24 Bit 18 Bit 30 Bit 24 Bit 18 Bit R0 R1 R10 R11 R2 R0 R12 R12 R3 R1 R13 R13 R4 R2 R0 R14 R14 R14 R5 R3 R1 R15 R15 R15 R6 R4 R2 R16 R16 R16 R7 R5 R3 R17 R17 R17 R8 R6 R4 R18 R18 R18 R9 R7 R5 R19 R19 R19 G0 G1 G10 G11 G2 G0 G12 G12 G3 G1 G13 G13 G4 G2 G0 G14 G14 G14 G5 G3 G1 G15 G15 G15 G6 G4 G2 G16 G16 G16 G7 G5 G3 G17 G17 G17 G8 G6 G4 G18 G18 G18 G9 G7 G5 G19 G19 G19 B0 B1 B10 B11 B2 B0 B12 B12 B3 B1 B13 B13 B4 B2 B0 B14 B14 B14 B5 B3 B1 B15 B15 B15 B6 B4 B2 B16 B16 B16 B7 B5 B3 B17 B17 B17 B8 B6 B4 B18 B18 B18 B9 B7 B5 B19 B19 B DOESTEK Co., Ltd.
16 Output Data Mapping (Continued) Table 4 : TTL / CMOS Output Data Mapping (Dual-out Mode, MODE0 = L) 1 st Pixel Data 2 nd Pixel Data Data Signals Receiver Output Pin Names Data Signals Receiver Output Pin Names 30 Bit 24 Bit 18 Bit 30 Bit 24 Bit 18 Bit 30 Bit 24 Bit 18 Bit 30 Bit 24 Bit 18 Bit RE0 R10 RO0 R20 RE1 R11 RO1 R21 RE2 RE0 R12 R12 RO2 RO0 R22 R22 RE3 RE1 R13 R13 RO3 RO1 R23 R23 RE4 RE2 RE0 R14 R14 R14 RO4 RO2 RO0 R24 R24 R24 RE5 RE3 RE1 R15 R15 R15 RO5 RO3 RO1 R25 R25 R25 RE6 RE4 RE2 R16 R16 R16 RO6 RO4 RO2 R26 R26 R26 RE7 RE5 RE3 R17 R17 R17 RO7 RO5 RO3 R27 R27 R27 RE8 RE6 RE4 R18 R18 R18 RO8 RO6 RO4 R28 R28 R28 RE9 RE7 RE5 R19 R19 R19 RO9 RO7 RO5 R29 R29 R29 GE0 G10 GO0 G20 GE1 G11 GO1 G21 GE2 GE0 G12 G12 GO2 GO0 G22 G22 GE3 GE1 G13 G13 GO3 GO1 G23 G23 GE4 GE2 GE0 G14 G14 G14 GO4 GO2 GO0 G24 G24 G24 GE5 GE3 GE1 G15 G15 G15 GO5 GO3 GO1 G25 G25 G25 GE6 GE4 GE2 G16 G16 G16 GO6 GO4 GO2 G26 G26 G26 GE7 GE5 GE3 G17 G17 G17 GO7 GO5 GO3 G27 G27 G27 GE8 GE6 GE4 G18 G18 G18 GO8 GO6 GO4 G28 G28 G28 GE9 GE7 GE5 G19 G19 G19 GO9 GO7 GO5 G29 G29 G29 BE0 B10 BO0 B20 BE1 B11 BO1 B21 BE2 BE0 B12 B12 BO2 BO0 B22 B22 BE3 BE1 B13 B13 BO3 BO1 B23 B23 BE4 BE2 BE0 B14 B14 B14 BO4 BO2 BO0 B24 B24 B24 BE5 BE3 BE1 B15 B15 B15 BO5 BO3 BO1 B25 B25 B25 BE6 BE4 BE2 B16 B16 B16 BO6 BO4 BO2 B26 B26 B26 BE7 BE5 BE3 B17 B17 B17 BO7 BO5 BO3 B27 B27 B27 BE8 BE6 BE4 B18 B18 B18 BO8 BO6 BO4 B28 B28 B28 BE9 BE7 BE5 B19 B19 B19 BO9 BO7 BO5 B29 B29 B DOESTEK Co., Ltd.
17 LVDS Input Data Mapping Figure 11. LVDS Inputs Mapped to TTL Data Outputs MODE1 = H (Single-in Mode) Figure 12.a. LVDS Inputs Mapped to TTL Data Outputs MODE1 = L (Dual-in Mode) SEL = L Figure 12.b. LVDS Inputs Mapped to TTL Data Outputs MODE1 = L (Dual-in Mode) SEL = H DOESTEK Co., Ltd.
18 LVDS Input Data Mapping (Continued) Table 5 : LVDS Input Data Mapping (Single-in/Single-out, MODE<1:0>=HH) LVDS Input Data Mapping Mode1 Mapping Mode2 RA10 R14 R12 RA11 R15 R13 RA12 R16 R14 RA13 R17 R15 RA14 R18 R16 RA15 R19 R17 RA16 G14 G12 RB10 G15 G13 RB11 G16 G14 RB12 G17 G15 RB13 G18 G16 RB14 G19 G17 RB15 B14 B12 RB16 B15 B13 RC10 B16 B14 RC11 B17 B15 RC12 B18 B16 RC13 B19 B17 RC14 HSYNC HSYNC RC15 VSYNC VSYNC RC16 DE DE RD10 R12 R18 RD11 R13 R19 RD12 G12 G18 RD13 G13 G19 RD14 B12 B18 RD15 B13 B19 RD16 CONT11 CONT11 RE10 R10 R10 RE11 R11 R11 RE12 G10 G10 RE13 G11 G11 RE14 B10 B10 RE15 B11 B11 RE16 CONT12 CONT DOESTEK Co., Ltd.
19 LVDS Input Data Mapping (Continued) Table 6 : LVDS Input Data Mapping (Single-in/Dual-out, MODE<1:0>=HL) LVDS Input Data (1 st Pixel) 1 st Pixel Data Mapping Mode1 Mapping Mode2 LVDS Input Data (2 nd Pixel) 2 nd Pixel Data Mapping Mode1 Mapping Mode2 RA10 (n) R14 R12 RA10 (n+1) R24 R22 RA11 (n) R15 R13 RA11 (n+1) R25 R23 RA12 (n) R16 R14 RA12 (n+1) R26 R24 RA13 (n) R17 R15 RA13 (n+1) R27 R25 RA14 (n) R18 R16 RA14 (n+1) R28 R26 RA15 (n) R19 R17 RA15 (n+1) R29 R27 RA16 (n) G14 G12 RA16 (n+1) G24 G22 RB10 (n) G15 G13 RB10 (n+1) G25 G23 RB11 (n) G16 G14 RB11 (n+1) G26 G24 RB12 (n) G17 G15 RB12 (n+1) G27 G25 RB13 (n) G18 G16 RB13 (n+1) G28 G26 RB14 (n) G19 G17 RB14 (n+1) G29 G27 RB15 (n) B14 B12 RB15 (n+1) B24 B22 RB16 (n) B15 B13 RB16 (n+1) B25 B23 RC10 (n) B16 B14 RC10 (n+1) B26 B24 RC11 (n) B17 B15 RC11 (n+1) B27 B25 RC12 (n) B18 B16 RC12 (n+1) B28 B26 RC13 (n) B19 B17 RC13 (n+1) B29 B27 RC14 (n) HSYNC HSYNC RC14 (n+1) HSYNC HSYNC RC15 (n) VSYNC VSYNC RC15 (n+1) VSYNC VSYNC RC16 (n) DE DE RC16 (n+1) DE DE RD10 (n) R12 R18 RD10 (n+1) R22 R28 RD11 (n) R13 R19 RD11 (n+1) R23 R29 RD12 (n) G12 G18 RD12 (n+1) G22 G28 RD13 (n) G13 G19 RD13 (n+1) G23 G29 RD14 (n) B12 B18 RD14 (n+1) B22 B28 RD15 (n) B13 B19 RD15 (n+1) B23 B29 RD16 (n) CONT11 CONT11 RD16 (n+1) CONT21 CONT21 RE10 (n) R10 R10 RE10 (n+1) R20 R20 RE11 (n) R11 R11 RE11 (n+1) R21 R21 RE12 (n) G10 G10 RE12 (n+1) G20 G20 RE13 (n) G11 G11 RE13 (n+1) G21 G21 RE14 (n) B10 B10 RE14 (n+1) B20 B20 RE15 (n) B11 B11 RE15 (n+1) B21 B21 RE16 (n) CONT12 CONT12 RE16 (n+1) CONT22 CONT DOESTEK Co., Ltd.
20 LVDS Input Data Mapping (Continued) Table 7 : LVDS Input Data Mapping (Dual-in/Single-out, DDR On or Off, MODE<1:0>=LH, MODE2=H or L, MODE3 = H) 1 st Pixel Data 2 nd Pixel Data LVDS Input Data (1 st Pixel) Mapping Mode1 Mapping Mode2 LVDS Input Data (2 nd Pixel) Mapping Mode1 Mapping Mode2 RA10 R14(n) R12(n) RA20 R14(n+1) R12(n+1) RA11 R15(n) R13(n) RA21 R15(n+1) R13(n+1) RA12 R16(n) R14(n) RA22 R16(n+1) R14(n+1) RA13 R17(n) R15(n) RA23 R17(n+1) R15(n+1) RA14 R18(n) R16(n) RA24 R18(n+1) R16(n+1) RA15 R19(n) R17(n) RA25 R19(n+1) R17(n+1) RA16 G14(n) G12(n) RA26 G14(n+1) G12(n+1) RB10 G15(n) G13(n) RB20 G15(n+1) G13(n+1) RB11 G16(n) G14(n) RB21 G16(n+1) G14(n+1) RB12 G17(n) G15(n) RB22 G17(n+1) G15(n+1) RB13 G18(n) G16(n) RB23 G18(n+1) G16(n+1) RB14 G19(n) G17(n) RB24 G19(n+1) G17(n+1) RB15 B14(n) B12(n) RB25 B14(n+1) B12(n+1) RB16 B15(n) B13(n) RB26 B15(n+1) B13(n+1) RC10 B16(n) B14(n) RC20 B16(n+1) B14(n+1) RC11 B17(n) B15(n) RC21 B17(n+1) B15(n+1) RC12 B18(n) B16(n) RC22 B18(n+1) B16(n+1) RC13 B19(n) B17(n) RC23 B19(n+1) B17(n+1) RC14 HSYNC(n) HSYNC(n) RC24 HSYNC(n+1) HSYNC(n+1) RC15 VSYNC(n) VSYNC(n) RC25 VSYNC(n+1) VSYNC(n+1) RC16 DE(n) DE(n) RC26 DE(n+1) DE(n+1) RD10 R12(n) R18(n) RD20 R12(n+1) R18(n+1) RD11 R13(n) R19(n) RD21 R13(n+1) R19(n+1) RD12 G12(n) G18(n) RD22 G12(n+1) G18(n+1) RD13 G13(n) G19(n) RD23 G13(n+1) G19(n+1) RD14 B12(n) B18(n) RD24 B12(n+1) B18(n+1) RD15 B13(n) B19(n) RD25 B13(n+1) B19(n+1) RD16 CONT11(n) CONT11(n) RD26 CONT11(n+1) CONT11(n+1) RE10 R10(n) R10(n) RE20 R10(n+1) R10(n+1) RE11 R11(n) R11(n) RE21 R11(n+1) R11(n+1) RE12 G10(n) G10(n) RE22 G10(n+1) G10(n+1) RE13 G11(n) G11(n) RE23 G11(n+1) G11(n+1) RE14 B10(n) B10(n) RE24 B10(n+1) B10(n+1) RE15 B11(n) B11(n) RE25 B11(n+1) B11(n+1) RE16 CONT12(n) CONT12(n) RE26 CONT12(n+1) CONT12(n+1) DOESTEK Co., Ltd.
21 LVDS Input Data Mapping (Continued) Table 8 : LVDS Input Data Mapping (Dual-in/Single-out, DDR On or Off, MODE<1:0>=LH, MODE2=H or L, MODE3 = L) LVDS Input Data (1 st Pixel) 1 st Pixel Data Mapping Mode1 Mapping Mode2 LVDS Input Data (2 nd Pixel) 2 nd Pixel Data Mapping Mode1 Mapping Mode2 RA10 R24(n) R22(n) RA20 R24(n+1) R22(n+1) RA11 R25(n) R23(n) RA21 R25(n+1) R23(n+1) RA12 R26(n) R24(n) RA22 R26(n+1) R24(n+1) RA13 R27(n) R25(n) RA23 R27(n+1) R25(n+1) RA14 R28(n) R26(n) RA24 R28(n+1) R26(n+1) RA15 R29(n) R27(n) RA25 R29(n+1) R27(n+1) RA16 G24(n) G22(n) RA26 G24(n+1) G22(n+1) RB10 G25(n) G23(n) RB20 G25(n+1) G23(n+1) RB11 G26(n) G24(n) RB21 G26(n+1) G24(n+1) RB12 G27(n) G25(n) RB22 G27(n+1) G25(n+1) RB13 G28(n) G26(n) RB23 G28(n+1) G26(n+1) RB14 G29(n) G27(n) RB24 G29(n+1) G27(n+1) RB15 B24(n) B22(n) RB25 B24(n+1) B22(n+1) RB16 B25(n) B23(n) RB26 B25(n+1) B23(n+1) RC10 B26(n) B24(n) RC20 B26(n+1) B24(n+1) RC11 B27(n) B25(n) RC21 B27(n+1) B25(n+1) RC12 B28(n) B26(n) RC22 B28(n+1) B26(n+1) RC13 B29(n) B27(n) RC23 B29(n+1) B27(n+1) RC14 HSYNC(n) HSYNC(n) RC24 HSYNC(n+1) HSYNC(n+1) RC15 VSYNC(n) VSYNC(n) RC25 VSYNC(n+1) VSYNC(n+1) RC16 DE(n) DE(n) RC26 DE(n+1) DE(n+1) RD10 R22(n) R28(n) RD20 R22(n+1) R28(n+1) RD11 R23(n) R29(n) RD21 R23(n+1) R29(n+1) RD12 G22(n) G28(n) RD22 G22(n+1) G28(n+1) RD13 G23(n) G29(n) RD23 G23(n+1) G29(n+1) RD14 B22(n) B28(n) RD24 B22(n+1) B28(n+1) RD15 B23(n) B29(n) RD25 B23(n+1) B29(n+1) RD16 CONT21(n) CONT21(n) RD26 CONT21(n+1) CONT21(n+1) RE10 R20(n) R20(n) RE20 R20(n+1) R20(n+1) RE11 R21(n) R21(n) RE21 R21(n+1) R21(n+1) RE12 G20(n) G20(n) RE22 G20(n+1) G20(n+1) RE13 G21(n) G21(n) RE23 G21(n+1) G21(n+1) RE14 B20(n) B20(n) RE24 B20(n+1) B20(n+1) RE15 B21(n) B21(n) RE25 B21(n+1) B21(n+1) RE16 CONT22(n) CONT22(n) RE26 CONT22(n+1) CONT22(n+1) DOESTEK Co., Ltd.
22 LVDS Input Data Mapping (Continued) Table 9 : LVDS Input Data Mapping (Dual-in/Dual-out, MODE<1:0>=LL) LVDS Input Data (1 st Pixel) 1 st Pixel Data Mapping Mode1 Mapping Mode2 LVDS Input Data (2 nd Pixel) 2 nd Pixel Data Mapping Mode1 Mapping Mode2 RA10 R14 R12 RA20 R24 R22 RA11 R15 R13 RA21 R25 R23 RA12 R16 R14 RA22 R26 R24 RA13 R17 R15 RA23 R27 R25 RA14 R18 R16 RA24 R28 R26 RA15 R19 R17 RA25 R29 R27 RA16 G14 G12 RA26 G24 G22 RB10 G15 G13 RB20 G25 G23 RB11 G16 G14 RB21 G26 G24 RB12 G17 G15 RB22 G27 G25 RB13 G18 G16 RB23 G28 G26 RB14 G19 G17 RB24 G29 G27 RB15 B14 B12 RB25 B24 B22 RB16 B15 B13 RB26 B25 B23 RC10 B16 B14 RC20 B26 B24 RC11 B17 B15 RC21 B27 B25 RC12 B18 B16 RC22 B28 B26 RC13 B19 B17 RC23 B29 B27 RC14 HSYNC HSYNC RC24 RC15 VSYNC VSYNC RC25 N/A RC16 DE DE RC26 RD10 R12 R18 RD20 R22 R28 RD11 R13 R19 RD21 R23 R29 RD12 G12 G18 RD22 G22 G28 RD13 G13 G19 RD23 G23 G29 RD14 B12 B18 RD24 B22 B28 RD15 B13 B19 RD25 B23 B29 RD16 CONT11 CONT11 RD26 CONT21 CONT21 RE10 R10 R10 RE20 R20 R20 RE11 R11 R11 RE21 R21 R21 RE12 G10 G10 RE22 G20 G20 RE13 G11 G11 RE23 G21 G21 RE14 B10 B10 RE24 B20 B20 RE15 B11 B11 RE25 B21 B21 RE16 CONT12 CONT12 RE26 CONT22 CONT DOESTEK Co., Ltd.
23 IMPORTANT NOTICE: - The contents of this data sheet are subject to change without prior notice. DOESTEK Co., Ltd. ( ) 6F TechnoComplex Korea Univ., Anam-Dong5-Ga, Songbuk-Gu, SEOUL, KOREA Tel) DOESTEK Co., Ltd.
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To Our Customers CEL continues to offer industry leading semiconductor products from Japan. We are pleased to add new communication products from Electronics to our product portfolio. www.cel.com 112MHz
Figure 1. Block Diagram
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To Our Customers CEL continues to offer industry leading semiconductor products from Japan. We are pleased to add new communication products from THine Electronics to our product portfolio. www.cel.com
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To Our Customers Continuing it s rich tradition of partnering with high quality Japanese semiconductor suppliers, CEL is now partnering with THine from May of 2015 onwards. www.cel.com THC63LVDR84C 24bit
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To Our Customers Continuing it s rich tradition of partnering with high quality Japanese semiconductor suppliers, CEL is now partnering with THine from May of 2015 onwards. www.cel.com Application Note
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