THC63LVD1023B/THC63LVD1024 Application Note

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1 Application Note / Application Note Mode setting, System Diagram and PCB Design Guide Date Revision Contents 200/09/0 Rev.1.00_E New created 200//15 Rev.1.01_E Typo 2008/08/06 Rev.1._E Add Some igures Copyright 2008 THine Electronics, Inc. 1/16 THine Electronics, Inc.

2 Contents 1.Mode Setting... P3 2.Signal Flow or Each Setting... P4 3.TTL Data Timing Diagram... P6 4.Example o System Diagram... P 5.Note... P13 6.PCB Design Guide Line... P14 Copyright 2008 THine Electronics, Inc. 2/16 THine Electronics, Inc.

3 1. Mode Setting SYNC /ASYNC SYNC ASYNC Input/Output Single In/ Single Out Single In/ Dual Out Dual In/ Single Out Dual In/ Dual Out Dual In/ Dual Out Option ASYNC MO3 MO MO MO0 SYNC/ASYNC Select H: ASYNC L: SYNC Single In / Dual Out Input Port H: Data Port1 L: Data Port2 Function select - Input mode H: Single L: Dual Output mode Distribution o (Fig.2-1, 4-1) L * L H H Distribution on (Fig.2-2) L * H H H DDR o, Port SW o (Use Data Port1) (Fig.2-3) L H or Open L H L DDR on, Port SW o (Use Data Port1) (Fig.2-4) L H or Open H H L DDR o, Port SW on (Use Data Port2) (Fig.2-5) L L L H L DDR on, Port SW on (Use Data Port2) (Fig.2-6, 4-4) L L H H L - (Fig.2-, 4-2) L * * L H - (Fig.2-8) L * * L L Crosspoint SW o (Fig.2-9) H * L * * Crosspoint SW on (Fig.2-) H * H * * *: Don t care H: Single L: Dual Input/Output Single In/Single Out (Fig.2-11, 4-1) Single In/Dual Out (Fig.2-12, 4-2) Dual In/Single Out (Fig.2-13/14, 4-4) Dual In/Dual Out (Fig.2-15, 4-5) Option MO MO MO0 DDR Input mode Output mode H: DDR on L: DDR o H: Single L: Dual H: Single L: Dual -- L H H -- L H L DDR o L L H DDR on H L H -- L L L Copyright 2008 THine Electronics, Inc. 3/16 THine Electronics, Inc.

4 2. Signal Flow or Each Setting Single In / Single Out Distribution O Single In / Single Out Distribution On Hysnc1 IN1 Hysnc2 IN2 Fig2-1 Single In / Dual Out DDR o / Port Switch O Hysnc1 IN1 Hysnc2 IN2 Same Data Fig2-2 Single In / Dual Out DDR on / Port Switch O T1+/- T2+/- T1+/- T2+/- =T1+/- Hysnc1 IN1 T1+/- /2 /2 /2 Hysnc1 IN1 T1+/- /2 /2 Hysnc2 IN2 T2+/- /2 /2 Hysnc2 IN2 T2+/- /2 /2 =T1+/- =T1+/- Fig2-3 Fig2-4 Single In / Dual Out DDR o / Port Switch On Single In / Dual Out DDR on / Port Switch On Hysnc1 IN1 T1+/- /2 /2 Hsync1 IN1 T1+/- /2 /2 Hysnc2 IN2 T2+/- /2 /2 /2 Hsync2 IN2 T2+/- /2 /2 Fig2-5 Dual In / Single Out =T1+/- Fig2-6 Dual In / Dual Out = T1+/- Hysnc1 IN1 T1+/- 2 2 Hysnc1 IN1 T1+/- Data Rate Hysnc2 IN2 Fig2- T2+/- Data Rate Hysnc2 IN2 Fig2-8 T2+/- = T1+/- Copyright 2008 THine Electronics, Inc. 4/16 THine Electronics, Inc.

5 Asynchronous mode / Cross Point Switch O Asynchronous mode / Cross Point Switch On 1 1 Hsync1 IN1 T1+/ Hsync1 IN1 T1+/ Hsync2 IN2 T2+/ Hsync2 IN2 T2+/- 1 1 Fig2-9 Fig2- Single In / Single Out Single In / Dual Out RA1+/- RB1+/- RC1+/- RD1+/- RE1+/- R1+/- VSYNC OUT 2 2 RA1+/- RB1+/- RC1+/- RD1+/- RE1+/- R1+/- VSYNC OUT RA2+/- RB2+/- RC2+/- RD2+/- RE2+/- L ix RA2+/- RB2+/- RC2+/- RD2+/- RE2+/- Data Rate Fig2-11 Fig2-12 Dual In / Single Out DDR o Dual In / Single Out DDR on /2 /2 RA1+/- RB1+/- RC1+/- RD1+/- RE1+/- R1+/- VSYNC OUT /2 /2 RA1+/- RB1+/- RC1+/- RD1+/- RE1+/- R1+/- VSYNC OUT /2 Data Rate /2 RA2+/- RB2+/- RC2+/- RD2+/- RE2+/- L ix Data Rate /2 RA2+/- RB2+/- RC2+/- RD2+/- RE2+/- L ix Fig2-13 Fig2-14 Dual In / Dual Out VSYNC OUT RA1+/- RB1+/- RC1+/- RD1+/- RE1+/- R1+/- RA2+/- RB2+/- Data Rate RC2+/- RD2+/- RE2+/- Data Rate Fig2-15 Copyright 2008 THine Electronics, Inc. 5/16 THine Electronics, Inc.

6 3. TTL Timing Diagram Following are TTL data input timing example or UXGA(1600 x 1200). Dot R1x/G1x/B1x #1 #3 #5 # 1595 #159 #1599 R2x/G2x/B2x #2 #4 #6 # #1598 #1600 #1 #2 #1599 #1600 TFT Panel (1600 x 1200) Note: R1x G1x B1x R2x G2x B2x MSB R19 G19 B19 R29 G29 B29 R18 G18 B18 R28 G28 B28 R1 G1 B1 R2 G2 B2 R16 G16 B16 R26 G26 B26 R15 G15 B15 R25 G25 B25 R14 G14 B14 R24 G24 B24 R13 G13 B13 R23 G23 B23 R12 G12 B12 R22 G22 B22 R11 G11 B11 R21 G21 B21 LSB R G B R20 G20 B20 Copyright 2008 THine Electronics, Inc. 6/16 THine Electronics, Inc.

7 4. Example o System Diagram 1) Single Link(TTL/CMOS Input: 20~135MHz) Example : : Falling edge / bit / Single in(ttl)-single out(lvds) / Distribution O : Falling edge / bit / Single in(lvds)-single out(ttl) PCB(Transmitter) PCB(Receiver) JP IN1 1 *3 *1 0.01uF RS L MO3 MO MO MO0 ASYNC PRBS N/C IN1 IN2 1 2 VSYNC2 P P RD2- RD2+ TE1- TE1+ TA2- TA2+ TB2- TB2+ TC2- TC2+ T2- T2+ TD2- TD2+ TE2- TE2+ 0ohm Cable or PCB trace *4 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm L P P TA1- TA1+ TB1- TB1+ TC1- TC1+ T1- T1+ TD1- TD1+ RA1- RA1+ RB1- RB1+ RC1- RC1+ R- R+ RD1- RD1+ RE1- RE1+ RA2- RA2+ RB2- RB2+ RC2- RC2+ RE2- RE2+ MO MO MO0 OUT VSYNC C C OUT 1 *1 : I RS pin tied to, LVDS swing is 350mV. I RS pin tied to, LVDS swing is 200mV. : Reer to datasheet *3: L/H ix or *4: Connect each PCB : CONT## pins can be used as data. Fig. 4-1 Copyright 2008 THine Electronics, Inc. /16 THine Electronics, Inc.

8 2) Single Link (TTL/CMOS Input: ~6.5MHz) Example : : Falling edge / bit / Dual in(ttl)-single out(lvds) : Falling edge / bit / Single in(lvds)-dual out(ttl) PCB(Transmitter) PCB(Receiver) JP IN1 1 *1 *3 0.01uF RS MO3 MO MO MO0 ASYNC PRBS N/C IN1 IN2 1 2 VSYNC2 L P P RD2- RD2+ TE1- TE1+ TA2- TA2+ TB2- TB2+ TC2- TC2+ T2- T2+ TD2- TD2+ TE2- TE2+ 0ohm Cable or PCB trace *4 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm L P P TA1- TA1+ TB1- TB1+ TC1- TC1+ T1- T1+ TD1- TD1+ RA1- RA1+ RB1- RB1+ RC1- RC1+ R- R+ RD1- RD1+ RE1- RE1+ RA2- RA2+ RB2- RB2+ RC2- RC2+ RE2- RE2+ MO MO MO0 OUT VSYNC C C OUT 1 *1 : I RS pin tied to, LVDS swing is 350mV. I RS pin tied to, LVDS swing is 200mV. : Reer to datasheet *3: L/H ix or *4: Connect each PCB : CONT## pins can be used as data Fig. 4-2 Copyright 2008 THine Electronics, Inc. 8/16 THine Electronics, Inc.

9 3) Single Link (TTL/CMOS Input: 20~135MHz) Example : : Falling edge / 8bit / Dual in(ttl)-single out(lvds) : Falling edge / 8bit / Single in(lvds)-dual out(ttl) PCB(Transmitter) PCB(Receiver) JP IN1 8 R19 - R12 8 G19 - G12 B19 - B *3 *3 * uF RS MO3 MO MO MO0 ASYNC PRBS N/C IN1 IN2 R19 - R12 G19 - G12 B19 - B VSYNC2 R11 - R G11 - G B11 - B L P P RD2- RD2+ TE1- TE1+ TA2- TA2+ TB2- TB2+ TC2- TC2+ T2- T2+ TD2- TD2+ TE2- TE2+ 0ohm Cable or PCB trace *4 820ohm 0ohm 40ohm 0ohm 0ohm 0ohm 0ohm 0ohm L P P TA1- TA1+ TB1- TB1+ TC1- TC1+ T1- T1+ TD1- TD1+ RA1- RA1+ RB1- RB1+ RC1- RC1+ R- R+ RD1- RD1+ RE1- RE1+ RA2- RA2+ RB2- RB2+ RC2- RC2+ RE2- RE2+ MO MO MO0 OUT R19 - R12 G19 - G12 B19 - B12 VSYNC R11 - R R11 - R R11 - R C C OUT R19 - R12 G19 - G12 B19 - B12 1 *1 : I RS pin tied to, LVDS swing is 350mV. I RS pin tied to, LVDS swing is 200mV. : Reer to datasheet *4: Connect each PCB *3: L/H ix or : CONT## pins can be used as data Fig. 4-3 Copyright 2008 THine Electronics, Inc. 9/16 THine Electronics, Inc.

10 4) Dual Link (TTL/CMOS Input:40~150MHz(DDR o),20~5mhz(ddr on)) Example : : Falling edge/ bit / Single in(ttl)-dual out(lvds) / DDR O or On / Port Swtich On : Falling edge / bit / Dual in(lvds)-dual out(ttl) or Single Out / DDR O or On Note1: tint = ttcipn (n=integer) Note2: tint >= 4*tTCIP Note3: th >= 2k*tTCIP, tl >= 2m*tTCIP (k,m = integer) (tint = Period, ttcip = IN Period, th = High Time, tl = Low Time ) PCB(Transmitter) PCB(Receiver) JP *1 MO 0.01uF RS MO3 MO MO MO0 ASYNC L P P TA1- TA1+ TB1- TB1+ 0ohm Cable or PCB trace 0ohm 0ohm L P P RA1- RA1+ RB1- RB1+ MO MO MO0 C C MO MO0 PRBS TC1- TC1+ 0ohm RC1- RC1+ OUT OUT IN2 N/C IN1 IN2 T1- T1+ TD1- TD1+ 0ohm 0ohm 0ohm R- R+ RD1- RD1+ TE1- TE1+ RE1- RE1+ VSYNC 2 VSYNC2 *3 2 VSYNC2 1 2 VSYNC2 *4 0ohm 0ohm 0ohm 0ohm 0ohm TA2- TA2+ TB2- TB2+ TC2- TC2+ T2- T2+ TD2- TD2+ TE2- TE2+ RA2- RA2+ RB2- RB2+ RC2- RC2+ RD2- RD2+ RE2- RE2+ or Open When Dual in Single out mode Fig. 4-4 *1 : I RS pin tied to, LVDS swing is 350mV. I RS pin tied to, LVDS swing is 200mV. : Reer to datasheet *3: L/H ix or *4: Connect each PCB : CONT## pins can be used as data Copyright 2008 THine Electronics, Inc. /16 THine Electronics, Inc.

11 5) Dual Link (TTL/CMOS Input: 20~135MHz) Example : : Falling edge / bit / Dual in(ttl)-dual out(lvds) : Falling edge / bit / Dual in(lvds)-dual out(ttl) PCB(Transmitter) PCB(Receiver) JP *1 0.01uF RS L MO3 MO MO MO0 ASYNC P P TA1- TA1+ TB1- TB1+ 0ohm Cable or PCB trace 0ohm 0ohm L P P RA1- RA1+ RB1- RB1+ MO MO MO0 C C IN1 PRBS N/C IN1 IN2 TC1- TC1+ T1- T1+ TD1- TD1+ 0ohm 0ohm 0ohm 0ohm RC1- RC1+ R- R+ RD1- RD1+ TE1- TE1+ RE1- RE1+ *4 OUT VSYNC OUT R19 - R20 G19 - G20 B19 - B VSYNC2 *4 *4 0ohm 0ohm 0ohm 0ohm 0ohm TA2- TA2+ TB2- TB2+ TC2- TC2+ T2- T2+ TD2- TD2+ TE2- TE2+ RA2- RA2+ RB2- RB2+ RC2- RC2+ RD2- RD2+ RE2- RE2+ *4 *3 *1 : I RS pin tied to, LVDS swing is 350mV. I RS pin tied to, LVDS swing is 200mV. : Reer to datasheet *3: Connect each PCB *4: CONT## pins can be used as data Fig. 4-5 Copyright 2008 THine Electronics, Inc. 11/16 THine Electronics, Inc.

12 6) Asynchronous Mode (TTL/CMOS Input: 20~112MHz) Example : : Falling edge / bit / Asynchronous Mode / Crosspoint Switch On THC63LVD4S : Falling edge / bit (3.3V) PCB(Transmitter) JP IN1 IN2 *1 0.01uF RS MO3 MO MO MO0 ASYNC PRBS N/C IN1 IN2 LVDS LVDS PLL PLL TA1- TA1+ TB1- TB1+ TC1- TC1+ T1- T1+ TD1- TD1+ TE1- TE1+ 0ohm Cable or PCB trace PCB(Receiver) 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm THC63LVD4S RA- RA+ RB- RB+ RC- RC+ R- R+ RD- RD+ RE- RE+ L P P OUT RA6 - RA0 RB6 - RB0 RC6 - RC0 RD6 - RD0 RE6 - RE0 (2.5V) *4 OUT2 TA26 - TA20 TB26 - TB20 TC26 - TC20 TD26 - TD20 TE26 - TE20 TA16 - TA TB16 - TB TC16 - TC TD16 - TD TE16 - TE TA26 - TA20 TB26 - TB20 TC26 - TC20 TD26 - TD20 TE26 - TE20 TA16 - TA TB16 - TB TC16 - TC TD16 - TD TE16 - TE TA26 - TA20 TB26 - TB20 TC26 - TC20 TD26 - TD20 TE26 - TE20 TA2- TA2+ TB2- TB2+ TC2- TC2+ T2- T2+ TD2- TD2+ TE2- TE2+ *3 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm THC63LVD4S RA- RA+ RB- RB+ RC- RC+ R- R+ RD- RD+ RE- RE+ L P P OUT RA6 - RA0 RB6 - RB0 RC6 - RC0 RD6 - RD0 RE6 - RE0 (2.5V) *4 OUT1 TA16 - TA TB16 - TB TC16 - TC TD16 - TD TE16 - TE *1 : I RS pin tied to, LVDS swing is 350mV. I RS pin tied to, LVDS swing is 200mV. : Reer to datasheet *3: Connect each PCB *4: Supply voltage o THC63LVD4S is 2.5V(Typ). Fig. 4-6 Copyright 2008 THine Electronics, Inc. 12/16 THine Electronics, Inc.

13 5. Note 1)Output Control Input(TTL) Output(LVDS) L Open or L Input H Open or H Input *1 Data, Out (THC63LVD4S) Input(LVDS) Output(TTL) L L Open or L L Input L H Open or All Low L H Input All Low H L Open or H L Input H H Open or All Low H H Input *1 Data, Out *1 With in the range o Recommended Operating Conditions. Reer to Recommended Operating Conditions on data sheet. Without the range, the Output(TTL) may unixed Data, Out. Open or Input Data channel outputs unixed Data(TTL). 2)Power On Sequence Power on ater. I it is not avoidable, please contact to mspsupport@thine.co.jp (or FAE mailing list) 3)Cable Connection and Disconnection Don t connect and disconnect the LVDS cable, when the power is supplied to the system. 4) Connection Connect the each o the PCB which and on it. It is better or EMI reduction to place cable as close to LVDS cable as possible. Copyright 2008 THine Electronics, Inc. 13/16 THine Electronics, Inc.

14 5)Multi Drop Connection Multi drop connection is not recommended. T+ T- 6)Asynchronous use Asynchronous use such as ollowing systems are not recommended. I it is not avoidable, please contact to mspsupport@thine.co.jp (or FAE mailing list) OUT T+ T- LVDS-Rx OUT IC OUT T+ T- LVDS-Rx IC OUT LVDS-Tx T+ T- OUT IC OUT LVDS-Tx T+ T- IC OUT T+ T- IC OUT T+ T- IC T+ T- OUT IC T+ T- IC Copyright 2008 THine Electronics, Inc. 14/16 THine Electronics, Inc.

15 6. PCB Design Guide Line General Guideline Use 4 layer PCB (minimum). Locate by-pass capacitors adjacent to the device pins as close as possible. Make the loop minimum which is consist o Power line and Gnd line. LVDS Traces Interconnecting media between Transmitter and Receiver (i.e. PCB trace, connector, and cable) should be well balanced.(keep all these dierential impedance and the length o media as same as possible.). Minimize the distance between traces o a pair (S1) to maximize common mode rejection. See ollowing igure. Place adjacent LVDS trace pair at least twice (>2 x S1) as ar away as much as possible. Avoid 90 degree bends. Minimize the number o VIA on LVDS traces. Match impedance o PCB trace, connector, media (cable) and termination to minimize relections (emissions) or cabled applications (typically 0ohm dierential mode characteristic impedance). Place Terminal Resister adjacent to the Receiver. S1 >2 x S1 +Signal -Signal +Signal -Signal Copyright 2008 THine Electronics, Inc. 15/16 THine Electronics, Inc.

16 Attentions and Requests 1. The product speciications described in this material are subject to change without prior notice. 2. The circuit diagrams described in this material are examples o the application which may not always apply to the customer's design. We are not responsible or possible errors and omissions in this material. Please note i errors or omissions should be ound in this material, we may not be able to correct them immediately. 3. This material contains our copy right, know-how or other proprietary. Copying or disclosing to third parties the contents o this material without our prior permission is prohibited. 4. Note that i inringement o any third party's industrial ownership should occur by using this product, we will be exempted rom the responsibility unless it directly relates to the production process or unctions o the product. 5. This product is presumed to be used or general electric equipment, not or the applications which require very high reliability (including medical equipment directly concerning people's lie, aerospace equipment, or nuclear control equipment). Also, when using this product or the equipment concerned with the control and saety o the transportation means, the traic signal equipment, or various Types o saety equipment, please do it ater applying appropriate measures to the product. 6. Despite our utmost eorts to improve the quality and reliability o the product, aults will occur with a certain small probability, which is inevitable to a semi-conductor product. Thereore, you are encouraged to have suiciently redundant or error preventive design applied to the use o the product so as not to have our product cause any social or public damage.. Please note that this product is not designed to be radiation-proo. 8. Customers are asked, i required, to judge by themselves i this product alls under the category o strategic goods under the Foreign Exchange and Foreign Trade Control Law. THine Electronics, Inc. sales@thine.co.jp Copyright 2008 THine Electronics, Inc. 16/16 THine Electronics, Inc.

THC63LVD823(B)/THC63LVD824A Application Note

THC63LVD823(B)/THC63LVD824A Application Note Application Note / Application Note Mode settings, System Diagram and PCB Design Guide Copyright 010 THine Electronics, Inc. 1/13 THine Electronics, Inc. 1.Mode Settings Input/Output Single In/ Single