The MIT Communications Technology Roadmap Program IPI TWG Report

Transcription

1 The MIT Communications Technology Roadmap Program IPI TWG Report May 19, 2006 Louay Eldada Integration, Packaging & Interconnection Technology Working Group CTO, VP Engineering DuPont Photonics Chair, IPI TWG

2 IPI TWG Participants Analog Devices Clayton & Associates Corning DuPont Photonics Technologies Fairchild Semiconductor Fujitsu Intel Corporation MIT Northrop Grumman University of Oxford

3 IPI TWG Participants Analog Devices: Tremont Miao, Shrenik Deliwala Clayton & Associates: Rick Clayton Corning: Jay Sutherland, Rich Grzybowski DuPont Photonics Technologies: Louay Eldada (Chair) Fairchild Semiconductor: Rajeev Joshi Fujitsu: (2 nd Chair?) Intel Corporation: Jerry Bautista MIT: Kim Kimerling, Randy Kirchain, Buzz Kenney, Fatwa Abdi Northrop Grumman: Joe Bresman University of Oxford: Dominic O'Brien

4 Goal & Scope of the TWG Goal: The IPI TWG will develop a strategic roadmap that identifies critical technical requirements of next-generation integration and packaging, and details technological opportunities to meet those requirements economically. Scope: Evaluate the use of optics in a broad range of segments Identify integration and packaging issues Develop a strategic roadmap Develop an action plan to address barriers

5 Output Paper identifying current technical challenges, future technical requirements & possibly converged integration and packaging strategies for emerging markets, covering 3/5-7/10 year time horizons. IPI TWG student research project will help answers these questions. Strategic Roadmap with market-based technical challenges, opportunities and barriers to implement a converged architecture, timeline by which the challenges must be addressed, and impacts if industry cannot meet the roadmaps or convergence opportunities. Prototype of pluggable optical module addressing some of the needs of an emerging market, developed at MIT ME department.

6 Overview Current market volumes for optical components in communication & computing networks are insufficient to support a robust industry, particularly level of R&D required to realize full potential of photonics. Emerging applications can provide a sizable TAM, but are cost sensitive. Key barrier to realizing cost targets is high cost of OE integration & packaging. To overcome this issue, IPI TWG is characterizing the technical requirements for integration and packaging in emerging markets and implementation strategies that can meet these requirements at low cost.

7 Overview $100 s / channel Optical 1 s / pin Copper Chip to Chip 1 50 cm Metro & Long Haul Billions km cm Volumes Board to Board Millions Rack to Rack 1 to 100 m Thousands Decreasing Distances Drive optical to high volumes and low costs

8 Compute Platform Computational power demands distributed processing for reasons of speed and power (CMOS frequencies will not exceed 10 GHz) Parallel processing for high speed computing will adopt architecture based on low-latency optical connections Chip-board-backplane-board-chip connections require 2 types of interconnects: chip-to-board board-to-board

9 Packaging Cost Electronics Optoelectronics What drives the optoelectronic packaging costs to be so high?

10 Packaging Cost Possible causes of high packaging cost: Lack of standardization Many package types, low demand per package Lack of common optics technology base Too few MSAs Too many package types per MSA Form Factor Difficult & costly processes No standard manufacturing processes No consensus as to the best practices 20-year component life standard of the telecom industry is inconsistent with the 3-5 year life cycle of equipment Low manufacturing capacity utilization Need few optical foundries with efficient supply chain management

11 Lack of Standardization in Packaging 2005 Standard Packages: TO, Butterfly, MiniDIL, etc. Form Factor Types GBIC 20 SFF 143 SFP 96 XFP 5 Misc. MSA 50 Other 17 Finisar, JDSU, Infineon, Excelight, Agilent, Intel

12 Electronic-Photonic ICs (EPICs) EPIC Boundaries/Assumptions/Approaches in TWG: Platform: CMOS Electronic-photonic co-packaging for next 10 years (eventually true convergence) Photonics built on / packaged with finished CMOS chip Pluggable solutions preferred Packaging approach: system in package When WDM used, Mux/Demux inside package to reduce number of optical pins

13 Technology Analysis Package Technical Requirements (TWG): Data rate of 10 Gbps 100 optical channels optical pins per pluggable solution Power dissipation below 10 W Critical Requirements for OE Packages: Good alignment for efficient optical link performance Stringent thermal management

14 Technology Analysis Challenges: Material (CTE matching) Monolithic materials vs. novel composites, e.g., MMC, PMC, CMC, CCC Design Efficient optical coupling Is self-alignment sufficient? Performance Heat dissipation Cooler?

15 Market Analysis worldwide market composition of optoelectronic industry 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% Optical (Solar) Energy Medical care/welfare Info-Communications Processing Environment/Sensing Optical Memory Input & Output Display/Lighting Total Numbers in US$B

16 Initial Focal Topics Emerging Applications Needing Pluggable High-Density Optics Application 1: Pluggable high-end processors Example: Processor with 5 bi-directional spatial Gb/s each way (140 bits wide x 10 Gb/s per channel), for 14 Tb/s total I/O (1400 Gb/s) Application 2: Pluggable large-matrix optical cross-connects Example: 1024x1024 OXC EPIC with 16 optical I/O ports for degree-8 Gb/s per aggregate line (128 DWDM channels x 10 Gb/s per channel), for Tb/s total I/O (2048 Gb/s); channel Mux/Demux pairs, 128 8x8 switches & electronic control circuitry integrated in module Application 3: Volume interconnects for high-slot-count backplanes Example: 1000 spatial optical channels on backplane, 100 optical pins to/from each board Optical I/O Ports: 8-24/Module, /Board, /Backplane

17 Pluggable Optical Modules Today s Pluggable Modules: 2-12 Optical I/O Ports QSFP (Quad Small Form-factor Pluggable) MSA: Initial release: May channel pluggable optical transceiver module, replaces 4 SFP modules Package and Electrical/Optical Connectors derived from designs in production Electrical connection made through a 38-pin connector Optical interface is via MPO connector

18 Pluggable Optical Interconnects Today s Pluggable Backplane Interconnects: 144 Lines Modified MT Connector for Polymer Waveguide Strips 144-Channel Polymer Optical Backplane Interconnects: Development completed in 2002 Optical Connectors derived from designs in production: 144-channel Super MT connector for strip-to-strip connection 24-channel modified MT connector (slot vs. fiber ferrules) for waveguide strip to fiber array connection Developed by using Polyguide

19 Emerging Market Requirements IPI TWG will identify requirements for integration and packaging in emerging applications over 3, 5-7, & 10 year horizons Metrics 3 Years 5-7 Years 10 Years Density of EPIC electronic circuit Density of EPIC photonic circuit Hybrid vs. monolithic Static / dynamic / active photonics* Role of electronics** Role of photonics** Location of photonics*** Form factor of package Electrical pin count Photonic pin count Wavelength SM vs. MM Parallel vs. WDM Multicast capability Signal bandwidth Distance Aggregate capacity Latency Crosstalk Pluggability Number of insertions (if pluggable) Wave solderability Environment (temperature, vibration, etc.) Reliability / required lifetime Electrical power budget Photonic power budget Cost expectation * Static: interconnects, splitters, couplers, etc.; Dynamics: switchable / tunable elements, modulators, etc.; Actives: sources, amplifiers, detectors, etc. ** Interconnection, signal processing, combination, etc. *** e.g., VCSEL in package, in socket, in separate package on board Quantity of optical signals destined to different locations Plug and play interconnection $/Gbps, differential cost, etc. Matrix will be populated for each emerging application

20 Next Steps Identify opportunities for convergence: Identify opportunities where converged specifications and architectures can address multiple markets. Develop Barrier Analysis: Identify barriers that could preclude the adoption of necessary integration and packaging technology, e.g., lack of interconnection hierarchy for electronic and photonic signal transmission. Develop an Action Plan: Develop a strategic roadmap, with multiple layers of risk, to proactively address each barrier. Communicate this plan broadly to the optics industry.

21 Participation in IPI TWG If interested in participating in the IPI TWG and helping shape the roadmap for Electronic-Photonic Integration and Packaging, contact: Louay Eldada Meeting frequency/times: Teleconference every 6 weeks (Fridays 11 AM Eastern) Meetings twice a year at MIT (May & November)