PSMC Roadmap For Integrated Photonics Manufacturing

Transcription

1 PSMC Roadmap For Integrated Photonics Manufacturing Richard Otte Promex Industries Inc. Santa Clara California For the Photonics Systems Manufacturing Consortium April 21, 2016

2 Meeting the Grand Challenges in Integrated Silicon Photonics Roadmap Participants as of December 13, Countries 481 Individuals 185 organizations

3 Steps in PSMC Roadmapping Process 1.Scope and Analyze the Situation 2.Identify the Grand Challenges and Needs 3.Identify Paradigm Shifts and Strategic Concerns 4.Develop Strategic Recommendations for all Stakeholders 5.Provide these recommendations to AIM Photonics to aid in focusing and prioritizing their Technical Plans for Research and Development 2

4 Scope of this Presentation This Presentation Covers the Grand Challenges identified by the PSMC TWGs. The Grand Technical Challenges: Reducing Power per function Reducing Cost Decreasing Latency Increasing physical bandwidth density More detailed guidance is available in the PSMC Written Roadmap. 3

5 Grand Challenges Identified by the PSMC Product Emulator Groups (PEGs) Data Center Applications Internet of Things Applications

6 The Technology Needs Differ by PEG Data Centers The data center servers require heterogeneous integration of memory, logic, power controllers and photonics in 3D-SiP package architecture to meet applications requirements in a controlled environment. The solution must also provide for packaging of replacements for existing top of rack components. These solutions must include SiP based traffic analysis supporting data path switching decisions, selecting between photonic and electronic data paths and between packet switching and circuit switching. Internet of Things The internet of things (IoT) will require a package for heterogeneous integration of sensors, RF components, memory and photonics in 3D-SiP architectures. The package must enable a general purpose SiP IoT hub packaging for uncontrolled environments. This capability will include energy scavenging to power the IoT hub in many cases and redundancy to ensure long term service free reliability. Product Emulators are Used To Drive Technology Requirements 5

7 Grand Challenges Identified by the PSMC Technical Working Groups (TWGs) Monolithic Integration Integrated Silicon Photonics Packaging Interconnections Assembly and Test

8 Monolithic Integration Professor Lionel Kimerling

9 Key Attributes Function TxRx Comm/Comp/Sense/Image E-P Hybrid Coherent WDM Embedded Embedded Matrix Switch 8x8 (VICTORIES) 32x32 Embedded Processor Signal Conditioning FFT Embedded Cost $1/Gbps $0.1/Gbps $0.01/Gbps BW density 30 Tb/s/cm 2 (PETRA) Energy 10pJ/b 1pJ/b 100fJ/b Reach Chip Escape Data Rate Small Commercial Demand for Technically Viable Optical Solutions 1000km 100m 1cm 40 Gbps 400Gbps NOW NEXT LIMITS Commercially Viable Optical Solutions Deployed 128Tbps No Technically Viable Optical Solutions Exist 8

10 Difficult Challenges: Monolithic Integration Light Source Process Tools (193nm litho, 65nm CMOS) Universal E-P CAD for photonic integration Electronic-Photonic process integration Power distribution Athermalization Wafer-level inspection and test Scalable (single mode, E-P) packaging solution Interconnection: fiber, optical, electronic Throughput, Yield and Reliability 9

11 Difficult Challenge: Light Source Do we want one laser or many lasers? Do we want one wavelength or multiple wavelengths? Can we integrate lasers without epitaxy? The gain medium for the light source is the crucial material. What are the materials system compatibility issues? Can we use wafer to wafer bonding and not lose the scalability? 1 0

12 Difficult Challenge: EDA Tools Goal: tape out functionality as with digital circuits today. difficult for analog electronic circuits essential to meet energy targets essential for SDN-like control functions essential for ramp of good enough photonics Fully integrated, seamless compatibility with digital/analog CAD tools. lumped element device/circuit models process integration optical impedance matching 1 1

13 Integrated Silicon Photonics Packaging Bill Bottoms

14 What Has To Be Packaged? The components that will be assembled into the resulting complex 3D-SiPs may include: Monolithic photonic ICs (PICs)(includes photonics, electronics and plasmonics) Discrete optical components not integrated in the SiPh-ICs. Si based logic and memory ICs MEMS devices Sensors (including a growing list of photonic sensors) GaN power controller circuits RF circuits Passive components (including integrated passive devices) Direct bandgap semiconductor lasers Packaging Functions Optical interconnects to and from the outside world Electrical interconnects to and from the outside world Thermal paths to and from the outside world 1 3

15 What Has To Be Packaged? The components that will be assembled into the resulting complex 3D-SiPs may include: Monolithic photonic ICs (PICs)(includes photonics, electronics and plasmonics) Discrete optical components not integrated in the SiPh-ICs. Si based logic and memory ICs MEMS devices Sensors (including a growing list of photonic sensors) GaN power controller circuits RF circuits Passive components (including integrated passive devices) New devices and new materials will be added over the 15 year life of this Roadmap. Direct bandgap semiconductor lasers Packaging Functions Optical interconnects to and from the outside world Electrical interconnects to and from the outside world Thermal paths to and from the outside world 1 4

16 Packaging Technology Needs and Gaps Co-design and simulation tools for heterogeneous integration Low cost electrical/photonic package substrates Power reduction at system level Increased parallelism in manufacturing processes Supply Chain supporting low cost package production 1 5

17 Interconnections: Connectors, Cable Assemblies & Printed Circuits John MacWilliams

18 Packaging Challenges Impact Connections: Cu Optical Transition at IO Port: NOW Circuit Functions are Disaggregated: SOON CPU/ASIC Embeds Optical Interconnect: FUTURE Fiber Optic Connections: As Few as Possible 1 7

19 Solutions to Interconnect Challenges: Connector/Cable Assembly Cost Reductions Volume-Dependent: 10 5 or 10 6 Standardization Automation Tooling Investments Transceiver Cost Reduction Device OEM SiPh Users Group! EMS Materials Substrates Connectors Optical Organic PCB Technology & Cost Packaging: Cables or Waveguides? Volume Commitments Process Linkages: WG Materials OPCB Makers OPCB Connector Developments Chip/SiP/PoP Level Optical Interconnect Technology Linkages Needed: Device Package Substrate Connector Manufacturers 1 8

20 Top Priority Interconnect Gap List: Parallel optical solutions, especially transceivers, require lower cost options for on-chip/off- chip and on board applications Single mode fiber from backplane through the data center. Organic Substrate Technology: Rigid.Flex..Fly- Over.Embedded Wave Guide Matching Connector Technology for Vertical u-via Connections to Embedded WG A physical architecture able to operate at 100Gb/s within Rack and 1Tb/s Rack-to-Rack. On-to and off-of chip data transmission methods for composite rates >5Tb/s that are hard to accommodate electrically due to approximately 25 Gb/s CMOS rate limit per I/O channel 1 9

21 Assembly and Test Richard Otte

22 Assembly & Test, Key Attributes Cost of Parts $$s cents # of Parts 10 s <5 Assy Time minutes many seconds few seconds Tolerances 0.5 micron 0.05 micron Assy Set Up Assy Equip Cost hours $50K to $1000K minutes <$200K SM Fiber Attach many minutes minutes seconds Test Time minutes/unit seconds/unit Small Commercial Demand for Technically Viable Optical Solutions NOW NEXT LIMITS Commercially Viable Optical Solutions Deployed Implementation Vision: dedicated materials, parts, tool suppliers; focus on yield, throughput and utilization. No Technically Viable Optical Solutions Exist 2 1

23 Why Assembly is Needed Since We Do Not Yet Know How to Provide All Needed Functionality with Integration, Heterogeneous Integration Is Needed. That Means Assembly, and that Means $$$!! 2 2

24 Optical vs Electronic Needs Optical products Differ from Electronic products Single Mode assemblies require sub micron assembly accuracy and mechanical stability. Assemblies often use the Z axis as well as X & Y. Cleanliness to minimize light loss and scattering by particles and surface contaminants is needed. A broader variety of parts and processes are used. Production volumes are lower. Notice that If electrical conductors maintain continuity, they can flex with temperature and mechanical stress. Historically, electronic devices have been designed to flex under these stresses!! So The TWG addresses the sub micron accuracy and stability required in many optical products. 2 3

25 Low Cost Starts with Design Minimize Part Count & Assembly Steps Eliminate Pigtails!!! Use parallel fabrication and assembly methods Choose Parts with: dimensional consistency location reference points Choose Robust Assembly Processes evaluate part specifications and dimensional tolerances maximize the tolerances required 2 4

26 Grand Challenges, Assembly & Test Developing the Right Mind Set: Move from individual parts to integration Eliminating Pigtails Achieving 0.05 micron Tolerances Improving Design Capability Training Designers to Design For Manufacturing Providing Material Properties Developing Optical Specific Assembly Equipment Minimize Assembly & Setup Time Developing The Low Cost High Accuracy Part Supply Chain Developing Standards Conceiving of New Applications 2 5

27 Strategic Recommendations from the PSMC Roadmap

28 Strategic Recommendation Focus Projects on Addressing the Grand Challenges Reduction in Power per function Reduction in Cost Decrease Latency Increased physical bandwidth density Address challenges that the supply chain will not achieve in time to address the quantified industrial needs in the PSMC Roadmap Design Tools Manufacturing Technology Materials Development Supply Chain Consolidation through Industry Standards 2 7

29 PSMC: What Next?

30 The Future of PSMC PSMC #1 ends April 30, 2016 with Submission of the Written Roadmap to NIST. PSMC #2 Continues the Roadmap effort as Part of AIM-IP. PSMC #2 will Expand and Synchronize with AIM-IP: More PEGs More TWGs Watch for Further Developments 2 9

31 Thank You for your Attention & Interest

32 Contacts: Masahiro Tsuriya Robert Pfahl Richard Otte