Technical Note NAND Flash Performance Increase with PROGRAM PAGE CACHE MODE Command
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- Winfred Harrell
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1 Technical Note NAND Flash Performance Increase with PROGRAM PAGE CACHE MODE Command TN-29-14: Increasing NAND Flash Performance Overview Overview NAND Flash devices are designed for applications requiring nonvolatile, high-density, solid-state storage memory. While NAND Flash may meet speed requirements of traditional applications, many newer applications require faster data processing capabilities. For these applications, Micron NAND Flash delivers higher data throughput using PROGRAM PAGE CACHE MODE operation. Cache programming works by pipelining data to the NAND Flash device. Pipelining involves inputting a page (2KB) of data to the cache register and then transferring this data to the data register when the cache programming command is issued. When the transfer is complete, the cache register is available to receive new data input while the data register simultaneously programs the NAND Flash array. Typical page-programming time ( t PROG) for Micron NAND Flash devices is approximately 300µs for a 2KB page of data. PROGRAM PAGE CACHE MODE operation can improve data throughput by as much as 35 percent for x8 devices and 17 percent for x16 devices. This technical note discusses the benefits of PROGRAM PAGE CACHE MODE operations over normal PROGRAM PAGE operations. It provides specific timing examples and instructions for performing PROGRAM PAGE CACHE MODE operations. Normal PROGRAM PAGE Operation Micron NAND Flash devices have two command latch cycles and five address latch cycles, which are followed by up to or 1,056 words of data in a normal PROGRAM PAGE operation. Following the ADDRESS LATCH cycles, R/B# goes LOW for t PROG (a typical time of 300µs, up to a maximum time of 700µs). Timing details are provided in Tables 2 and 3 on page 5 for x8 devices and Tables 4 and 5 on page 6 for x16 devices. Data can be programmed sequentially, one byte or word per cycle, depending on the width configuration of the NAND Flash device. Assuming 50ns cycles, timing is shown in Figure 1 on page 2. tn2914_prog_page_cache_mode_perf_increase.fm - Rev.B 5/07 EN Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron s production data sheet specifications. All information discussed herein is provided on an as is basis, without warranties of any kind.
2 TN-29-14: Increasing NAND Flash Performance Figure 1: Normal PROGRAM PAGE Timing x8 Configurations (2 x 50ns) commands + (5 x 50ns) address + (2,112 x 50ns) data + 300µs t PROG = µs per page x16 Configurations (2 x 50ns) commands + (5 x 50ns) address + (1,056 x 50ns) data + 300µs t PROG = µs per page Figure 2: NAND Flash Typical PROGRAM PAGE Operation Timing CLE CE# t WC t ADL WE# t WB t PROG ALE RE# I/Ox 80h add 3 N M 10h 70h Status SERIAL DATA INPUT command 1 up to MB serial input PROGRAM command READ STATUS command R/B# x8 device: m = 2,111 byte x16 device: m = 1,055 byte Don t Care tn2914_prog_page_cache_mode_perf_increase.fm - Rev.B 5/07 EN Micron Technology, Inc. All rights reserved.
3 PROGRAM PAGE CACHE MODE Operation TN-29-14: Increasing NAND Flash Performance PROGRAM PAGE CACHE MODE operation begins with a PROGRAM PAGE CACHE MODE (80h-15h) command. Initially, data is copied into the cache register. When the 15h command completes, the data is transferred to the data register. Assuming that a page 0 address is issued in the PROGRAM PAGE CACHE MODE command, page 0 programming from the data register into the NAND Flash array begins when R/B# returns HIGH. When R/B# returns HIGH, another PROGRAM PAGE CACHE MODE command sequence can be issued to write new data to the cache register. The time that R/B# stays LOW is determined by the actual programming time. On the first programming pass, R/B# stays LOW for the time it takes to transfer data from the cache register to the data register. On subsequent passes prior to the last page, the data in the data register must be programmed into the NAND Flash memory array before additional data can be transferred from the cache register. When R/B# is used to determine programming status during PROGRAM PAGE CACHE MODE, a PROGRAM PAGE (80h-10h) command is used to program the last page of data. For the last cache programming sequence, R/B# stays LOW for t LPROG. Table 1 below and Figure 3 on page 4 provide signal and timing information required for PROGRAM PAGE CACHE MODE operations. For programming a single page, the PROGRAM PAGE CACHE MODE operation takes the same time as a regular PROGRAM PAGE operation (see tech note TN-29-01); however, for two or more pages, there is a significant performance gain using PROGRAM PAGE CACHE MODE. The following examples assume t CBSY is equal to t PROG (TYP) after the first t CBSY. Table 1: Timing Delays Parameter Description Typ Max Unit t PROG Data transfer from data register to NAND Flash array µs t CBSY Busy time for PROGRAM PAGE CACHE MODE µs t LPROG 1 Last-page programming time for PROGRAM PAGE CACHE MODE (see 2Gb NAND Flash data sheet) Notes: 1. t LPROG = t PROG (last page) + t PROG ((last - 1) page) - command load time (last page) - address load time (last page) - data load time (last page). tn2914_prog_page_cache_mode_perf_increase.fm - Rev.B 5/07 EN Micron Technology, Inc. All rights reserved.
4 TN-29-14: Increasing NAND Flash Performance 240-Pin DDR2 SDRAM UDIMM Figure 3: PROGRAM PAGE CACHE MODE Operation Timing CLE CE# twc tadl WE# twb tcbsy twb tprog ALE RE# I/Ox 80h 15h R/B# Serial data input add 3 N M N 80h 10h 70h Status Serial input PROGRAM PROGRAM Add 3 M Last page - 1 Last page Don t Care tn2914_prog_page_cache_mode_perf_increase.fm - Rev.B 5/07 EN Micron Technology, Inc. All rights reserved.
5 TN-29-14: Increasing NAND Flash Performance Table 2: Single-Block PROGRAM PAGE Operation Timing (x8) 50ns Cycle Time Process Repetitions Time Total Time Unit Command latch (80h) ns Address latch ns Program data cycles 2, ns Program data cycles total page µs Command latch (10h) ns R/B# LOW ( t PROG) typical µs Total time to program a page µs Total time to program a block ms Speed (programming 64 pages in a block) 5.2 MB/s Table 3: Single-Block PROGRAM PAGE CACHE MODE Operation Timing (x8) 50ns Cycle Time Process Repetitions Time Total Time Unit Command latch (80h) ns Address latch ns Program data cycles 2, ns Program data cycles total page µs Command latch (15h) ns R/B# LOW (1st t CBSY) µs Time to program page µs R/B# LOW ( t CBSY) typical µs Time to program page µs Time to program pages 2: ms R/B# LOW ( t LPROG) µs Time to program page µs Total time to program a block ms Speed (programming 64 pages in a block) 7.04 MB/s tn2914_prog_page_cache_mode_perf_increase.fm - Rev.B 5/07 EN Micron Technology, Inc. All rights reserved.
6 TN-29-14: Increasing NAND Flash Performance Table 4: Single-Block PROGRAM PAGE Operation Timing (x16) 50ns Cycle Time Process Repetitions Time Total Time Unit Command latch (80h) ns Address latch ns Program data cycles 1, ns Program data cycles total page µs Command latch (10h) ns R/B# LOW ( t PROG) µs Total time to program a page µs Total time to program a block ms Speed (programming 64 pages in a block) 5.98 MB/s Table 5 shows timing calculations for 50ns PROGRAM CLOCK cycles with PROGRAM PAGE CACHE MODE. Table 5: Single-Block PROGRAM PAGE CACHE MODE Operation Timing (x16) Process Number of Cycles Time/Cycle 50ns Cycle Time Total Time Timing for page 0 programming Command latch (80h) ns Address latch ns Program data cycles 1, ns Program data cycles total page µs Command latch (15h) ns R/B# LOW (1st t CBSY) µs Time to program page µs R/B# LOW ( t CBSY) µs Time to program page µs Time to program pages 2: ms R/B# LOW ( t LPROG) µs Time to program page µs Total time to program a block 19.2 ms Speed (programming 64 pages in a block) 7.04 MB/s Units Figure 4 on page 7 is a visual example that demonstrates the time savings associated with using PROGRAM PAGE CACHE MODE. tn2914_prog_page_cache_mode_perf_increase.fm - Rev.B 5/07 EN Micron Technology, Inc. All rights reserved.
7 TN-29-14: Increasing NAND Flash Performance 240-Pin DDR2 SDRAM UDIMM Figure 4: PROGRAM PAGE CACHE MODE Time Savings Program Page 80h 10h 80h 10h R/B# for Page 0 for Page 1 t PROG (300µs) t PROG (300µs) Program Page Cache Mode 80h 15h 80h 15h 80h 15h 80h for Page 0 for Page 1 for Page 2 R/B# t CBSY t CBSY t CBSY Time 0µs 100µs 200µs 300µs 400µs 500µs 600µs 700µs Commands Address Data Summary By using the PROGRAM PAGE CACHE MODE operation available in Micron NAND Flash devices, customers can realize programming performance gains and increase data throughput in their systems S. Federal Way, P.O. Box 6, Boise, ID , Tel: prodmktg@micron.com Customer Comment Line: Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. tn2914_prog_page_cache_mode_perf_increase.fm - Rev.B 5/07 EN Micron Technology, Inc. All rights reserved.
8 Revision History TN-29-14: Increasing NAND Flash Performance Revision History Rev. B /07 Overview on page 1: Updated description. Normal PROGRAM PAGE Operation on page 1: Added cross references. PROGRAM PAGE CACHE MODE Operation on page 3: Revised description and cross reference. Former Head-to-Head Program Modes Comparison and former Figure 5 on page 8: Deleted text and figure. Former Performance Increases and former Figure 6 on page 9: Deleted text and figure. Rev. A /06 Initial release. tn2914_prog_page_cache_mode_perf_increase.fm - Rev.B 5/07 EN Micron Technology, Inc. All rights reserved.
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