Enabled (both during preconditioning and measurement) 4KB for random writes, 2MB for sequential writes

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1 Technical Note Introduction e.mmc Validation and Use Model Performance Introduction This technical note describes performance measurement of the Micron automotive e.mmc 5.0 device during validation and use model simulation. Use model simulation performance results differ from Micron validation performance results (found in the appropriate Micron e.mmc data sheet) due to different testing conditions. This technical note also shows that use model performance can be improved by altering commands and chunk size distribution. Validation Performance Conditions used to validate Micron automotive e.mmc 5.0 performance are shown in the table below. See the appropriate Micron data sheet for e.mmc device performance specifications (with no system overhead). Table 1: Validation Conditions Feature Condition Notes Bus x8, HS400 (or other frequency conditions) 1 Ambient temperature 25 C Byte [167] of EXT_CSD register 1Fh 2 Cache Starting access address Data chunk sizes Random write performance span Enabled (both during preconditioning and measurement) Aligned to 4KB 4KB for random writes, 2MB for sequential writes 1GB 3 Notes: 1. Accesses are close-ended. 2. The device protects previously written data during power failure. 3. Data chunk size is defined as the total amount of user data transferred within a unique READ MULTIPLE or WRITE MULTIPLE command; 1000 accesses performed for each chunk size. 1 Products and specifications discussed herein are subject to change by Micron without notice.

2 e.mmc performance potential during actual application use can be evaluated by measuring the total time to complete all commands during use model simulation. Features of a typical infotainment use model (Use_A) are shown in the tables below. One use model loop represents one hour of application use. Table 2: Command Distribution per Loop Command Occurrence Percentage CMD % CMD18 126, % CMD % CMD % Table 3: Data Size per Loop Command READ WRITE Data Size MB 14.54MB Table 4: Command Access Type per Loop Command Access Type Occurrence Percentage Random read 27, % Sequential read 99, % Random write % Sequential write % 2

3 The figures below show chunk size distribution for each Use_A loop. Figure 1 shows that 4KB and 32KB are the most frequently used read chunk sizes (40.13% and 50.83% respectively), and Figure 2 shows that 2KB is the most frequently used write chunk size (94.24%). Figure 1: Read Chunk Size Occurrence per Loop Figure 2: Write Chunk Size Occurrence per Loop The table below shows that enabling cache reduces the total write time for one Use_A loop by three times. Table 5: Command Duration for One Use Model Loop Cache Enabled Cache Disabled READ commands 216s 216s WRITE commands 1.7s 5.1s All commands 217.7s 221.1s Note: 1. Time measured using HS400 mode, x8 DDR after a full sequential preconditioning performed. 3

4 Use Model Improvement To improve use model performance, one strategy is to attempt to use 100% sequential reads after 100% sequential write preconditioning, both with 4KB chunk size multiples and 4KB command address multiples. This ideal use model was used to improve upon Use_A, which only attempts to achieve 100% sequential reads and not 100% sequential writes, and can be referred to when configuring use model performance. Use_A was modified to create Use_B, which uses 100% sequential reads at 32KB and 100% sequential writes at 4KB. Use_B and Use_A have the same quantity of read data ( MB per loop) and of written data (14.54 MB per loop), but Use_B command and chunk size distribution have been improved. Table 6: Use_A and Use_B Feature Comparison per Loop Feature Use_A Use_B Data read per loop MB MB Data written per loop 14.54MB 14.54MB CMD17 percentage 0.02% 0.00% CMD18 percentage 95.02% 95.27% CMD24 percentage 0.00% 0.00% CMD25 percentage 4.96% 4.73% CMD18 + CMD17 occurrence 126,558 75,055 CMD25 occurrence Random reads 21.53% 0% Sequential reads 78.47% 100% Random writes 99.83% 0% Sequential writes 0.17% 100% Read chunk size ~40% at 4KB, ~50% at 32KB 100% at 32KB Written chunk size ~94% at 2KB 100% at 4KB The table below shows use model performance improvement when switching to only sequential reads/writes and aligning chunk size distribution in Use_B. Notice that WRITE command improvement is more evident because only 0.17% of writes in Use_A were sequential. Table 7: Use_A and Use_B Command Duration Comparison for One Use Model Loop Use_A Duration Use_B Duration Cache state Cache enabled Cache disabled Cache enabled Cache disabled READ commands 216s 216s 211s 211s WRITE commands 1.7s 5.1s 1.2s 2.9s All commands 217.7s 221.1s 212.2s 213.9s Note: 1. Time measured using HS400 mode, x8 DDR after a full sequential preconditioning performed. 4

5 Figure 3: Use_A and Use_B WRITE Command Duration Comparison for One Use Model Loop 6 5 Duration (s) Use Improvement 0 Use_A cache enabled Use_A cache disabled Use Model Use_B cache enabled Use_B cache disabled 5

6 Revision History Revision History Rev. A 05/16 Initial release 8000 S. Federal Way, P.O. Box 6, Boise, ID , Tel: Sales inquiries: Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 6