Overview of Computer Architecture & Organization. Co Attained : CO1 Hours required : 07 Self study : 10 hrs

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1 Overview of Computer Architecture & Organization Co Attained : CO1 Hours required : 07 Self study : 10 hrs

2 Syllabus 1. Introduction of Computer Organization and Architecture. 2. Basic organization of computer and block level description of the functional units. 3. Evolution of Computers, Von Neumann model. 4. Performance measure of Computer Architecture. 5. Architecture of 8086 family, Hardware Design, Minimum mode & Maximum mode of Operation. 7. Study of bus controller 8288 & its use in Maximum mode.

3 L1. Introduction of Computer Organization and Architecture. Computer Architecture and Organization is the study of internal working, structuring and implementation of a computer system. Architecture in computer system, same as anywhere else, refers to the externally visual attributes of the system. Externally visual attributes, here in computer science, mean the way a system is visible to the logic of programs (not the human eyes!).

4 L1. Continue.. Organization of computer system is the way of practical implementation which results in realization of architectural specifications of a computer system. In more general language, Architecture of computer system can be considered as a catalog of tools available for any operator using the system, while Organization will be the way the system is structured so that all those cataloged tools can be used, and that in an efficient fashion.

5 L1. Continue.. Architecture is those attributes visible to the programmer Instruction set, number of bits used for data representation, I/O mechanisms, addressing techniques. e.g. Is there a multiply instruction? Organization is how features are implemented Control signals, interfaces, memory technology. e.g. Is there a hardware multiply unit or is it done by repeated addition?

6 L1. Continue.. All Intel x86 family share the same basic architecture The IBM System/370 family share the same basic architecture This gives code compatibility... at least backwards Organization differs within members of the same family, e.g. floating point numerical coprocessors with names like 8087, and With very few exceptions, the and subsequent x86 processors then integrated this x87 functionality on chip.

7 L1. Continue.. Structure and Function Structure is the way in which components relate to each other Function is the operation of individual components as part of the structure

8 L1. Structure Top Level

9 L1. Structure- The CPU

10 L1. Structure- The Control Unit

11 L1. Function General computer functions: Data processing Data storage Data movement Control

12 L1.Operation : Data Movement I/O (peripherals directly attached) through Communications/Networking (communication lines) E.g. Camera attached to a PC, sending the frames to a window on the screen of the same PC.

13 L1.Operation : Data Storage Playing an mp3 file stored in memory to earphones attached to the same PC.

14 L1.Operation : Processing from/to storage Any number-crunching application that takes data from memory and stores the result back in memory.

15 L1.Operation : Processing from storage to I/O Receiving packets over a network interface, verifying their CRC, then storing them in memory.

16 L2.Basic organization of computer and block level description of the functional units A computer is a fast and accurate device, which can accept data, store data, process them and give, desired results as output. The computer is organized into four units as shown in the diagram.

18 L2. Input Unit: Any device designed to assist in the entry of data into a computer is known as input device. Input devices convert data from any convenient external format into binary codes that a computer can store and manipulate internally. Some of the most common, most popularly used devices are following. a) Mouse b) Light Pen c) Touch Screen d) Keyboard e) Scanner f) OCR and MICR g) Bar Code Reader h) Joy Stick etc.

19 L2. Output unit Any peripheral device that converts the stored binary coded data into convenient external forms as test and pictures are known as Output device. Some of the most popularly used Output devices are following: a) Visual Display Unit (Monitor) b) Printer : Dot Matrix and Impact/Non Impact, Printer, Daisy wheel Printer, Line Printers, Ink-jet, Laser Printer c) Plotters etc.

20 L2. Central Processing Unit: The Central Processing Unit (CPU) is the heart of the computer combined in the sys with the processing system of a computer. The CPU carries out actions with information help of Arithmetic-Logic Unit (ALU). This is done following a detailed set of arithmetic instructions written in the main memory. It also uses the main memory for the memory temporary storage of information. Through the channels of information specified t Bus, the CPU instructs various parts called device controllers to transfer data between secondary memory and the main memory. The CPU accepts the data from the Input unit processes it and gives the result/output to the output device. The data/result can be stored for the use by storing it in the secondary emory. The total operations of the computer is synchronized and controlled by the CPU.

21 L2. Continue The processing capacity of a computer is measured in terms the amount of data processed by the CPU in one operation. The CPU has three important sub units. 1) Arithmetic-Logic unit 2) Control Unit 3) Memory Unit Arithmetic-Logic Unit (ALU): The ALU is an electronic circuit used to carry out the arithmetic operations like addition, subtraction, multiplication and division. This unit carries out logical operations like greater than, less than, be equal to etc. It performs the operation on the data provided by the input devices. A comparison operation allows a program to make decisions based on its data input and results of the previous calculations. Logical operations can be used to determine whether particular statement is re TRUE or FALSE.

22 L2. Memory Unit The main memory is also called primary memory, is used to store data temporarily. Although, the CPU is the brain behind all the operations in the computer, it needs to be supplied with the data to be processed and the instructions to tell it what to do. Once the CPU has carried out an instruction, it needs the result to be stored. This storage space is provided by the computer s memory. Data provided by the input device, and the result of that processed data is also stored in the memory nit. This main memory is like a scratch pad. The storage capacity of the memory is generally measured in megabytes.

23 L2. Memory Unit Different kinds of primary memory are Random Access Memory (RAM) and Read Only Memory (ROM). You can read and write data in RAM but the data is volatile or temporary that is whenever the power is switched off the contents of RAM is lost so its is required to store the data in the secondary memory if the data is required for the future use. But you can only read the data from ROM and you can not write any thing into it and the data is permanent. The manufacturer himself has written the data in it initially.

24 L2. Secondary Memory: This is the permanent memory. The data stored in it is permanent. But you can delete the data if you want. There are different kinds of secondary storage devices available. Few of them are Floppy disks, Fixed (hard) disks and Optical disks etc. a) Floppy Disk b) Fixed or Hard Disk c) Optical Disk like: CD (Compact Disk) DVD (Digital Versatile Disk) d) Magnetic Tape Drive

25 L3. Evolution of Computers, Von Neumann model ENIAC Background Electronic Numerical Integrator And Computer Eckert and Mauchly University of Pennsylvania Trajectory tables for weapons Started 1943 Finished 1946 Too late for war effort Used until 1955

26 L3. ENIAC ENIAC -details Decimal (not binary) 20 accumulators of 10 digits Programmed manually by switches 18,000 vacuum tubes Weight :30 tons Size: 15,000 square feet Power: 140 kw power consumption Speed:5,000 additions per second

27 L3. von Neumann/Turing Stored Program concept Main memory storing programs and data ALU operating on binary data Control unit interpreting instructions from memory and executing Input and output equipment operated by control unit Princeton Institute for Advanced Studies (IAS) computer Completed 1952

28 L3. Structure of Von Neumann Machine

29 L3. IAS -details 1000 x 40 bit words, each word representing One 40-bit binary number Two 20-bit instructions: 8 bits opcode 12 bits address Set of registers (storage in CPU) Memory Buffer Register Memory Address Register Instruction Register Instruction Buffer Register Program Counter Accumulator Multiplier Quotient

30 John von Neumann and the IAS machine, 1952

31 L3. IAS organization

32 L3. Commercial Computers Eckert-Mauchly Computer Corporation UNIVAC I(Universal Automatic Computer) US Bureau of Census 1950 calculations Became part of Sperry-Rand Corporation Late 1950s -UNIVAC II Faster More memory

33 L3. IBM Punched-card processing equipment the 701 IBM s first stored program computer Scientific calculations the 702 Business applications Lead to 700/7000 series

34 L3. Second generation of computers Transistors Replaced vacuum tubes Smaller Cheaper Less heat dissipation Solid State device Made from Silicon (Sand) Invented 1947 at Bell Labs by William Shockley et al.

35 L3. Transistor Based Computers NCR & RCA produced small transistor machines BM 7000 DEC (Digital Equipment Corporation) was founded in 957 Produced PDP-1 in the same year

36 L3. Third generation of computers: Integrated Circuits A computer is made up of gates, memory cells and interconnections All these can be manufactured either separately (discrete components) or on the same piece of semiconductor (a.k.a. silicon wafer)

37 L3. Generations of Computers Summary Vacuum tube ransistor Small scale integration on Up to 100 devices on a chip Medium scale integration -to ,000 devices on a chip Large scale integration , ,000 devices on a chip Very large scale integration , ,000,000 devices on a chip Ultra large scale integration 1991 Over 100,000,000 devices on a chip

38 L4. Performance measure of Computer Architecture Necessity of evaluation computer performance For comparing different computer performances User: Interested in reducing the execution time (response time) of a task. Computer centre administrator: throughput The computer user may say a computer is faster when a program runs in less time, while The computer centre manager may say a computer is faster when it completes more jobs in an hour

39 L4. TIME Time is the measure of computer performance The computer that performs the same amount of work in the least time is the fastest. Program execution time is measured in seconds per Program execution time is measured in seconds per program. But, since with multiprogramming the CPU works on another program while waiting for I/O CPUtime - the time CPU is computing (not including extra-time; e.g. time waiting for I/O or running other programs)

40 L4. A computer faster than another? when a program runs in less time (will say a computer user) the computer user is interested in reducing response time also referred to as execution time or latency. time also referred to as execution time or latency. when computer completes more jobs in an hour (will say computer centre manager) the computer centre manager is interested in increasing throughput the total amount of work done in a given time sometimes called bandwidth

41 L4. USE accurate terms: Response time, execution time and throughput utilized for evaluate an entire computing work Response time (execution time, latency): how long the computer responds to user input or finishes a program; the sooner the better A user sees the result in 5 second after inputting the keyword to a library database system A simulation program finishes in one hour Throughput: Amount of work done in a given time. Throughput = how much work a computer can finish for a given time; the higher the better A web server serves up to 5 million requests per second Why throughput: a system runs multiple jobs simultaneously Bandwidth and latency for memory performance

42 L5. Architecture of 8086 family 8086 CPU ARCHITECTURE The microprocessors functions as the CPU in the stored program model of the digital computer. Its job is to generate all system timing signals and synchronize the transfer of data between memory, I/O, and itself. It accomplishes this task via the three-bus system architecture previously discussed. The microprocessor also has a S/W function. It must recognize, decode, and execute program instructions fetched from the memory unit. This requires an Arithmetic-Logic Unit (ALU) within the CPU to perform arithmetic and logical (AND, OR, NOT, compare, etc) functions.

43 L5. Features of 8086 The most prominent features of a 8086 microprocessor are as follows It has an instruction queue, which is capable of storing six instruction bytes from the memory resulting in faster processing. It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus, and 16-bit external data bus resulting in faster processing. It is available in 3 versions based on the frequency of operation MHz MHz (c) MHz It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which improves performance. Fetch stage can prefetch up to 6 bytes of instructions and stores them in the queue. Execute stage executes these instructions. It has 256 vectored interrupts. It consists of 29,000 transistors.

44 L5. Architecture of 8086 family The 8086 CPU is organized as two separate processors, called the Bus Interface Unit (BIU) and the Execution Unit (EU). The BIU provides H/W functions, including generation of the memory and I/O addresses for the transfer of data between the outside world -outside the CPU, that isand the EU. The EU receives program instruction codes and data from the BIU, executes these instructions, and store the results in the general registers. By passing the data back to the BIU, data can also be stored in a memory location or written to an output device. Note that the EU has no connection to the system buses. It receives and outputs all its data thru the BIU.

46 L5. Continue.. The only difference between an 8088 microprocessor and an 8086 microprocessor is the BIU. In the 8088, the BIU data bus path is 8 bits wide versus the 8086's 16-bit data bus. Another difference is that the 8088 instruction queue is four bytes long instead of six. The important point to note, however, is that because the EU is the same for each processor, the programming instructions are exactly the same for each. Programs written for the 8086 can be run on the 8088 without any changes.

47 L5. Fetch and execute Although the 8086/88 still functions as a stored program computer, organization of the CPU into a separate BIU and EU allows the fetch and execute cycles to overlap. To see this, consider what happens when the 8086 or 8088 is first started. 1. The BIU outputs the contents of the instruction pointer register (IP) onto the address bus, causing the selected byte or word to be read into the BIU. 2. Register IP is incremented by 1 to prepare for the next instruction fetch. 3. Once inside the BIU, the instruction is passed to the queue. This is a first-in, first-out storage register sometimes likened to a "pipeline". 4. Assuming that the queue is initially empty, the EU immediately draws this instruction from the queue and begins execution. 5. While the EU is executing this instruction, the BIU proceeds to fetch a new instruction. Depending on the execution time of the first instruction, the BIU may fill the queue with several new instructions before the EU is ready to draw its next instruction.

48 L Hardware Design Minimum mode & Maximum mode of Operation The 8086 has a combined address and data bus commonly referred as a time multiplexed address and data bus. The main reason behind multiplexing address and data over the same pins is the maximum utilization of processor pins and it facilitates the use of 40 pin standard DIP package. The bus can be demultiplexed using a few latches and transreceivers, when ever required. Basically, all the processor bus cycles consist of at least four clock cycles. These are referred to as T1, T2, T3, T4. The address is transmitted by the processor during T1. It is present on the bus only for one cycle.

49 L6. Continue.. The negative edge of this ALE pulse is used to separate the address and the data or status information. In maximum mode, the status lines S0, S1 and S2 are used to indicate the type of operation. Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal. Address is valid during T1 while status bits S3 to S7 are valid during T2 through T4

50 L6. General Bus Cycle For 8086

51 L6. Minimum Mode 8086 System The microprocessor 8086 is operated in minimum mode by strapping its MN/MX pin to logic 1. In this mode, all the control signals are given out by the microprocessor chip itself. There is a single microprocessor in the minimum mode system. The remaining components in the system are latches, transreceivers, clock generator, memory and I/O devices. Latches are generally buffered output D-type flip-flops like74ls373 or They are used for separating the valid address from the multiplexed address/data signals and are controlled by the ALE signal generated by 8086.

52 L6. Minimum Mode Configuration For 8086

53 L6.Continue Transreceivers are the bidirectional buffers and some times they are called as data amplifiers. They are required to separate the valid data from the time multiplexed address/data signals. They are controlled by two signals namely, DEN and DT/R. The DEN signal indicates the direction of data, i.e. from or to the processor. The system contains memory for the monitor and users program storage. Usually, EPROM are used for monitor storage, while RAM for users program storage. A system may contain I/O devices. The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized in two parts, the first is the timing diagram for read cycle and the second is the timing diagram for write cycle. The read cycle begins in T1 with the assertion of address latch enable(ale) signal and also M / IO signal. During the negative going edge of this signal, the valid address is latched on the local bus.

54 L6. Continue The BHE and A0 signals address low, high or both bytes. FromT1 to T4, the M/IO signal indicates a memory or I/O operation. At T2, the address is removed from the local bus and is sent to the output. The bus is then tristated. The read (RD) control signal is also activated in T2. The read (RD) signal causes the address device to enable its data bus drivers. After RD goes low, the valid data is available on the data bus. The addressed device will drive the READY line high. When the processor returns the read signal to high level, the addressed device will again tristate its bus drivers.

55 L6. Continue A write cycle also begins with the assertion of ALE and the emission of the address. The M/IO signal is again asserted to indicate a memory or I/O operation. In T2, after sending the address in T1, the processors ends the data to be written to the addressed location. The data remains on the bus until middle of T4 state. The WR becomes active at the beginning of T2 (unlike RD is somewhat delayed in T2 to provide time for floating). The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O word to be read or write. The M/IO, RD and WR signals indicate the type of data transferas specified in table below.

57 L6. Maximum Mode 8086 System In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground. In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus controller derives the control signal using this status information. In the maximum mode, there may be more than one microprocessor in the system configuration. The components in the system are same as in the minimum mode system. The basic function of the bus controller chip IC8288, is to derive control signals like RD and WR ( for memory and I/O devices), DEN, DT/R, ALE etc. using the information by the processor on the status lines.

58 L6. Continue.. The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288 are driven by CPU. It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and AIOWC. The AEN, IOB and CEN pins are specially useful for multiprocessor systems. AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The significance of the MCE/PDEN output depends upon the status of the IOB pin. INTA pin used to issue two interrupt acknowledge pulses to the interrupt controller or to an interrupting device.

59 L6. Continue.. IORC, IOWC are I/O read command and I/O write command signals respectively. These signals enable an IO interface to read or write the data from or to the address port. The MRDC, MWTC are memory read command and memory write command signals respectively and may be used as memory read or write signals. All these command signals instructs the memory to accept or send data from or to the bus. Here the only difference between in timing diagram between minimum mode and maximum mode is the status signals used and the available control and advanced command signals.

61 L6. Continue.. R0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will output a pulse as on the ALE and apply a required signal to its DT / R pin during T1. In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate MRDC or IORC. These signals are activated until T4. For an output, the AMWC or AIOWC is activated from T2 to T4 and MWTC or IOWC is activated from T3 to T4. The status bit S0 to S2 remains active until T3 and become passive during T3 and T4. If reader input is not activated before T3, wait state will be inserted between T3 and T4.

64 L7. Study of bus controller 8288 & its use in Maximum mode The minimum mode signals, INTA, ALE, DEN, DT/ IT, M/ 10, WR, HLDA, and HOLD (on pins 24 to 31) that are essential for interfacing memory and I/O devices, are not available in the system if the 8086 is operated in maximum mode. An 8288 bus controller is used to generate the relevant signals for interfacing memory and I/O devices in the maximum mode. Figure (a) gives the block diagram of The bus controller has a command signal generator and a control signal generator. Figure (b) illustrates the maximum mode configuration of 8086 and the use of 8288 in 8086 based system. The 8288 input and output signals:

65 L7. Continue SO, SL and S2: The inputs (8086 Status outputs) are decoded to generate command signals. AEN: A low Address Enable signal activates the memory control signals. CEN: The Control Enable signal enables the 8288 command outputs. IOB: High on the I/O Bus input operates the 8288 in the I/O bus mode in systems where there are separate system bus and I/O bus. CLK: The Clock input DEN: The Data bus Enable signal controls the data bus buffers in the system. This signal is active-high in contrast to the DEN signal in the minimum mode.

67 ALE: The Address Latch Enable signal is used to de-multiplex address and data lines signals. DT/R: The Data Transmit/Receive signal controls bidirectional data bus buffer. MRDC, MWTC, IORC and lowc: The 8288 generates the normal Memory Read, Memory Write, I/O Read, I/O Write Control signals. AMWC, and AIOWC: These are Advanced Memory and Advanced I/O Write Control signals. INTA: The Interrupt Acknowledge output. MCE/PDEN: The Master Cascade Enable/Peripheral Data Enable output serves dual function. If IOB input is low it selects cascading of interrupt controllers, and if high enables the I/0 bus transceivers.

69 Difference between minimum and maximum mode

William Stallings Computer Organization and Architecture 8 th Edition. Chapter 2 Computer Evolution and Performance

William Stallings Computer Organization and Architecture 8 th Edition Chapter 2 Computer Evolution and Performance Analytical Engine ENIAC - background Electronic Numerical Integrator And Computer Eckert