Introduction. Computer System Organization. Languages, Levels, Virtual Machines. A multilevel machine. Sarjana Magister Program

Transcription

1 Computer System Organization Sarjana Magister Program Introduction Tb. Maulana Kusuma Week 1 Session 1 Languages, Levels, Virtual Machines A multilevel machine 1

2 Contemporary Multilevel Machines A six-level computer. The support method for each level is indicated below it. Evolution of Multilevel Machines Invention of microprogramming Invention of operating system Migration of functionality to microcode Elimination of microprogramming 2

3 Operating System Tasks A sample job for the FMS operating system Milestones in Computer Architecture (1) Some milestones in the development of the modern digital computer. 3

4 Milestones in Computer Architecture (2) Some milestones in the development of the modern digital computer. Computer Generations Zeroth Generation Mechanical Computers ( ) First Generation Vacuum Tubes ( ) Second Generation Transistors ( ) Third Generation Integrated Circuits ( ) Fourth Generation Very Large Scale Integration (1980?) 4

5 Von Neumann Machine The original Von Neumann machine. PDP-8 Innovation Single Bus The PDP-8 omnibus 5

6 IBM 360 The initial offering of the IBM product line. Technological and Economic Forces Moore s law predicts a 60-percent annual increase in the number of transistors that can be put on a chip. The data points given in this figure are memory sizes, in bits. 6

7 The Computer Spectrum The current spectrum of computers available. The prices should be taken with a grain (or better yet, a metric ton) of salt. Personal Computer 1. Pentium 4 socket P Support chip 3. Memory sockets 4. AGP connector 5. Disk interface 6. Gigabit Ethernet 7. Five PCI slots 8. USB 2.0 ports 9. Cooling technology 10. BIOS A printed circuit board is at the heart of every personal computer. This figure is a photograph of the Intel D875PBZ board. The photograph is copyrighted by the Intel Corporation, 2003 and is used by permission. 7

8 Example Computer Families Pentium 4 by Intel UltraSPARC III by Sun Microsystems The 8051 chip by Intel, used for embedded systems Intel Computer Family (1) The Intel CPU family. Clock speeds are measured in MHz (megahertz) where 1 MHZ is 1 million cycles/sec. 8

9 Intel Computer Family (2) The Pentium 4 chip. The photograph is copyrighted by the Intel Corporation, 2003 and is used by permission. Intel Computer Family (3) Moore s law for (Intel) CPU chips. 9

10 MCS-51 Family Members of the MCS-51 family. Metric Units The principal metric prefixes. 10

11 Architecture & Organization 1 Architecture is those attributes visible to the programmer Instruction set, number of bits used for data representation, I/O mechanisms, addressing techniques. e.g. Is there a multiply instruction? Organization is how features are implemented Control signals, interfaces, memory technology. e.g. Is there a hardware multiply unit or is it done by repeated addition? Architecture & Organization 2 All Intel x86 family share the same basic architecture The IBM System/370 family share the same basic architecture This gives code compatibility At least backwards Organization differs between different versions 11

12 Structure & Function Structure is the way in which components relate to each other Function is the operation of individual components as part of the structure Function All computer functions are: Data processing Data storage Data movement Control 12

13 Functional view Functional view of a computer Data Storage Facility Data Movement Apparatus Control Mechanism Data Processing Facility Operations (1) Data movement e.g. keyboard to screen Data Storage Facility Data Movement Apparatus Control Mechanism Data Processing Facility 13

14 Operations (2) Storage e.g. Internet download to disk Data Storage Facility Data Movement Apparatus Control Mechanism Data Processing Facility Operation (3) Processing from/to storage e.g. updating document Data Storage Facility Data Movement Apparatus Control Mechanism Data Processing Facility 14

15 Operation (4) Processing from storage to I/O e.g. printing a document Data Storage Facility Data Movement Apparatus Control Mechanism Data Processing Facility Structure - Top Level Peripherals Computer Central Processing Unit Main Memory Computer Systems Interconnection Communication lines Input Output 15

16 Structure - The CPU CPU I/O Computer System Bus Memory CPU Registers Internal CPU Interconnection Arithmetic and Logic Unit Control Unit Structure - The Control Unit Control Unit ALU CPU Internal Bus Registers Control Unit Sequencing Login Control Unit Registers and Decoders Control Memory 16

17 Computer System Organization Sarjana Magister Program Computer Systems Organization Tb. Maulana Kusuma Week 1 Session 2 Central Processing Unit The organization of a simple computer with one CPU and two I/O devices 17

18 CPU Organization The data path of a typical Von Neumann machine. Instruction Execution Steps 1. Fetch next instruction from memory into instruction register 2. Change program counter to point to next instruction 3. Determine type of instruction just fetched 4. If instructions uses word in memory, determine where Fetch word, if needed, into CPU register 5. Execute the instruction 6. Go to step 1 to begin executing following instruction 18

19 Interpreter (1)... An interpreter for a simple computer (written in Java). Interpreter (2) An interpreter for a simple computer (written in Java). 19

20 CPU components Memory Address Register: holds main memory addresses when fetching instructions or data CPU components Memory Data Register (Memory Buffer Register, MBR): stores instruction and data just fetched and data to be written to the main memory 20

21 CPU components Instruction Register: contains the instruction currently being executed CPU components Control Unit: generates control signals that cause the execution of an instruction or the fetch of another instruction 21

22 CPU components Arithmetic-Logic Unit: where calculations and manipulations take place CPU components General Purpose Registers: special memory cells for temporary storage of data 22

23 CPU components Program Counter: contains the address of the next instruction to be executed CPU components Processor Status Register (Processor Status Word, PSW): contains information about the state of the CPU 23

24 CPU components Fetch-Execute Cycle Defines how instructions are retrieved and executed inside the computer Sometimes called the Instruction Cycle or Automatic Sequence Control Fetch the instruction from memory to IR Increment the PC Execute the instruction in IR Repeat steps 1 to 3 until termination 24

25 CPU Execute the instruction Increment the PC PC Fetch-Execute Cycle Fetch next instruction from memory to IR IR Memory address data Fetch-Execute Cycle: Fetching Fetch Stage: Copy contents of PC into MAR Increment PC (point to the next instruction) Copy an instruction from MDR into IR 25

26 Fetch-Execute Cycle: Executing Execute Stage: Decode the instruction from IR Run the instruction in IR (may require getting data from the main memory) Unless the current instruction is HALT (stop), repeat the cycle Illustration 26

27 Design Principles for Modern Computers All instructions directly executed by hardware Maximize rate at which instructions are issued Instructions should be easy to decode Only loads, stores should reference memory Provide plenty of registers Instruction-Level Parallelism a) A five-stage pipeline b) The state of each stage as a function of time. Nine clock cycles are illustrated 27

28 Superscalar Architectures (1) Dual five-stage pipelines with a common instruction fetch unit. Superscalar Architectures (2) A superscalar processor with five functional units. 28

29 Processor-Level Parallelism (1) An array of processor of the ILLIAC IV type. Processor-Level Parallelism (2) a) A single-bus multiprocessor. b) A multicomputer with local memories. 29

30 Primary Memory Memory Addresses (1) Three ways of organizing a 96-bit memory. Primary Memory Memory Addresses (2) Number of bits per cell for some historically interesting commercial computers 30

31 Byte Ordering (1) (a) Big endian memory (b) Little endian memory Byte Ordering (2) (a) A personal record for a big endian machine. (b) The same record for a little endian machine. (c) The result of transferring from big endian to little endian. (d) The result of byte-swapping (c). 31

32 Error Correcting Codes (1) Number of check bits for a code that can correct a single error Error Correcting Codes (2) (a) Encoding of 1100 (b) Even parity added (c) Error in AC 32

33 Error Correcting Codes (3) Construction of the Hamming code for the memory word by adding 5 check bits to the 16 data bits. Cache Memory The cache is logically between the CPU and main memory. Physically, there are several possible places it could be located. 33

34 Memory Packaging and Types A single inline memory module (SIMM) holding 256 MB. Two of the chips control the SIMM. Memory Hierarchies A five-level memory hierarchy. 34

35 Magnetic Disks (1) A portion of a disk track. Two sectors are illustrated. Magnetic Disks (2) A disk with four platters. 35

36 Magnetic Disks (3) A disk with five zones. Each zone has many tracks. SCSI Disks Some of the possible SCSI parameters. 36

37 RAID (1) Redundant Array of Inexpensive Disks RAID levels 0 through 2. Backup and parity disks are shown shaded. RAID (1) Redundant Array of Inexpensive Disks RAID levels 3 through 5. Backup and parity disks are shown shaded. 37

38 CD-ROMs (1) Recording structure of a Compact Disk or CD-ROM. CD-ROMs (2) Logical data layout on a CD-ROM. 38

39 CD-Recordables Cross section of a CD-R disk and laser (not to scale). A CD-ROM has a similar structure, except without the dye layer and with a pitted aluminum layer instead of a reflective layer. DVD A double-sided, dual layer DVD disk. 39

40 Input/Output Buses (1) Physical structure of a personal computer. Input/Output Buses (2) Logical structure of a simple personal computer. 40

41 Input/Output Buses (3) A typical modern PC with a PCI bus and an ISA bus. CRT Monitors (a) Cross section of a CRT (b) CRT scanning pattern 41

42 Flat Panel Displays (a) The construction of an LCD screen. (b) The grooves on the rear and front plates are perpendicular to one another. Mice A mouse being used to point to menu items. 42

43 Printers (1) (a) The letter A on a 5 x 7 matrix. (b) The letter A printed with 24 overlapping needles. Printers (2) Operation of a laser printer. 43

44 Printers (3) Halftone dots for various gray scale ranges. (a) 0 6. (b) (c) (d) (e) (f) Telecommunications a) Transmission of the binary number over a b) telephone line bit by bit. (a) Two-level signal. (b) Amplitude c) modulation. (c) Frequency modulation. (d) Phase modulation. 44

45 Digital Subscriber Lines (1) Operation of ADSL. Digital Subscriber Lines (2) A typical ADSL equipment configuration. 45

46 Internet over Cable (1) Frequency allocation in a typical cable TV system used for Internet access Internet over Cable (2) Typical details of the upstream and downstream channels in North America. QAM-64 (Quadrature Amplitude Modulation) allows 6 bits/hz but only works at high frequencies. QPSK (Quadrature Phase Shift Keying) works at low frequencies but allows only 2 bits/hz. 46

47 Digital Cameras A digital camera. ASCII Character Codes (1) The ASCII Character set: characters

48 ASCII Character Codes (2) The ASCII Character set: characters